bus_defs.h revision 1.1.12.2
1 /* $NetBSD: bus_defs.h,v 1.1.12.2 2013/02/25 00:28:29 tls Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 35 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Christopher G. Demetriou 48 * for the NetBSD Project. 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 #ifndef _ARM32_BUS_DEFS_H_ 65 #define _ARM32_BUS_DEFS_H_ 66 67 #if defined(_KERNEL_OPT) 68 #include "opt_arm_bus_space.h" 69 #endif 70 71 /* 72 * Addresses (in bus space). 73 */ 74 typedef u_long bus_addr_t; 75 typedef u_long bus_size_t; 76 77 #define PRIxBUSADDR "lx" 78 #define PRIxBUSSIZE "lx" 79 #define PRIuBUSSIZE "lu" 80 81 /* 82 * Access methods for bus space. 83 */ 84 typedef struct bus_space *bus_space_tag_t; 85 typedef u_long bus_space_handle_t; 86 87 #define PRIxBSH "lx" 88 89 /* 90 * int bus_space_map(bus_space_tag_t t, bus_addr_t addr, 91 * bus_size_t size, int flags, bus_space_handle_t *bshp); 92 * 93 * Map a region of bus space. 94 */ 95 96 #define BUS_SPACE_MAP_CACHEABLE 0x01 97 #define BUS_SPACE_MAP_LINEAR 0x02 98 #define BUS_SPACE_MAP_PREFETCHABLE 0x04 99 100 struct bus_space { 101 /* cookie */ 102 void *bs_cookie; 103 104 /* mapping/unmapping */ 105 int (*bs_map)(void *, bus_addr_t, bus_size_t, 106 int, bus_space_handle_t *); 107 void (*bs_unmap)(void *, bus_space_handle_t, 108 bus_size_t); 109 int (*bs_subregion)(void *, bus_space_handle_t, 110 bus_size_t, bus_size_t, bus_space_handle_t *); 111 112 /* allocation/deallocation */ 113 int (*bs_alloc)(void *, bus_addr_t, bus_addr_t, 114 bus_size_t, bus_size_t, bus_size_t, int, 115 bus_addr_t *, bus_space_handle_t *); 116 void (*bs_free)(void *, bus_space_handle_t, 117 bus_size_t); 118 119 /* get kernel virtual address */ 120 void * (*bs_vaddr)(void *, bus_space_handle_t); 121 122 /* mmap bus space for user */ 123 paddr_t (*bs_mmap)(void *, bus_addr_t, off_t, int, int); 124 125 /* barrier */ 126 void (*bs_barrier)(void *, bus_space_handle_t, 127 bus_size_t, bus_size_t, int); 128 129 /* read (single) */ 130 uint8_t (*bs_r_1)(void *, bus_space_handle_t, 131 bus_size_t); 132 uint16_t (*bs_r_2)(void *, bus_space_handle_t, 133 bus_size_t); 134 uint32_t (*bs_r_4)(void *, bus_space_handle_t, 135 bus_size_t); 136 uint64_t (*bs_r_8)(void *, bus_space_handle_t, 137 bus_size_t); 138 139 /* read multiple */ 140 void (*bs_rm_1)(void *, bus_space_handle_t, 141 bus_size_t, uint8_t *, bus_size_t); 142 void (*bs_rm_2)(void *, bus_space_handle_t, 143 bus_size_t, uint16_t *, bus_size_t); 144 void (*bs_rm_4)(void *, bus_space_handle_t, 145 bus_size_t, uint32_t *, bus_size_t); 146 void (*bs_rm_8)(void *, bus_space_handle_t, 147 bus_size_t, uint64_t *, bus_size_t); 148 149 /* read region */ 150 void (*bs_rr_1)(void *, bus_space_handle_t, 151 bus_size_t, uint8_t *, bus_size_t); 152 void (*bs_rr_2)(void *, bus_space_handle_t, 153 bus_size_t, uint16_t *, bus_size_t); 154 void (*bs_rr_4)(void *, bus_space_handle_t, 155 bus_size_t, uint32_t *, bus_size_t); 156 void (*bs_rr_8)(void *, bus_space_handle_t, 157 bus_size_t, uint64_t *, bus_size_t); 158 159 /* write (single) */ 160 void (*bs_w_1)(void *, bus_space_handle_t, 161 bus_size_t, uint8_t); 162 void (*bs_w_2)(void *, bus_space_handle_t, 163 bus_size_t, uint16_t); 164 void (*bs_w_4)(void *, bus_space_handle_t, 165 bus_size_t, uint32_t); 166 void (*bs_w_8)(void *, bus_space_handle_t, 167 bus_size_t, uint64_t); 168 169 /* write multiple */ 170 void (*bs_wm_1)(void *, bus_space_handle_t, 171 bus_size_t, const uint8_t *, bus_size_t); 172 void (*bs_wm_2)(void *, bus_space_handle_t, 173 bus_size_t, const uint16_t *, bus_size_t); 174 void (*bs_wm_4)(void *, bus_space_handle_t, 175 bus_size_t, const uint32_t *, bus_size_t); 176 void (*bs_wm_8)(void *, bus_space_handle_t, 177 bus_size_t, const uint64_t *, bus_size_t); 178 179 /* write region */ 180 void (*bs_wr_1)(void *, bus_space_handle_t, 181 bus_size_t, const uint8_t *, bus_size_t); 182 void (*bs_wr_2)(void *, bus_space_handle_t, 183 bus_size_t, const uint16_t *, bus_size_t); 184 void (*bs_wr_4)(void *, bus_space_handle_t, 185 bus_size_t, const uint32_t *, bus_size_t); 186 void (*bs_wr_8)(void *, bus_space_handle_t, 187 bus_size_t, const uint64_t *, bus_size_t); 188 189 /* set multiple */ 190 void (*bs_sm_1)(void *, bus_space_handle_t, 191 bus_size_t, uint8_t, bus_size_t); 192 void (*bs_sm_2)(void *, bus_space_handle_t, 193 bus_size_t, uint16_t, bus_size_t); 194 void (*bs_sm_4)(void *, bus_space_handle_t, 195 bus_size_t, uint32_t, bus_size_t); 196 void (*bs_sm_8)(void *, bus_space_handle_t, 197 bus_size_t, uint64_t, bus_size_t); 198 199 /* set region */ 200 void (*bs_sr_1)(void *, bus_space_handle_t, 201 bus_size_t, uint8_t, bus_size_t); 202 void (*bs_sr_2)(void *, bus_space_handle_t, 203 bus_size_t, uint16_t, bus_size_t); 204 void (*bs_sr_4)(void *, bus_space_handle_t, 205 bus_size_t, uint32_t, bus_size_t); 206 void (*bs_sr_8)(void *, bus_space_handle_t, 207 bus_size_t, uint64_t, bus_size_t); 208 209 /* copy */ 210 void (*bs_c_1)(void *, bus_space_handle_t, bus_size_t, 211 bus_space_handle_t, bus_size_t, bus_size_t); 212 void (*bs_c_2)(void *, bus_space_handle_t, bus_size_t, 213 bus_space_handle_t, bus_size_t, bus_size_t); 214 void (*bs_c_4)(void *, bus_space_handle_t, bus_size_t, 215 bus_space_handle_t, bus_size_t, bus_size_t); 216 void (*bs_c_8)(void *, bus_space_handle_t, bus_size_t, 217 bus_space_handle_t, bus_size_t, bus_size_t); 218 219 #ifdef __BUS_SPACE_HAS_STREAM_METHODS 220 /* read stream (single) */ 221 uint8_t (*bs_r_1_s)(void *, bus_space_handle_t, 222 bus_size_t); 223 uint16_t (*bs_r_2_s)(void *, bus_space_handle_t, 224 bus_size_t); 225 uint32_t (*bs_r_4_s)(void *, bus_space_handle_t, 226 bus_size_t); 227 uint64_t (*bs_r_8_s)(void *, bus_space_handle_t, 228 bus_size_t); 229 230 /* read multiple stream */ 231 void (*bs_rm_1_s)(void *, bus_space_handle_t, 232 bus_size_t, uint8_t *, bus_size_t); 233 void (*bs_rm_2_s)(void *, bus_space_handle_t, 234 bus_size_t, uint16_t *, bus_size_t); 235 void (*bs_rm_4_s)(void *, bus_space_handle_t, 236 bus_size_t, uint32_t *, bus_size_t); 237 void (*bs_rm_8_s)(void *, bus_space_handle_t, 238 bus_size_t, uint64_t *, bus_size_t); 239 240 /* read region stream */ 241 void (*bs_rr_1_s)(void *, bus_space_handle_t, 242 bus_size_t, uint8_t *, bus_size_t); 243 void (*bs_rr_2_s)(void *, bus_space_handle_t, 244 bus_size_t, uint16_t *, bus_size_t); 245 void (*bs_rr_4_s)(void *, bus_space_handle_t, 246 bus_size_t, uint32_t *, bus_size_t); 247 void (*bs_rr_8_s)(void *, bus_space_handle_t, 248 bus_size_t, uint64_t *, bus_size_t); 249 250 /* write stream (single) */ 251 void (*bs_w_1_s)(void *, bus_space_handle_t, 252 bus_size_t, uint8_t); 253 void (*bs_w_2_s)(void *, bus_space_handle_t, 254 bus_size_t, uint16_t); 255 void (*bs_w_4_s)(void *, bus_space_handle_t, 256 bus_size_t, uint32_t); 257 void (*bs_w_8_s)(void *, bus_space_handle_t, 258 bus_size_t, uint64_t); 259 260 /* write multiple stream */ 261 void (*bs_wm_1_s)(void *, bus_space_handle_t, 262 bus_size_t, const uint8_t *, bus_size_t); 263 void (*bs_wm_2_s)(void *, bus_space_handle_t, 264 bus_size_t, const uint16_t *, bus_size_t); 265 void (*bs_wm_4_s)(void *, bus_space_handle_t, 266 bus_size_t, const uint32_t *, bus_size_t); 267 void (*bs_wm_8_s)(void *, bus_space_handle_t, 268 bus_size_t, const uint64_t *, bus_size_t); 269 270 /* write region stream */ 271 void (*bs_wr_1_s)(void *, bus_space_handle_t, 272 bus_size_t, const uint8_t *, bus_size_t); 273 void (*bs_wr_2_s)(void *, bus_space_handle_t, 274 bus_size_t, const uint16_t *, bus_size_t); 275 void (*bs_wr_4_s)(void *, bus_space_handle_t, 276 bus_size_t, const uint32_t *, bus_size_t); 277 void (*bs_wr_8_s)(void *, bus_space_handle_t, 278 bus_size_t, const uint64_t *, bus_size_t); 279 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 280 }; 281 282 #define BUS_SPACE_BARRIER_READ 0x01 283 #define BUS_SPACE_BARRIER_WRITE 0x02 284 285 #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) 286 287 /* Bus Space DMA macros */ 288 289 /* 290 * Flags used in various bus DMA methods. 291 */ 292 #define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */ 293 #define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */ 294 #define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */ 295 #define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */ 296 #define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */ 297 #define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */ 298 #define BUS_DMA_BUS2 0x020 299 #define BUS_DMA_BUS3 0x040 300 #define BUS_DMA_BUS4 0x080 301 #define BUS_DMA_READ 0x100 /* mapping is device -> memory only */ 302 #define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */ 303 #define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */ 304 305 /* 306 * Private flags stored in the DMA map. 307 */ 308 #define _BUS_DMAMAP_COHERENT 0x10000 /* no cache flush necessary on sync */ 309 #define _BUS_DMAMAP_IS_BOUNCING 0x20000 /* is bouncing current xfer */ 310 #define _BUS_DMAMAP_NOALLOC 0x40000 /* don't alloc memory from this range */ 311 312 /* Forwards needed by prototypes below. */ 313 struct mbuf; 314 struct uio; 315 316 /* 317 * Operations performed by bus_dmamap_sync(). 318 */ 319 #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */ 320 #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */ 321 #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */ 322 #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */ 323 324 typedef struct arm32_bus_dma_tag *bus_dma_tag_t; 325 typedef struct arm32_bus_dmamap *bus_dmamap_t; 326 327 #define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) 328 329 /* 330 * bus_dma_segment_t 331 * 332 * Describes a single contiguous DMA transaction. Values 333 * are suitable for programming into DMA registers. 334 */ 335 struct arm32_bus_dma_segment { 336 /* 337 * PUBLIC MEMBERS: these are used by machine-independent code. 338 */ 339 bus_addr_t ds_addr; /* DMA address */ 340 bus_size_t ds_len; /* length of transfer */ 341 uint32_t _ds_flags; /* _BUS_DMAMAP_COHERENT */ 342 }; 343 typedef struct arm32_bus_dma_segment bus_dma_segment_t; 344 345 /* 346 * arm32_dma_range 347 * 348 * This structure describes a valid DMA range. 349 */ 350 struct arm32_dma_range { 351 bus_addr_t dr_sysbase; /* system base address */ 352 bus_addr_t dr_busbase; /* appears here on bus */ 353 bus_size_t dr_len; /* length of range */ 354 uint32_t dr_flags; /* flags for range */ 355 }; 356 357 /* 358 * bus_dma_tag_t 359 * 360 * A machine-dependent opaque type describing the implementation of 361 * DMA for a given bus. 362 */ 363 364 struct arm32_bus_dma_tag { 365 /* 366 * DMA range for this tag. If the page doesn't fall within 367 * one of these ranges, an error is returned. The caller 368 * may then decide what to do with the transfer. If the 369 * range pointer is NULL, it is ignored. 370 */ 371 struct arm32_dma_range *_ranges; 372 int _nranges; 373 374 /* 375 * Opaque cookie for use by back-end. 376 */ 377 void *_cookie; 378 379 /* 380 * DMA mapping methods. 381 */ 382 int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int, 383 bus_size_t, bus_size_t, int, bus_dmamap_t *); 384 void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t); 385 int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *, 386 bus_size_t, struct proc *, int); 387 int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t, 388 struct mbuf *, int); 389 int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t, 390 struct uio *, int); 391 int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t, 392 bus_dma_segment_t *, int, bus_size_t, int); 393 void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t); 394 void (*_dmamap_sync_pre)(bus_dma_tag_t, bus_dmamap_t, 395 bus_addr_t, bus_size_t, int); 396 void (*_dmamap_sync_post)(bus_dma_tag_t, bus_dmamap_t, 397 bus_addr_t, bus_size_t, int); 398 399 /* 400 * DMA memory utility functions. 401 */ 402 int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t, 403 bus_size_t, bus_dma_segment_t *, int, int *, int); 404 void (*_dmamem_free)(bus_dma_tag_t, 405 bus_dma_segment_t *, int); 406 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *, 407 int, size_t, void **, int); 408 void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t); 409 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *, 410 int, off_t, int, int); 411 412 /* 413 * DMA tag utility functions 414 */ 415 int (*_dmatag_subregion)(bus_dma_tag_t, bus_addr_t, bus_addr_t, 416 bus_dma_tag_t *, int); 417 void (*_dmatag_destroy)(bus_dma_tag_t); 418 419 /* 420 * State for bounce buffers 421 */ 422 int _tag_needs_free; 423 int (*_may_bounce)(bus_dma_tag_t, bus_dmamap_t, int, int *); 424 }; 425 426 /* 427 * bus_dmamap_t 428 * 429 * Describes a DMA mapping. 430 */ 431 struct arm32_bus_dmamap { 432 /* 433 * PRIVATE MEMBERS: not for use by machine-independent code. 434 */ 435 bus_size_t _dm_size; /* largest DMA transfer mappable */ 436 int _dm_segcnt; /* number of segs this map can map */ 437 bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */ 438 bus_size_t _dm_boundary; /* don't cross this */ 439 int _dm_flags; /* misc. flags */ 440 441 void *_dm_origbuf; /* pointer to original buffer */ 442 int _dm_buftype; /* type of buffer */ 443 struct vmspace *_dm_vmspace; /* vmspace that owns the mapping */ 444 445 void *_dm_cookie; /* cookie for bus-specific functions */ 446 447 /* 448 * PUBLIC MEMBERS: these are used by machine-independent code. 449 */ 450 bus_size_t dm_maxsegsz; /* largest possible segment */ 451 bus_size_t dm_mapsize; /* size of the mapping */ 452 int dm_nsegs; /* # valid segments in mapping */ 453 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 454 }; 455 456 /* _dm_buftype */ 457 #define _BUS_DMA_BUFTYPE_INVALID 0 458 #define _BUS_DMA_BUFTYPE_LINEAR 1 459 #define _BUS_DMA_BUFTYPE_MBUF 2 460 #define _BUS_DMA_BUFTYPE_UIO 3 461 #define _BUS_DMA_BUFTYPE_RAW 4 462 463 #ifdef _ARM32_BUS_DMA_PRIVATE 464 #define _BUS_AVAIL_END physical_end 465 /* 466 * Cookie used for bounce buffers. A pointer to one of these it stashed in 467 * the DMA map. 468 */ 469 struct arm32_bus_dma_cookie { 470 int id_flags; /* flags; see below */ 471 472 /* 473 * Information about the original buffer used during 474 * DMA map syncs. Note that origibuflen is only used 475 * for ID_BUFTYPE_LINEAR. 476 */ 477 union { 478 void *un_origbuf; /* pointer to orig buffer if 479 bouncing */ 480 char *un_linearbuf; 481 struct mbuf *un_mbuf; 482 struct uio *un_uio; 483 } id_origbuf_un; 484 #define id_origbuf id_origbuf_un.un_origbuf 485 #define id_origlinearbuf id_origbuf_un.un_linearbuf 486 #define id_origmbuf id_origbuf_un.un_mbuf 487 #define id_origuio id_origbuf_un.un_uio 488 bus_size_t id_origbuflen; /* ...and size */ 489 490 void *id_bouncebuf; /* pointer to the bounce buffer */ 491 bus_size_t id_bouncebuflen; /* ...and size */ 492 int id_nbouncesegs; /* number of valid bounce segs */ 493 bus_dma_segment_t id_bouncesegs[0]; /* array of bounce buffer 494 physical memory segments */ 495 }; 496 497 /* id_flags */ 498 #define _BUS_DMA_IS_BOUNCING 0x04 /* is bouncing current xfer */ 499 #define _BUS_DMA_HAS_BOUNCE 0x02 /* has bounce buffers */ 500 #endif /* _ARM32_BUS_DMA_PRIVATE */ 501 #define _BUS_DMA_MIGHT_NEED_BOUNCE 0x01 /* may need bounce buffers */ 502 503 #endif /* _ARM32_BUS_DEFS_H_ */ 504
Indexes created Sat Nov 01 21:09:44 GMT 2025