bus_defs.h revision 1.11.2.2
1 /* $NetBSD: bus_defs.h,v 1.11.2.2 2020/04/08 14:07:29 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 35 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Christopher G. Demetriou 48 * for the NetBSD Project. 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 #ifndef _ARM_BUS_DEFS_H_ 65 #define _ARM_BUS_DEFS_H_ 66 67 #if defined(_KERNEL_OPT) 68 #include "opt_arm_bus_space.h" 69 #endif 70 71 /* 72 * Addresses (in bus space). 73 */ 74 typedef u_long bus_addr_t; 75 typedef u_long bus_size_t; 76 77 #define PRIxBUSADDR "lx" 78 #define PRIxBUSSIZE "lx" 79 #define PRIuBUSSIZE "lu" 80 81 /* 82 * Access methods for bus space. 83 */ 84 typedef struct bus_space *bus_space_tag_t; 85 typedef u_long bus_space_handle_t; 86 87 #define PRIxBSH "lx" 88 89 /* 90 * int bus_space_map(bus_space_tag_t t, bus_addr_t addr, 91 * bus_size_t size, int flags, bus_space_handle_t *bshp); 92 * 93 * Map a region of bus space. 94 */ 95 96 #define BUS_SPACE_MAP_CACHEABLE 0x01 97 #define BUS_SPACE_MAP_LINEAR 0x02 98 #define BUS_SPACE_MAP_PREFETCHABLE 0x04 99 100 #define BUS_SPACE_MAP_BUS1 0x0100 101 #define BUS_SPACE_MAP_BUS2 0x0200 102 #define BUS_SPACE_MAP_BUS3 0x0400 103 #define BUS_SPACE_MAP_BUS4 0x0800 104 105 #define _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED BUS_SPACE_MAP_BUS1 106 107 struct bus_space { 108 /* cookie */ 109 void *bs_cookie; 110 111 /* used for aarch64. require ".bs_cookie = bus_space" */ 112 int bs_stride; /* offset <<= bs_stride (if needed) */ 113 int bs_flags; 114 115 /* mapping/unmapping */ 116 int (*bs_map)(void *, bus_addr_t, bus_size_t, 117 int, bus_space_handle_t *); 118 void (*bs_unmap)(void *, bus_space_handle_t, 119 bus_size_t); 120 int (*bs_subregion)(void *, bus_space_handle_t, 121 bus_size_t, bus_size_t, bus_space_handle_t *); 122 123 /* allocation/deallocation */ 124 int (*bs_alloc)(void *, bus_addr_t, bus_addr_t, 125 bus_size_t, bus_size_t, bus_size_t, int, 126 bus_addr_t *, bus_space_handle_t *); 127 void (*bs_free)(void *, bus_space_handle_t, 128 bus_size_t); 129 130 /* get kernel virtual address */ 131 void * (*bs_vaddr)(void *, bus_space_handle_t); 132 133 /* mmap bus space for user */ 134 paddr_t (*bs_mmap)(void *, bus_addr_t, off_t, int, int); 135 136 /* barrier */ 137 void (*bs_barrier)(void *, bus_space_handle_t, 138 bus_size_t, bus_size_t, int); 139 140 /* read (single) */ 141 uint8_t (*bs_r_1)(void *, bus_space_handle_t, 142 bus_size_t); 143 uint16_t (*bs_r_2)(void *, bus_space_handle_t, 144 bus_size_t); 145 uint32_t (*bs_r_4)(void *, bus_space_handle_t, 146 bus_size_t); 147 uint64_t (*bs_r_8)(void *, bus_space_handle_t, 148 bus_size_t); 149 150 /* read multiple */ 151 void (*bs_rm_1)(void *, bus_space_handle_t, 152 bus_size_t, uint8_t *, bus_size_t); 153 void (*bs_rm_2)(void *, bus_space_handle_t, 154 bus_size_t, uint16_t *, bus_size_t); 155 void (*bs_rm_4)(void *, bus_space_handle_t, 156 bus_size_t, uint32_t *, bus_size_t); 157 void (*bs_rm_8)(void *, bus_space_handle_t, 158 bus_size_t, uint64_t *, bus_size_t); 159 160 /* read region */ 161 void (*bs_rr_1)(void *, bus_space_handle_t, 162 bus_size_t, uint8_t *, bus_size_t); 163 void (*bs_rr_2)(void *, bus_space_handle_t, 164 bus_size_t, uint16_t *, bus_size_t); 165 void (*bs_rr_4)(void *, bus_space_handle_t, 166 bus_size_t, uint32_t *, bus_size_t); 167 void (*bs_rr_8)(void *, bus_space_handle_t, 168 bus_size_t, uint64_t *, bus_size_t); 169 170 /* write (single) */ 171 void (*bs_w_1)(void *, bus_space_handle_t, 172 bus_size_t, uint8_t); 173 void (*bs_w_2)(void *, bus_space_handle_t, 174 bus_size_t, uint16_t); 175 void (*bs_w_4)(void *, bus_space_handle_t, 176 bus_size_t, uint32_t); 177 void (*bs_w_8)(void *, bus_space_handle_t, 178 bus_size_t, uint64_t); 179 180 /* write multiple */ 181 void (*bs_wm_1)(void *, bus_space_handle_t, 182 bus_size_t, const uint8_t *, bus_size_t); 183 void (*bs_wm_2)(void *, bus_space_handle_t, 184 bus_size_t, const uint16_t *, bus_size_t); 185 void (*bs_wm_4)(void *, bus_space_handle_t, 186 bus_size_t, const uint32_t *, bus_size_t); 187 void (*bs_wm_8)(void *, bus_space_handle_t, 188 bus_size_t, const uint64_t *, bus_size_t); 189 190 /* write region */ 191 void (*bs_wr_1)(void *, bus_space_handle_t, 192 bus_size_t, const uint8_t *, bus_size_t); 193 void (*bs_wr_2)(void *, bus_space_handle_t, 194 bus_size_t, const uint16_t *, bus_size_t); 195 void (*bs_wr_4)(void *, bus_space_handle_t, 196 bus_size_t, const uint32_t *, bus_size_t); 197 void (*bs_wr_8)(void *, bus_space_handle_t, 198 bus_size_t, const uint64_t *, bus_size_t); 199 200 /* set multiple */ 201 void (*bs_sm_1)(void *, bus_space_handle_t, 202 bus_size_t, uint8_t, bus_size_t); 203 void (*bs_sm_2)(void *, bus_space_handle_t, 204 bus_size_t, uint16_t, bus_size_t); 205 void (*bs_sm_4)(void *, bus_space_handle_t, 206 bus_size_t, uint32_t, bus_size_t); 207 void (*bs_sm_8)(void *, bus_space_handle_t, 208 bus_size_t, uint64_t, bus_size_t); 209 210 /* set region */ 211 void (*bs_sr_1)(void *, bus_space_handle_t, 212 bus_size_t, uint8_t, bus_size_t); 213 void (*bs_sr_2)(void *, bus_space_handle_t, 214 bus_size_t, uint16_t, bus_size_t); 215 void (*bs_sr_4)(void *, bus_space_handle_t, 216 bus_size_t, uint32_t, bus_size_t); 217 void (*bs_sr_8)(void *, bus_space_handle_t, 218 bus_size_t, uint64_t, bus_size_t); 219 220 /* copy */ 221 void (*bs_c_1)(void *, bus_space_handle_t, bus_size_t, 222 bus_space_handle_t, bus_size_t, bus_size_t); 223 void (*bs_c_2)(void *, bus_space_handle_t, bus_size_t, 224 bus_space_handle_t, bus_size_t, bus_size_t); 225 void (*bs_c_4)(void *, bus_space_handle_t, bus_size_t, 226 bus_space_handle_t, bus_size_t, bus_size_t); 227 void (*bs_c_8)(void *, bus_space_handle_t, bus_size_t, 228 bus_space_handle_t, bus_size_t, bus_size_t); 229 230 #ifdef __BUS_SPACE_HAS_STREAM_METHODS 231 /* read stream (single) */ 232 uint8_t (*bs_r_1_s)(void *, bus_space_handle_t, 233 bus_size_t); 234 uint16_t (*bs_r_2_s)(void *, bus_space_handle_t, 235 bus_size_t); 236 uint32_t (*bs_r_4_s)(void *, bus_space_handle_t, 237 bus_size_t); 238 uint64_t (*bs_r_8_s)(void *, bus_space_handle_t, 239 bus_size_t); 240 241 /* read multiple stream */ 242 void (*bs_rm_1_s)(void *, bus_space_handle_t, 243 bus_size_t, uint8_t *, bus_size_t); 244 void (*bs_rm_2_s)(void *, bus_space_handle_t, 245 bus_size_t, uint16_t *, bus_size_t); 246 void (*bs_rm_4_s)(void *, bus_space_handle_t, 247 bus_size_t, uint32_t *, bus_size_t); 248 void (*bs_rm_8_s)(void *, bus_space_handle_t, 249 bus_size_t, uint64_t *, bus_size_t); 250 251 /* read region stream */ 252 void (*bs_rr_1_s)(void *, bus_space_handle_t, 253 bus_size_t, uint8_t *, bus_size_t); 254 void (*bs_rr_2_s)(void *, bus_space_handle_t, 255 bus_size_t, uint16_t *, bus_size_t); 256 void (*bs_rr_4_s)(void *, bus_space_handle_t, 257 bus_size_t, uint32_t *, bus_size_t); 258 void (*bs_rr_8_s)(void *, bus_space_handle_t, 259 bus_size_t, uint64_t *, bus_size_t); 260 261 /* write stream (single) */ 262 void (*bs_w_1_s)(void *, bus_space_handle_t, 263 bus_size_t, uint8_t); 264 void (*bs_w_2_s)(void *, bus_space_handle_t, 265 bus_size_t, uint16_t); 266 void (*bs_w_4_s)(void *, bus_space_handle_t, 267 bus_size_t, uint32_t); 268 void (*bs_w_8_s)(void *, bus_space_handle_t, 269 bus_size_t, uint64_t); 270 271 /* write multiple stream */ 272 void (*bs_wm_1_s)(void *, bus_space_handle_t, 273 bus_size_t, const uint8_t *, bus_size_t); 274 void (*bs_wm_2_s)(void *, bus_space_handle_t, 275 bus_size_t, const uint16_t *, bus_size_t); 276 void (*bs_wm_4_s)(void *, bus_space_handle_t, 277 bus_size_t, const uint32_t *, bus_size_t); 278 void (*bs_wm_8_s)(void *, bus_space_handle_t, 279 bus_size_t, const uint64_t *, bus_size_t); 280 281 /* write region stream */ 282 void (*bs_wr_1_s)(void *, bus_space_handle_t, 283 bus_size_t, const uint8_t *, bus_size_t); 284 void (*bs_wr_2_s)(void *, bus_space_handle_t, 285 bus_size_t, const uint16_t *, bus_size_t); 286 void (*bs_wr_4_s)(void *, bus_space_handle_t, 287 bus_size_t, const uint32_t *, bus_size_t); 288 void (*bs_wr_8_s)(void *, bus_space_handle_t, 289 bus_size_t, const uint64_t *, bus_size_t); 290 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 291 292 #ifdef __BUS_SPACE_HAS_PROBING_METHODS 293 /* peek */ 294 int (*bs_pe_1)(void *, bus_space_handle_t, 295 bus_size_t, uint8_t *); 296 int (*bs_pe_2)(void *, bus_space_handle_t, 297 bus_size_t, uint16_t *); 298 int (*bs_pe_4)(void *, bus_space_handle_t, 299 bus_size_t, uint32_t *); 300 int (*bs_pe_8)(void *, bus_space_handle_t, 301 bus_size_t, uint64_t *); 302 303 /* poke */ 304 int (*bs_po_1)(void *, bus_space_handle_t, 305 bus_size_t, uint8_t); 306 int (*bs_po_2)(void *, bus_space_handle_t, 307 bus_size_t, uint16_t); 308 int (*bs_po_4)(void *, bus_space_handle_t, 309 bus_size_t, uint32_t); 310 int (*bs_po_8)(void *, bus_space_handle_t, 311 bus_size_t, uint64_t); 312 #endif /* __BUS_SPACE_HAS_PROBING_METHODS */ 313 }; 314 315 #define BUS_SPACE_BARRIER_READ 0x01 316 #define BUS_SPACE_BARRIER_WRITE 0x02 317 318 #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) 319 320 /* Bus Space DMA macros */ 321 322 /* 323 * Flags used in various bus DMA methods. 324 */ 325 #define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */ 326 #define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */ 327 #define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */ 328 #define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */ 329 #define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */ 330 #define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */ 331 #define BUS_DMA_BUS2 0x020 332 #define BUS_DMA_BUS3 0x040 333 #define BUS_DMA_BUS4 0x080 334 #define BUS_DMA_READ 0x100 /* mapping is device -> memory only */ 335 #define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */ 336 #define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */ 337 338 /* 339 * Private flags stored in the DMA map. 340 */ 341 #define _BUS_DMAMAP_COHERENT 0x10000 /* no cache flush necessary on sync */ 342 #define _BUS_DMAMAP_IS_BOUNCING 0x20000 /* is bouncing current xfer */ 343 #define _BUS_DMAMAP_NOALLOC 0x40000 /* don't alloc memory from this range */ 344 345 /* Forwards needed by prototypes below. */ 346 struct mbuf; 347 struct uio; 348 349 /* 350 * Operations performed by bus_dmamap_sync(). 351 */ 352 #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */ 353 #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */ 354 #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */ 355 #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */ 356 357 typedef struct arm32_bus_dma_tag *bus_dma_tag_t; 358 typedef struct arm32_bus_dmamap *bus_dmamap_t; 359 360 #define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) 361 362 /* 363 * bus_dma_segment_t 364 * 365 * Describes a single contiguous DMA transaction. Values 366 * are suitable for programming into DMA registers. 367 */ 368 struct arm32_bus_dma_segment { 369 /* 370 * PUBLIC MEMBERS: these are used by machine-independent code. 371 */ 372 bus_addr_t ds_addr; /* DMA address */ 373 bus_size_t ds_len; /* length of transfer */ 374 375 /* 376 * PRIVATE MEMBERS: 377 */ 378 uint32_t _ds_flags; /* _BUS_DMAMAP_COHERENT */ 379 }; 380 typedef struct arm32_bus_dma_segment bus_dma_segment_t; 381 382 /* 383 * arm32_dma_range 384 * 385 * This structure describes a valid DMA range. 386 */ 387 struct arm32_dma_range { 388 bus_addr_t dr_sysbase; /* system base address */ 389 bus_addr_t dr_busbase; /* appears here on bus */ 390 bus_size_t dr_len; /* length of range */ 391 uint32_t dr_flags; /* flags for range */ 392 }; 393 394 /* 395 * bus_dma_tag_t 396 * 397 * A machine-dependent opaque type describing the implementation of 398 * DMA for a given bus. 399 */ 400 401 struct arm32_bus_dma_tag { 402 /* 403 * DMA range for this tag. If the page doesn't fall within 404 * one of these ranges, an error is returned. The caller 405 * may then decide what to do with the transfer. If the 406 * range pointer is NULL, it is ignored. 407 */ 408 struct arm32_dma_range *_ranges; 409 int _nranges; 410 411 /* 412 * Opaque cookie for use by back-end. 413 */ 414 void *_cookie; 415 416 /* 417 * DMA mapping methods. 418 */ 419 int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int, 420 bus_size_t, bus_size_t, int, bus_dmamap_t *); 421 void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t); 422 int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *, 423 bus_size_t, struct proc *, int); 424 int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t, 425 struct mbuf *, int); 426 int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t, 427 struct uio *, int); 428 int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t, 429 bus_dma_segment_t *, int, bus_size_t, int); 430 void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t); 431 void (*_dmamap_sync_pre)(bus_dma_tag_t, bus_dmamap_t, 432 bus_addr_t, bus_size_t, int); 433 void (*_dmamap_sync_post)(bus_dma_tag_t, bus_dmamap_t, 434 bus_addr_t, bus_size_t, int); 435 436 /* 437 * DMA memory utility functions. 438 */ 439 int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t, 440 bus_size_t, bus_dma_segment_t *, int, int *, int); 441 void (*_dmamem_free)(bus_dma_tag_t, 442 bus_dma_segment_t *, int); 443 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *, 444 int, size_t, void **, int); 445 void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t); 446 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *, 447 int, off_t, int, int); 448 449 /* 450 * DMA tag utility functions 451 */ 452 int (*_dmatag_subregion)(bus_dma_tag_t, bus_addr_t, bus_addr_t, 453 bus_dma_tag_t *, int); 454 void (*_dmatag_destroy)(bus_dma_tag_t); 455 456 /* 457 * State for bounce buffers 458 */ 459 int _tag_needs_free; 460 int (*_may_bounce)(bus_dma_tag_t, bus_dmamap_t, int, int *); 461 }; 462 463 /* 464 * bus_dmamap_t 465 * 466 * Describes a DMA mapping. 467 */ 468 struct arm32_bus_dmamap { 469 /* 470 * PRIVATE MEMBERS: not for use by machine-independent code. 471 */ 472 bus_size_t _dm_size; /* largest DMA transfer mappable */ 473 int _dm_segcnt; /* number of segs this map can map */ 474 bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */ 475 bus_size_t _dm_boundary; /* don't cross this */ 476 int _dm_flags; /* misc. flags */ 477 478 void *_dm_origbuf; /* pointer to original buffer */ 479 int _dm_buftype; /* type of buffer */ 480 struct vmspace *_dm_vmspace; /* vmspace that owns the mapping */ 481 482 void *_dm_cookie; /* cookie for bus-specific functions */ 483 484 /* 485 * PUBLIC MEMBERS: these are used by machine-independent code. 486 */ 487 bus_size_t dm_maxsegsz; /* largest possible segment */ 488 bus_size_t dm_mapsize; /* size of the mapping */ 489 int dm_nsegs; /* # valid segments in mapping */ 490 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 491 }; 492 493 /* _dm_buftype */ 494 #define _BUS_DMA_BUFTYPE_INVALID 0 495 #define _BUS_DMA_BUFTYPE_LINEAR 1 496 #define _BUS_DMA_BUFTYPE_MBUF 2 497 #define _BUS_DMA_BUFTYPE_UIO 3 498 #define _BUS_DMA_BUFTYPE_RAW 4 499 500 #ifdef _ARM32_BUS_DMA_PRIVATE 501 #define _BUS_AVAIL_END physical_end 502 /* 503 * Cookie used for bounce buffers. A pointer to one of these it stashed in 504 * the DMA map. 505 */ 506 struct arm32_bus_dma_cookie { 507 int id_flags; /* flags; see below */ 508 509 /* 510 * Information about the original buffer used during 511 * DMA map syncs. Note that origibuflen is only used 512 * for ID_BUFTYPE_LINEAR. 513 */ 514 union { 515 void *un_origbuf; /* pointer to orig buffer if 516 bouncing */ 517 char *un_linearbuf; 518 struct mbuf *un_mbuf; 519 struct uio *un_uio; 520 } id_origbuf_un; 521 #define id_origbuf id_origbuf_un.un_origbuf 522 #define id_origlinearbuf id_origbuf_un.un_linearbuf 523 #define id_origmbuf id_origbuf_un.un_mbuf 524 #define id_origuio id_origbuf_un.un_uio 525 bus_size_t id_origbuflen; /* ...and size */ 526 527 void *id_bouncebuf; /* pointer to the bounce buffer */ 528 bus_size_t id_bouncebuflen; /* ...and size */ 529 int id_nbouncesegs; /* number of valid bounce segs */ 530 bus_dma_segment_t id_bouncesegs[0]; /* array of bounce buffer 531 physical memory segments */ 532 }; 533 534 /* id_flags */ 535 #define _BUS_DMA_IS_BOUNCING 0x04 /* is bouncing current xfer */ 536 #define _BUS_DMA_HAS_BOUNCE 0x02 /* has bounce buffers */ 537 #endif /* _ARM32_BUS_DMA_PRIVATE */ 538 #define _BUS_DMA_MIGHT_NEED_BOUNCE 0x01 /* may need bounce buffers */ 539 540 #endif /* _ARM_BUS_DEFS_H_ */ 541
Indexes created Sat Nov 01 21:09:44 GMT 2025