bus_defs.h revision 1.12
1 /* $NetBSD: bus_defs.h,v 1.12 2018/11/18 20:21:48 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 35 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Christopher G. Demetriou 48 * for the NetBSD Project. 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 #ifndef _ARM_BUS_DEFS_H_ 65 #define _ARM_BUS_DEFS_H_ 66 67 #if defined(_KERNEL_OPT) 68 #include "opt_arm_bus_space.h" 69 #endif 70 71 /* 72 * Addresses (in bus space). 73 */ 74 typedef u_long bus_addr_t; 75 typedef u_long bus_size_t; 76 77 #define PRIxBUSADDR "lx" 78 #define PRIxBUSSIZE "lx" 79 #define PRIuBUSSIZE "lu" 80 81 /* 82 * Access methods for bus space. 83 */ 84 typedef struct bus_space *bus_space_tag_t; 85 typedef u_long bus_space_handle_t; 86 87 #define PRIxBSH "lx" 88 89 /* 90 * int bus_space_map(bus_space_tag_t t, bus_addr_t addr, 91 * bus_size_t size, int flags, bus_space_handle_t *bshp); 92 * 93 * Map a region of bus space. 94 */ 95 96 #define BUS_SPACE_MAP_CACHEABLE 0x01 97 #define BUS_SPACE_MAP_LINEAR 0x02 98 #define BUS_SPACE_MAP_PREFETCHABLE 0x04 99 100 struct bus_space { 101 /* cookie */ 102 void *bs_cookie; 103 104 /* used for aarch64. require ".bs_cookie = bus_space" */ 105 bus_addr_t bs_base; 106 int bs_stride; /* offset <<= bs_stride (if needed) */ 107 int bs_flags; 108 109 /* mapping/unmapping */ 110 int (*bs_map)(void *, bus_addr_t, bus_size_t, 111 int, bus_space_handle_t *); 112 void (*bs_unmap)(void *, bus_space_handle_t, 113 bus_size_t); 114 int (*bs_subregion)(void *, bus_space_handle_t, 115 bus_size_t, bus_size_t, bus_space_handle_t *); 116 117 /* allocation/deallocation */ 118 int (*bs_alloc)(void *, bus_addr_t, bus_addr_t, 119 bus_size_t, bus_size_t, bus_size_t, int, 120 bus_addr_t *, bus_space_handle_t *); 121 void (*bs_free)(void *, bus_space_handle_t, 122 bus_size_t); 123 124 /* get kernel virtual address */ 125 void * (*bs_vaddr)(void *, bus_space_handle_t); 126 127 /* mmap bus space for user */ 128 paddr_t (*bs_mmap)(void *, bus_addr_t, off_t, int, int); 129 130 /* barrier */ 131 void (*bs_barrier)(void *, bus_space_handle_t, 132 bus_size_t, bus_size_t, int); 133 134 /* read (single) */ 135 uint8_t (*bs_r_1)(void *, bus_space_handle_t, 136 bus_size_t); 137 uint16_t (*bs_r_2)(void *, bus_space_handle_t, 138 bus_size_t); 139 uint32_t (*bs_r_4)(void *, bus_space_handle_t, 140 bus_size_t); 141 uint64_t (*bs_r_8)(void *, bus_space_handle_t, 142 bus_size_t); 143 144 /* read multiple */ 145 void (*bs_rm_1)(void *, bus_space_handle_t, 146 bus_size_t, uint8_t *, bus_size_t); 147 void (*bs_rm_2)(void *, bus_space_handle_t, 148 bus_size_t, uint16_t *, bus_size_t); 149 void (*bs_rm_4)(void *, bus_space_handle_t, 150 bus_size_t, uint32_t *, bus_size_t); 151 void (*bs_rm_8)(void *, bus_space_handle_t, 152 bus_size_t, uint64_t *, bus_size_t); 153 154 /* read region */ 155 void (*bs_rr_1)(void *, bus_space_handle_t, 156 bus_size_t, uint8_t *, bus_size_t); 157 void (*bs_rr_2)(void *, bus_space_handle_t, 158 bus_size_t, uint16_t *, bus_size_t); 159 void (*bs_rr_4)(void *, bus_space_handle_t, 160 bus_size_t, uint32_t *, bus_size_t); 161 void (*bs_rr_8)(void *, bus_space_handle_t, 162 bus_size_t, uint64_t *, bus_size_t); 163 164 /* write (single) */ 165 void (*bs_w_1)(void *, bus_space_handle_t, 166 bus_size_t, uint8_t); 167 void (*bs_w_2)(void *, bus_space_handle_t, 168 bus_size_t, uint16_t); 169 void (*bs_w_4)(void *, bus_space_handle_t, 170 bus_size_t, uint32_t); 171 void (*bs_w_8)(void *, bus_space_handle_t, 172 bus_size_t, uint64_t); 173 174 /* write multiple */ 175 void (*bs_wm_1)(void *, bus_space_handle_t, 176 bus_size_t, const uint8_t *, bus_size_t); 177 void (*bs_wm_2)(void *, bus_space_handle_t, 178 bus_size_t, const uint16_t *, bus_size_t); 179 void (*bs_wm_4)(void *, bus_space_handle_t, 180 bus_size_t, const uint32_t *, bus_size_t); 181 void (*bs_wm_8)(void *, bus_space_handle_t, 182 bus_size_t, const uint64_t *, bus_size_t); 183 184 /* write region */ 185 void (*bs_wr_1)(void *, bus_space_handle_t, 186 bus_size_t, const uint8_t *, bus_size_t); 187 void (*bs_wr_2)(void *, bus_space_handle_t, 188 bus_size_t, const uint16_t *, bus_size_t); 189 void (*bs_wr_4)(void *, bus_space_handle_t, 190 bus_size_t, const uint32_t *, bus_size_t); 191 void (*bs_wr_8)(void *, bus_space_handle_t, 192 bus_size_t, const uint64_t *, bus_size_t); 193 194 /* set multiple */ 195 void (*bs_sm_1)(void *, bus_space_handle_t, 196 bus_size_t, uint8_t, bus_size_t); 197 void (*bs_sm_2)(void *, bus_space_handle_t, 198 bus_size_t, uint16_t, bus_size_t); 199 void (*bs_sm_4)(void *, bus_space_handle_t, 200 bus_size_t, uint32_t, bus_size_t); 201 void (*bs_sm_8)(void *, bus_space_handle_t, 202 bus_size_t, uint64_t, bus_size_t); 203 204 /* set region */ 205 void (*bs_sr_1)(void *, bus_space_handle_t, 206 bus_size_t, uint8_t, bus_size_t); 207 void (*bs_sr_2)(void *, bus_space_handle_t, 208 bus_size_t, uint16_t, bus_size_t); 209 void (*bs_sr_4)(void *, bus_space_handle_t, 210 bus_size_t, uint32_t, bus_size_t); 211 void (*bs_sr_8)(void *, bus_space_handle_t, 212 bus_size_t, uint64_t, bus_size_t); 213 214 /* copy */ 215 void (*bs_c_1)(void *, bus_space_handle_t, bus_size_t, 216 bus_space_handle_t, bus_size_t, bus_size_t); 217 void (*bs_c_2)(void *, bus_space_handle_t, bus_size_t, 218 bus_space_handle_t, bus_size_t, bus_size_t); 219 void (*bs_c_4)(void *, bus_space_handle_t, bus_size_t, 220 bus_space_handle_t, bus_size_t, bus_size_t); 221 void (*bs_c_8)(void *, bus_space_handle_t, bus_size_t, 222 bus_space_handle_t, bus_size_t, bus_size_t); 223 224 #ifdef __BUS_SPACE_HAS_STREAM_METHODS 225 /* read stream (single) */ 226 uint8_t (*bs_r_1_s)(void *, bus_space_handle_t, 227 bus_size_t); 228 uint16_t (*bs_r_2_s)(void *, bus_space_handle_t, 229 bus_size_t); 230 uint32_t (*bs_r_4_s)(void *, bus_space_handle_t, 231 bus_size_t); 232 uint64_t (*bs_r_8_s)(void *, bus_space_handle_t, 233 bus_size_t); 234 235 /* read multiple stream */ 236 void (*bs_rm_1_s)(void *, bus_space_handle_t, 237 bus_size_t, uint8_t *, bus_size_t); 238 void (*bs_rm_2_s)(void *, bus_space_handle_t, 239 bus_size_t, uint16_t *, bus_size_t); 240 void (*bs_rm_4_s)(void *, bus_space_handle_t, 241 bus_size_t, uint32_t *, bus_size_t); 242 void (*bs_rm_8_s)(void *, bus_space_handle_t, 243 bus_size_t, uint64_t *, bus_size_t); 244 245 /* read region stream */ 246 void (*bs_rr_1_s)(void *, bus_space_handle_t, 247 bus_size_t, uint8_t *, bus_size_t); 248 void (*bs_rr_2_s)(void *, bus_space_handle_t, 249 bus_size_t, uint16_t *, bus_size_t); 250 void (*bs_rr_4_s)(void *, bus_space_handle_t, 251 bus_size_t, uint32_t *, bus_size_t); 252 void (*bs_rr_8_s)(void *, bus_space_handle_t, 253 bus_size_t, uint64_t *, bus_size_t); 254 255 /* write stream (single) */ 256 void (*bs_w_1_s)(void *, bus_space_handle_t, 257 bus_size_t, uint8_t); 258 void (*bs_w_2_s)(void *, bus_space_handle_t, 259 bus_size_t, uint16_t); 260 void (*bs_w_4_s)(void *, bus_space_handle_t, 261 bus_size_t, uint32_t); 262 void (*bs_w_8_s)(void *, bus_space_handle_t, 263 bus_size_t, uint64_t); 264 265 /* write multiple stream */ 266 void (*bs_wm_1_s)(void *, bus_space_handle_t, 267 bus_size_t, const uint8_t *, bus_size_t); 268 void (*bs_wm_2_s)(void *, bus_space_handle_t, 269 bus_size_t, const uint16_t *, bus_size_t); 270 void (*bs_wm_4_s)(void *, bus_space_handle_t, 271 bus_size_t, const uint32_t *, bus_size_t); 272 void (*bs_wm_8_s)(void *, bus_space_handle_t, 273 bus_size_t, const uint64_t *, bus_size_t); 274 275 /* write region stream */ 276 void (*bs_wr_1_s)(void *, bus_space_handle_t, 277 bus_size_t, const uint8_t *, bus_size_t); 278 void (*bs_wr_2_s)(void *, bus_space_handle_t, 279 bus_size_t, const uint16_t *, bus_size_t); 280 void (*bs_wr_4_s)(void *, bus_space_handle_t, 281 bus_size_t, const uint32_t *, bus_size_t); 282 void (*bs_wr_8_s)(void *, bus_space_handle_t, 283 bus_size_t, const uint64_t *, bus_size_t); 284 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 285 286 #ifdef __BUS_SPACE_HAS_PROBING_METHODS 287 /* peek */ 288 int (*bs_pe_1)(void *, bus_space_handle_t, 289 bus_size_t, uint8_t *); 290 int (*bs_pe_2)(void *, bus_space_handle_t, 291 bus_size_t, uint16_t *); 292 int (*bs_pe_4)(void *, bus_space_handle_t, 293 bus_size_t, uint32_t *); 294 int (*bs_pe_8)(void *, bus_space_handle_t, 295 bus_size_t, uint64_t *); 296 297 /* poke */ 298 int (*bs_po_1)(void *, bus_space_handle_t, 299 bus_size_t, uint8_t); 300 int (*bs_po_2)(void *, bus_space_handle_t, 301 bus_size_t, uint16_t); 302 int (*bs_po_4)(void *, bus_space_handle_t, 303 bus_size_t, uint32_t); 304 int (*bs_po_8)(void *, bus_space_handle_t, 305 bus_size_t, uint64_t); 306 #endif /* __BUS_SPACE_HAS_PROBING_METHODS */ 307 }; 308 309 #define BUS_SPACE_BARRIER_READ 0x01 310 #define BUS_SPACE_BARRIER_WRITE 0x02 311 312 #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) 313 314 /* Bus Space DMA macros */ 315 316 /* 317 * Flags used in various bus DMA methods. 318 */ 319 #define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */ 320 #define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */ 321 #define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */ 322 #define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */ 323 #define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */ 324 #define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */ 325 #define BUS_DMA_BUS2 0x020 326 #define BUS_DMA_BUS3 0x040 327 #define BUS_DMA_BUS4 0x080 328 #define BUS_DMA_READ 0x100 /* mapping is device -> memory only */ 329 #define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */ 330 #define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */ 331 332 /* 333 * Private flags stored in the DMA map. 334 */ 335 #define _BUS_DMAMAP_COHERENT 0x10000 /* no cache flush necessary on sync */ 336 #define _BUS_DMAMAP_IS_BOUNCING 0x20000 /* is bouncing current xfer */ 337 #define _BUS_DMAMAP_NOALLOC 0x40000 /* don't alloc memory from this range */ 338 339 /* Forwards needed by prototypes below. */ 340 struct mbuf; 341 struct uio; 342 343 /* 344 * Operations performed by bus_dmamap_sync(). 345 */ 346 #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */ 347 #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */ 348 #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */ 349 #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */ 350 351 typedef struct arm32_bus_dma_tag *bus_dma_tag_t; 352 typedef struct arm32_bus_dmamap *bus_dmamap_t; 353 354 #define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) 355 356 /* 357 * bus_dma_segment_t 358 * 359 * Describes a single contiguous DMA transaction. Values 360 * are suitable for programming into DMA registers. 361 */ 362 struct arm32_bus_dma_segment { 363 /* 364 * PUBLIC MEMBERS: these are used by machine-independent code. 365 */ 366 bus_addr_t ds_addr; /* DMA address */ 367 bus_size_t ds_len; /* length of transfer */ 368 369 /* 370 * PRIVATE MEMBERS: 371 */ 372 uint32_t _ds_flags; /* _BUS_DMAMAP_COHERENT */ 373 }; 374 typedef struct arm32_bus_dma_segment bus_dma_segment_t; 375 376 /* 377 * arm32_dma_range 378 * 379 * This structure describes a valid DMA range. 380 */ 381 struct arm32_dma_range { 382 bus_addr_t dr_sysbase; /* system base address */ 383 bus_addr_t dr_busbase; /* appears here on bus */ 384 bus_size_t dr_len; /* length of range */ 385 uint32_t dr_flags; /* flags for range */ 386 }; 387 388 /* 389 * bus_dma_tag_t 390 * 391 * A machine-dependent opaque type describing the implementation of 392 * DMA for a given bus. 393 */ 394 395 struct arm32_bus_dma_tag { 396 /* 397 * DMA range for this tag. If the page doesn't fall within 398 * one of these ranges, an error is returned. The caller 399 * may then decide what to do with the transfer. If the 400 * range pointer is NULL, it is ignored. 401 */ 402 struct arm32_dma_range *_ranges; 403 int _nranges; 404 405 /* 406 * Opaque cookie for use by back-end. 407 */ 408 void *_cookie; 409 410 /* 411 * DMA mapping methods. 412 */ 413 int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int, 414 bus_size_t, bus_size_t, int, bus_dmamap_t *); 415 void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t); 416 int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *, 417 bus_size_t, struct proc *, int); 418 int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t, 419 struct mbuf *, int); 420 int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t, 421 struct uio *, int); 422 int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t, 423 bus_dma_segment_t *, int, bus_size_t, int); 424 void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t); 425 void (*_dmamap_sync_pre)(bus_dma_tag_t, bus_dmamap_t, 426 bus_addr_t, bus_size_t, int); 427 void (*_dmamap_sync_post)(bus_dma_tag_t, bus_dmamap_t, 428 bus_addr_t, bus_size_t, int); 429 430 /* 431 * DMA memory utility functions. 432 */ 433 int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t, 434 bus_size_t, bus_dma_segment_t *, int, int *, int); 435 void (*_dmamem_free)(bus_dma_tag_t, 436 bus_dma_segment_t *, int); 437 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *, 438 int, size_t, void **, int); 439 void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t); 440 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *, 441 int, off_t, int, int); 442 443 /* 444 * DMA tag utility functions 445 */ 446 int (*_dmatag_subregion)(bus_dma_tag_t, bus_addr_t, bus_addr_t, 447 bus_dma_tag_t *, int); 448 void (*_dmatag_destroy)(bus_dma_tag_t); 449 450 /* 451 * State for bounce buffers 452 */ 453 int _tag_needs_free; 454 int (*_may_bounce)(bus_dma_tag_t, bus_dmamap_t, int, int *); 455 }; 456 457 /* 458 * bus_dmamap_t 459 * 460 * Describes a DMA mapping. 461 */ 462 struct arm32_bus_dmamap { 463 /* 464 * PRIVATE MEMBERS: not for use by machine-independent code. 465 */ 466 bus_size_t _dm_size; /* largest DMA transfer mappable */ 467 int _dm_segcnt; /* number of segs this map can map */ 468 bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */ 469 bus_size_t _dm_boundary; /* don't cross this */ 470 int _dm_flags; /* misc. flags */ 471 472 void *_dm_origbuf; /* pointer to original buffer */ 473 int _dm_buftype; /* type of buffer */ 474 struct vmspace *_dm_vmspace; /* vmspace that owns the mapping */ 475 476 void *_dm_cookie; /* cookie for bus-specific functions */ 477 478 /* 479 * PUBLIC MEMBERS: these are used by machine-independent code. 480 */ 481 bus_size_t dm_maxsegsz; /* largest possible segment */ 482 bus_size_t dm_mapsize; /* size of the mapping */ 483 int dm_nsegs; /* # valid segments in mapping */ 484 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 485 }; 486 487 /* _dm_buftype */ 488 #define _BUS_DMA_BUFTYPE_INVALID 0 489 #define _BUS_DMA_BUFTYPE_LINEAR 1 490 #define _BUS_DMA_BUFTYPE_MBUF 2 491 #define _BUS_DMA_BUFTYPE_UIO 3 492 #define _BUS_DMA_BUFTYPE_RAW 4 493 494 #ifdef _ARM32_BUS_DMA_PRIVATE 495 #define _BUS_AVAIL_END physical_end 496 /* 497 * Cookie used for bounce buffers. A pointer to one of these it stashed in 498 * the DMA map. 499 */ 500 struct arm32_bus_dma_cookie { 501 int id_flags; /* flags; see below */ 502 503 /* 504 * Information about the original buffer used during 505 * DMA map syncs. Note that origibuflen is only used 506 * for ID_BUFTYPE_LINEAR. 507 */ 508 union { 509 void *un_origbuf; /* pointer to orig buffer if 510 bouncing */ 511 char *un_linearbuf; 512 struct mbuf *un_mbuf; 513 struct uio *un_uio; 514 } id_origbuf_un; 515 #define id_origbuf id_origbuf_un.un_origbuf 516 #define id_origlinearbuf id_origbuf_un.un_linearbuf 517 #define id_origmbuf id_origbuf_un.un_mbuf 518 #define id_origuio id_origbuf_un.un_uio 519 bus_size_t id_origbuflen; /* ...and size */ 520 521 void *id_bouncebuf; /* pointer to the bounce buffer */ 522 bus_size_t id_bouncebuflen; /* ...and size */ 523 int id_nbouncesegs; /* number of valid bounce segs */ 524 bus_dma_segment_t id_bouncesegs[0]; /* array of bounce buffer 525 physical memory segments */ 526 }; 527 528 /* id_flags */ 529 #define _BUS_DMA_IS_BOUNCING 0x04 /* is bouncing current xfer */ 530 #define _BUS_DMA_HAS_BOUNCE 0x02 /* has bounce buffers */ 531 #endif /* _ARM32_BUS_DMA_PRIVATE */ 532 #define _BUS_DMA_MIGHT_NEED_BOUNCE 0x01 /* may need bounce buffers */ 533 534 #endif /* _ARM_BUS_DEFS_H_ */ 535
Indexes created Sat Nov 01 21:09:44 GMT 2025