bus_defs.h revision 1.17
1 /* $NetBSD: bus_defs.h,v 1.17 2021/08/30 22:56:26 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 35 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Christopher G. Demetriou 48 * for the NetBSD Project. 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 #ifndef _ARM_BUS_DEFS_H_ 65 #define _ARM_BUS_DEFS_H_ 66 67 #if defined(_KERNEL_OPT) 68 #include "opt_arm_bus_space.h" 69 #include "opt_kasan.h" 70 #endif 71 72 /* 73 * Addresses (in bus space). 74 */ 75 typedef u_long bus_addr_t; 76 typedef u_long bus_size_t; 77 78 #define PRIxBUSADDR "lx" 79 #define PRIxBUSSIZE "lx" 80 #define PRIuBUSSIZE "lu" 81 82 /* 83 * Access methods for bus space. 84 */ 85 typedef struct bus_space *bus_space_tag_t; 86 typedef u_long bus_space_handle_t; 87 88 #define PRIxBSH "lx" 89 90 /* 91 * int bus_space_map(bus_space_tag_t t, bus_addr_t addr, 92 * bus_size_t size, int flags, bus_space_handle_t *bshp); 93 * 94 * Map a region of bus space. 95 */ 96 97 #define BUS_SPACE_MAP_CACHEABLE 0x01 98 #define BUS_SPACE_MAP_LINEAR 0x02 99 #define BUS_SPACE_MAP_PREFETCHABLE 0x04 100 101 #define BUS_SPACE_MAP_BUS1 0x0100 102 #define BUS_SPACE_MAP_BUS2 0x0200 103 #define BUS_SPACE_MAP_BUS3 0x0400 104 #define BUS_SPACE_MAP_BUS4 0x0800 105 106 #define _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED BUS_SPACE_MAP_BUS1 107 108 struct bus_space { 109 /* cookie */ 110 void *bs_cookie; 111 112 /* used for aarch64. require ".bs_cookie = bus_space" */ 113 int bs_stride; /* offset <<= bs_stride (if needed) */ 114 int bs_flags; 115 116 /* mapping/unmapping */ 117 int (*bs_map)(void *, bus_addr_t, bus_size_t, 118 int, bus_space_handle_t *); 119 void (*bs_unmap)(void *, bus_space_handle_t, 120 bus_size_t); 121 int (*bs_subregion)(void *, bus_space_handle_t, 122 bus_size_t, bus_size_t, bus_space_handle_t *); 123 124 /* allocation/deallocation */ 125 int (*bs_alloc)(void *, bus_addr_t, bus_addr_t, 126 bus_size_t, bus_size_t, bus_size_t, int, 127 bus_addr_t *, bus_space_handle_t *); 128 void (*bs_free)(void *, bus_space_handle_t, 129 bus_size_t); 130 131 /* get kernel virtual address */ 132 void * (*bs_vaddr)(void *, bus_space_handle_t); 133 134 /* mmap bus space for user */ 135 paddr_t (*bs_mmap)(void *, bus_addr_t, off_t, int, int); 136 137 /* barrier */ 138 void (*bs_barrier)(void *, bus_space_handle_t, 139 bus_size_t, bus_size_t, int); 140 141 /* read (single) */ 142 uint8_t (*bs_r_1)(void *, bus_space_handle_t, 143 bus_size_t); 144 uint16_t (*bs_r_2)(void *, bus_space_handle_t, 145 bus_size_t); 146 uint32_t (*bs_r_4)(void *, bus_space_handle_t, 147 bus_size_t); 148 uint64_t (*bs_r_8)(void *, bus_space_handle_t, 149 bus_size_t); 150 151 /* read multiple */ 152 void (*bs_rm_1)(void *, bus_space_handle_t, 153 bus_size_t, uint8_t *, bus_size_t); 154 void (*bs_rm_2)(void *, bus_space_handle_t, 155 bus_size_t, uint16_t *, bus_size_t); 156 void (*bs_rm_4)(void *, bus_space_handle_t, 157 bus_size_t, uint32_t *, bus_size_t); 158 void (*bs_rm_8)(void *, bus_space_handle_t, 159 bus_size_t, uint64_t *, bus_size_t); 160 161 /* read region */ 162 void (*bs_rr_1)(void *, bus_space_handle_t, 163 bus_size_t, uint8_t *, bus_size_t); 164 void (*bs_rr_2)(void *, bus_space_handle_t, 165 bus_size_t, uint16_t *, bus_size_t); 166 void (*bs_rr_4)(void *, bus_space_handle_t, 167 bus_size_t, uint32_t *, bus_size_t); 168 void (*bs_rr_8)(void *, bus_space_handle_t, 169 bus_size_t, uint64_t *, bus_size_t); 170 171 /* write (single) */ 172 void (*bs_w_1)(void *, bus_space_handle_t, 173 bus_size_t, uint8_t); 174 void (*bs_w_2)(void *, bus_space_handle_t, 175 bus_size_t, uint16_t); 176 void (*bs_w_4)(void *, bus_space_handle_t, 177 bus_size_t, uint32_t); 178 void (*bs_w_8)(void *, bus_space_handle_t, 179 bus_size_t, uint64_t); 180 181 /* write multiple */ 182 void (*bs_wm_1)(void *, bus_space_handle_t, 183 bus_size_t, const uint8_t *, bus_size_t); 184 void (*bs_wm_2)(void *, bus_space_handle_t, 185 bus_size_t, const uint16_t *, bus_size_t); 186 void (*bs_wm_4)(void *, bus_space_handle_t, 187 bus_size_t, const uint32_t *, bus_size_t); 188 void (*bs_wm_8)(void *, bus_space_handle_t, 189 bus_size_t, const uint64_t *, bus_size_t); 190 191 /* write region */ 192 void (*bs_wr_1)(void *, bus_space_handle_t, 193 bus_size_t, const uint8_t *, bus_size_t); 194 void (*bs_wr_2)(void *, bus_space_handle_t, 195 bus_size_t, const uint16_t *, bus_size_t); 196 void (*bs_wr_4)(void *, bus_space_handle_t, 197 bus_size_t, const uint32_t *, bus_size_t); 198 void (*bs_wr_8)(void *, bus_space_handle_t, 199 bus_size_t, const uint64_t *, bus_size_t); 200 201 /* set multiple */ 202 void (*bs_sm_1)(void *, bus_space_handle_t, 203 bus_size_t, uint8_t, bus_size_t); 204 void (*bs_sm_2)(void *, bus_space_handle_t, 205 bus_size_t, uint16_t, bus_size_t); 206 void (*bs_sm_4)(void *, bus_space_handle_t, 207 bus_size_t, uint32_t, bus_size_t); 208 void (*bs_sm_8)(void *, bus_space_handle_t, 209 bus_size_t, uint64_t, bus_size_t); 210 211 /* set region */ 212 void (*bs_sr_1)(void *, bus_space_handle_t, 213 bus_size_t, uint8_t, bus_size_t); 214 void (*bs_sr_2)(void *, bus_space_handle_t, 215 bus_size_t, uint16_t, bus_size_t); 216 void (*bs_sr_4)(void *, bus_space_handle_t, 217 bus_size_t, uint32_t, bus_size_t); 218 void (*bs_sr_8)(void *, bus_space_handle_t, 219 bus_size_t, uint64_t, bus_size_t); 220 221 /* copy */ 222 void (*bs_c_1)(void *, bus_space_handle_t, bus_size_t, 223 bus_space_handle_t, bus_size_t, bus_size_t); 224 void (*bs_c_2)(void *, bus_space_handle_t, bus_size_t, 225 bus_space_handle_t, bus_size_t, bus_size_t); 226 void (*bs_c_4)(void *, bus_space_handle_t, bus_size_t, 227 bus_space_handle_t, bus_size_t, bus_size_t); 228 void (*bs_c_8)(void *, bus_space_handle_t, bus_size_t, 229 bus_space_handle_t, bus_size_t, bus_size_t); 230 231 #ifdef __BUS_SPACE_HAS_STREAM_METHODS 232 /* read stream (single) */ 233 uint8_t (*bs_r_1_s)(void *, bus_space_handle_t, 234 bus_size_t); 235 uint16_t (*bs_r_2_s)(void *, bus_space_handle_t, 236 bus_size_t); 237 uint32_t (*bs_r_4_s)(void *, bus_space_handle_t, 238 bus_size_t); 239 uint64_t (*bs_r_8_s)(void *, bus_space_handle_t, 240 bus_size_t); 241 242 /* read multiple stream */ 243 void (*bs_rm_1_s)(void *, bus_space_handle_t, 244 bus_size_t, uint8_t *, bus_size_t); 245 void (*bs_rm_2_s)(void *, bus_space_handle_t, 246 bus_size_t, uint16_t *, bus_size_t); 247 void (*bs_rm_4_s)(void *, bus_space_handle_t, 248 bus_size_t, uint32_t *, bus_size_t); 249 void (*bs_rm_8_s)(void *, bus_space_handle_t, 250 bus_size_t, uint64_t *, bus_size_t); 251 252 /* read region stream */ 253 void (*bs_rr_1_s)(void *, bus_space_handle_t, 254 bus_size_t, uint8_t *, bus_size_t); 255 void (*bs_rr_2_s)(void *, bus_space_handle_t, 256 bus_size_t, uint16_t *, bus_size_t); 257 void (*bs_rr_4_s)(void *, bus_space_handle_t, 258 bus_size_t, uint32_t *, bus_size_t); 259 void (*bs_rr_8_s)(void *, bus_space_handle_t, 260 bus_size_t, uint64_t *, bus_size_t); 261 262 /* write stream (single) */ 263 void (*bs_w_1_s)(void *, bus_space_handle_t, 264 bus_size_t, uint8_t); 265 void (*bs_w_2_s)(void *, bus_space_handle_t, 266 bus_size_t, uint16_t); 267 void (*bs_w_4_s)(void *, bus_space_handle_t, 268 bus_size_t, uint32_t); 269 void (*bs_w_8_s)(void *, bus_space_handle_t, 270 bus_size_t, uint64_t); 271 272 /* write multiple stream */ 273 void (*bs_wm_1_s)(void *, bus_space_handle_t, 274 bus_size_t, const uint8_t *, bus_size_t); 275 void (*bs_wm_2_s)(void *, bus_space_handle_t, 276 bus_size_t, const uint16_t *, bus_size_t); 277 void (*bs_wm_4_s)(void *, bus_space_handle_t, 278 bus_size_t, const uint32_t *, bus_size_t); 279 void (*bs_wm_8_s)(void *, bus_space_handle_t, 280 bus_size_t, const uint64_t *, bus_size_t); 281 282 /* write region stream */ 283 void (*bs_wr_1_s)(void *, bus_space_handle_t, 284 bus_size_t, const uint8_t *, bus_size_t); 285 void (*bs_wr_2_s)(void *, bus_space_handle_t, 286 bus_size_t, const uint16_t *, bus_size_t); 287 void (*bs_wr_4_s)(void *, bus_space_handle_t, 288 bus_size_t, const uint32_t *, bus_size_t); 289 void (*bs_wr_8_s)(void *, bus_space_handle_t, 290 bus_size_t, const uint64_t *, bus_size_t); 291 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 292 293 #ifdef __BUS_SPACE_HAS_PROBING_METHODS 294 /* peek */ 295 int (*bs_pe_1)(void *, bus_space_handle_t, 296 bus_size_t, uint8_t *); 297 int (*bs_pe_2)(void *, bus_space_handle_t, 298 bus_size_t, uint16_t *); 299 int (*bs_pe_4)(void *, bus_space_handle_t, 300 bus_size_t, uint32_t *); 301 int (*bs_pe_8)(void *, bus_space_handle_t, 302 bus_size_t, uint64_t *); 303 304 /* poke */ 305 int (*bs_po_1)(void *, bus_space_handle_t, 306 bus_size_t, uint8_t); 307 int (*bs_po_2)(void *, bus_space_handle_t, 308 bus_size_t, uint16_t); 309 int (*bs_po_4)(void *, bus_space_handle_t, 310 bus_size_t, uint32_t); 311 int (*bs_po_8)(void *, bus_space_handle_t, 312 bus_size_t, uint64_t); 313 #endif /* __BUS_SPACE_HAS_PROBING_METHODS */ 314 }; 315 316 #define BUS_SPACE_BARRIER_READ 0x01 317 #define BUS_SPACE_BARRIER_WRITE 0x02 318 319 #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) 320 321 /* Bus Space DMA macros */ 322 323 /* 324 * Flags used in various bus DMA methods. 325 */ 326 #define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */ 327 #define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */ 328 #define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */ 329 #define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */ 330 #define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */ 331 #define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */ 332 #define BUS_DMA_BUS2 0x020 333 #define BUS_DMA_BUS3 0x040 334 #define BUS_DMA_BUS4 0x080 335 #define BUS_DMA_READ 0x100 /* mapping is device -> memory only */ 336 #define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */ 337 #define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */ 338 339 /* 340 * Private flags stored in the DMA map. 341 */ 342 #define _BUS_DMAMAP_COHERENT 0x10000 /* no cache flush necessary on sync */ 343 #define _BUS_DMAMAP_IS_BOUNCING 0x20000 /* is bouncing current xfer */ 344 #define _BUS_DMAMAP_NOALLOC 0x40000 /* don't alloc memory from this range */ 345 346 /* Forwards needed by prototypes below. */ 347 struct mbuf; 348 struct uio; 349 350 /* 351 * Operations performed by bus_dmamap_sync(). 352 */ 353 #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */ 354 #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */ 355 #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */ 356 #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */ 357 358 typedef struct arm32_bus_dma_tag *bus_dma_tag_t; 359 typedef struct arm32_bus_dmamap *bus_dmamap_t; 360 361 #define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) 362 363 /* 364 * bus_dma_segment_t 365 * 366 * Describes a single contiguous DMA transaction. Values 367 * are suitable for programming into DMA registers. 368 */ 369 struct arm32_bus_dma_segment { 370 /* 371 * PUBLIC MEMBERS: these are used by machine-independent code. 372 */ 373 bus_addr_t ds_addr; /* DMA address */ 374 bus_size_t ds_len; /* length of transfer */ 375 376 /* 377 * PRIVATE MEMBERS: 378 */ 379 uint32_t _ds_flags; /* _BUS_DMAMAP_COHERENT */ 380 paddr_t _ds_paddr; /* CPU address */ 381 }; 382 typedef struct arm32_bus_dma_segment bus_dma_segment_t; 383 384 /* 385 * arm32_dma_range 386 * 387 * This structure describes a valid DMA range. 388 */ 389 struct arm32_dma_range { 390 bus_addr_t dr_sysbase; /* system base address */ 391 bus_addr_t dr_busbase; /* appears here on bus */ 392 bus_size_t dr_len; /* length of range */ 393 uint32_t dr_flags; /* flags for range */ 394 }; 395 396 /* 397 * bus_dma_tag_t 398 * 399 * A machine-dependent opaque type describing the implementation of 400 * DMA for a given bus. 401 */ 402 403 struct arm32_bus_dma_tag { 404 /* 405 * DMA range for this tag. If the page doesn't fall within 406 * one of these ranges, an error is returned. The caller 407 * may then decide what to do with the transfer. If the 408 * range pointer is NULL, it is ignored. 409 */ 410 struct arm32_dma_range *_ranges; 411 int _nranges; 412 413 /* 414 * Opaque cookie for use by back-end. 415 */ 416 void *_cookie; 417 418 /* 419 * DMA mapping methods. 420 */ 421 int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int, 422 bus_size_t, bus_size_t, int, bus_dmamap_t *); 423 void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t); 424 int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *, 425 bus_size_t, struct proc *, int); 426 int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t, 427 struct mbuf *, int); 428 int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t, 429 struct uio *, int); 430 int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t, 431 bus_dma_segment_t *, int, bus_size_t, int); 432 void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t); 433 void (*_dmamap_sync_pre)(bus_dma_tag_t, bus_dmamap_t, 434 bus_addr_t, bus_size_t, int); 435 void (*_dmamap_sync_post)(bus_dma_tag_t, bus_dmamap_t, 436 bus_addr_t, bus_size_t, int); 437 438 /* 439 * DMA memory utility functions. 440 */ 441 int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t, 442 bus_size_t, bus_dma_segment_t *, int, int *, int); 443 void (*_dmamem_free)(bus_dma_tag_t, 444 bus_dma_segment_t *, int); 445 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *, 446 int, size_t, void **, int); 447 void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t); 448 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *, 449 int, off_t, int, int); 450 451 /* 452 * DMA tag utility functions 453 */ 454 int (*_dmatag_subregion)(bus_dma_tag_t, bus_addr_t, bus_addr_t, 455 bus_dma_tag_t *, int); 456 void (*_dmatag_destroy)(bus_dma_tag_t); 457 458 /* 459 * State for bounce buffers 460 */ 461 int _tag_needs_free; 462 int (*_may_bounce)(bus_dma_tag_t, bus_dmamap_t, int, int *); 463 }; 464 465 /* 466 * bus_dmamap_t 467 * 468 * Describes a DMA mapping. 469 */ 470 struct arm32_bus_dmamap { 471 /* 472 * PRIVATE MEMBERS: not for use by machine-independent code. 473 */ 474 bus_size_t _dm_size; /* largest DMA transfer mappable */ 475 int _dm_segcnt; /* number of segs this map can map */ 476 bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */ 477 bus_size_t _dm_boundary; /* don't cross this */ 478 int _dm_flags; /* misc. flags */ 479 480 void *_dm_origbuf; /* pointer to original buffer */ 481 int _dm_buftype; /* type of buffer */ 482 struct vmspace *_dm_vmspace; /* vmspace that owns the mapping */ 483 484 void *_dm_cookie; /* cookie for bus-specific functions */ 485 void *_dm_iommu; /* cookie for iommu functions */ 486 487 /* 488 * PUBLIC MEMBERS: these are used by machine-independent code. 489 */ 490 #if defined(KASAN) 491 void *dm_buf; 492 bus_size_t dm_buflen; 493 int dm_buftype; 494 #endif 495 bus_size_t dm_maxsegsz; /* largest possible segment */ 496 bus_size_t dm_mapsize; /* size of the mapping */ 497 int dm_nsegs; /* # valid segments in mapping */ 498 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 499 }; 500 501 /* _dm_buftype */ 502 #define _BUS_DMA_BUFTYPE_INVALID 0 503 #define _BUS_DMA_BUFTYPE_LINEAR 1 504 #define _BUS_DMA_BUFTYPE_MBUF 2 505 #define _BUS_DMA_BUFTYPE_UIO 3 506 #define _BUS_DMA_BUFTYPE_RAW 4 507 508 #ifdef _ARM32_BUS_DMA_PRIVATE 509 #define _BUS_AVAIL_END physical_end 510 /* 511 * Cookie used for bounce buffers. A pointer to one of these it stashed in 512 * the DMA map. 513 */ 514 struct arm32_bus_dma_cookie { 515 int id_flags; /* flags; see below */ 516 517 /* 518 * Information about the original buffer used during 519 * DMA map syncs. Note that origibuflen is only used 520 * for ID_BUFTYPE_LINEAR. 521 */ 522 union { 523 void *un_origbuf; /* pointer to orig buffer if 524 bouncing */ 525 char *un_linearbuf; 526 struct mbuf *un_mbuf; 527 struct uio *un_uio; 528 } id_origbuf_un; 529 #define id_origbuf id_origbuf_un.un_origbuf 530 #define id_origlinearbuf id_origbuf_un.un_linearbuf 531 #define id_origmbuf id_origbuf_un.un_mbuf 532 #define id_origuio id_origbuf_un.un_uio 533 bus_size_t id_origbuflen; /* ...and size */ 534 535 void *id_bouncebuf; /* pointer to the bounce buffer */ 536 bus_size_t id_bouncebuflen; /* ...and size */ 537 int id_nbouncesegs; /* number of valid bounce segs */ 538 bus_dma_segment_t id_bouncesegs[0]; /* array of bounce buffer 539 physical memory segments */ 540 }; 541 542 /* id_flags */ 543 #define _BUS_DMA_IS_BOUNCING 0x04 /* is bouncing current xfer */ 544 #define _BUS_DMA_HAS_BOUNCE 0x02 /* has bounce buffers */ 545 #endif /* _ARM32_BUS_DMA_PRIVATE */ 546 #define _BUS_DMA_MIGHT_NEED_BOUNCE 0x01 /* may need bounce buffers */ 547 548 #endif /* _ARM_BUS_DEFS_H_ */ 549
Indexes created Sat Nov 01 21:09:44 GMT 2025