bus_defs.h revision 1.8
1 /* $NetBSD: bus_defs.h,v 1.8 2013/01/27 19:00:08 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 35 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Christopher G. Demetriou 48 * for the NetBSD Project. 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 #ifndef _ARM32_BUS_DEFS_H_ 65 #define _ARM32_BUS_DEFS_H_ 66 67 #if defined(_KERNEL_OPT) 68 #include "opt_arm_bus_space.h" 69 #endif 70 71 /* 72 * Addresses (in bus space). 73 */ 74 typedef u_long bus_addr_t; 75 typedef u_long bus_size_t; 76 77 /* 78 * Access methods for bus space. 79 */ 80 typedef struct bus_space *bus_space_tag_t; 81 typedef u_long bus_space_handle_t; 82 83 /* 84 * int bus_space_map(bus_space_tag_t t, bus_addr_t addr, 85 * bus_size_t size, int flags, bus_space_handle_t *bshp); 86 * 87 * Map a region of bus space. 88 */ 89 90 #define BUS_SPACE_MAP_CACHEABLE 0x01 91 #define BUS_SPACE_MAP_LINEAR 0x02 92 #define BUS_SPACE_MAP_PREFETCHABLE 0x04 93 94 struct bus_space { 95 /* cookie */ 96 void *bs_cookie; 97 98 /* mapping/unmapping */ 99 int (*bs_map)(void *, bus_addr_t, bus_size_t, 100 int, bus_space_handle_t *); 101 void (*bs_unmap)(void *, bus_space_handle_t, 102 bus_size_t); 103 int (*bs_subregion)(void *, bus_space_handle_t, 104 bus_size_t, bus_size_t, bus_space_handle_t *); 105 106 /* allocation/deallocation */ 107 int (*bs_alloc)(void *, bus_addr_t, bus_addr_t, 108 bus_size_t, bus_size_t, bus_size_t, int, 109 bus_addr_t *, bus_space_handle_t *); 110 void (*bs_free)(void *, bus_space_handle_t, 111 bus_size_t); 112 113 /* get kernel virtual address */ 114 void * (*bs_vaddr)(void *, bus_space_handle_t); 115 116 /* mmap bus space for user */ 117 paddr_t (*bs_mmap)(void *, bus_addr_t, off_t, int, int); 118 119 /* barrier */ 120 void (*bs_barrier)(void *, bus_space_handle_t, 121 bus_size_t, bus_size_t, int); 122 123 /* read (single) */ 124 uint8_t (*bs_r_1)(void *, bus_space_handle_t, 125 bus_size_t); 126 uint16_t (*bs_r_2)(void *, bus_space_handle_t, 127 bus_size_t); 128 uint32_t (*bs_r_4)(void *, bus_space_handle_t, 129 bus_size_t); 130 uint64_t (*bs_r_8)(void *, bus_space_handle_t, 131 bus_size_t); 132 133 /* read multiple */ 134 void (*bs_rm_1)(void *, bus_space_handle_t, 135 bus_size_t, uint8_t *, bus_size_t); 136 void (*bs_rm_2)(void *, bus_space_handle_t, 137 bus_size_t, uint16_t *, bus_size_t); 138 void (*bs_rm_4)(void *, bus_space_handle_t, 139 bus_size_t, uint32_t *, bus_size_t); 140 void (*bs_rm_8)(void *, bus_space_handle_t, 141 bus_size_t, uint64_t *, bus_size_t); 142 143 /* read region */ 144 void (*bs_rr_1)(void *, bus_space_handle_t, 145 bus_size_t, uint8_t *, bus_size_t); 146 void (*bs_rr_2)(void *, bus_space_handle_t, 147 bus_size_t, uint16_t *, bus_size_t); 148 void (*bs_rr_4)(void *, bus_space_handle_t, 149 bus_size_t, uint32_t *, bus_size_t); 150 void (*bs_rr_8)(void *, bus_space_handle_t, 151 bus_size_t, uint64_t *, bus_size_t); 152 153 /* write (single) */ 154 void (*bs_w_1)(void *, bus_space_handle_t, 155 bus_size_t, uint8_t); 156 void (*bs_w_2)(void *, bus_space_handle_t, 157 bus_size_t, uint16_t); 158 void (*bs_w_4)(void *, bus_space_handle_t, 159 bus_size_t, uint32_t); 160 void (*bs_w_8)(void *, bus_space_handle_t, 161 bus_size_t, uint64_t); 162 163 /* write multiple */ 164 void (*bs_wm_1)(void *, bus_space_handle_t, 165 bus_size_t, const uint8_t *, bus_size_t); 166 void (*bs_wm_2)(void *, bus_space_handle_t, 167 bus_size_t, const uint16_t *, bus_size_t); 168 void (*bs_wm_4)(void *, bus_space_handle_t, 169 bus_size_t, const uint32_t *, bus_size_t); 170 void (*bs_wm_8)(void *, bus_space_handle_t, 171 bus_size_t, const uint64_t *, bus_size_t); 172 173 /* write region */ 174 void (*bs_wr_1)(void *, bus_space_handle_t, 175 bus_size_t, const uint8_t *, bus_size_t); 176 void (*bs_wr_2)(void *, bus_space_handle_t, 177 bus_size_t, const uint16_t *, bus_size_t); 178 void (*bs_wr_4)(void *, bus_space_handle_t, 179 bus_size_t, const uint32_t *, bus_size_t); 180 void (*bs_wr_8)(void *, bus_space_handle_t, 181 bus_size_t, const uint64_t *, bus_size_t); 182 183 /* set multiple */ 184 void (*bs_sm_1)(void *, bus_space_handle_t, 185 bus_size_t, uint8_t, bus_size_t); 186 void (*bs_sm_2)(void *, bus_space_handle_t, 187 bus_size_t, uint16_t, bus_size_t); 188 void (*bs_sm_4)(void *, bus_space_handle_t, 189 bus_size_t, uint32_t, bus_size_t); 190 void (*bs_sm_8)(void *, bus_space_handle_t, 191 bus_size_t, uint64_t, bus_size_t); 192 193 /* set region */ 194 void (*bs_sr_1)(void *, bus_space_handle_t, 195 bus_size_t, uint8_t, bus_size_t); 196 void (*bs_sr_2)(void *, bus_space_handle_t, 197 bus_size_t, uint16_t, bus_size_t); 198 void (*bs_sr_4)(void *, bus_space_handle_t, 199 bus_size_t, uint32_t, bus_size_t); 200 void (*bs_sr_8)(void *, bus_space_handle_t, 201 bus_size_t, uint64_t, bus_size_t); 202 203 /* copy */ 204 void (*bs_c_1)(void *, bus_space_handle_t, bus_size_t, 205 bus_space_handle_t, bus_size_t, bus_size_t); 206 void (*bs_c_2)(void *, bus_space_handle_t, bus_size_t, 207 bus_space_handle_t, bus_size_t, bus_size_t); 208 void (*bs_c_4)(void *, bus_space_handle_t, bus_size_t, 209 bus_space_handle_t, bus_size_t, bus_size_t); 210 void (*bs_c_8)(void *, bus_space_handle_t, bus_size_t, 211 bus_space_handle_t, bus_size_t, bus_size_t); 212 213 #ifdef __BUS_SPACE_HAS_STREAM_METHODS 214 /* read stream (single) */ 215 uint8_t (*bs_r_1_s)(void *, bus_space_handle_t, 216 bus_size_t); 217 uint16_t (*bs_r_2_s)(void *, bus_space_handle_t, 218 bus_size_t); 219 uint32_t (*bs_r_4_s)(void *, bus_space_handle_t, 220 bus_size_t); 221 uint64_t (*bs_r_8_s)(void *, bus_space_handle_t, 222 bus_size_t); 223 224 /* read multiple stream */ 225 void (*bs_rm_1_s)(void *, bus_space_handle_t, 226 bus_size_t, uint8_t *, bus_size_t); 227 void (*bs_rm_2_s)(void *, bus_space_handle_t, 228 bus_size_t, uint16_t *, bus_size_t); 229 void (*bs_rm_4_s)(void *, bus_space_handle_t, 230 bus_size_t, uint32_t *, bus_size_t); 231 void (*bs_rm_8_s)(void *, bus_space_handle_t, 232 bus_size_t, uint64_t *, bus_size_t); 233 234 /* read region stream */ 235 void (*bs_rr_1_s)(void *, bus_space_handle_t, 236 bus_size_t, uint8_t *, bus_size_t); 237 void (*bs_rr_2_s)(void *, bus_space_handle_t, 238 bus_size_t, uint16_t *, bus_size_t); 239 void (*bs_rr_4_s)(void *, bus_space_handle_t, 240 bus_size_t, uint32_t *, bus_size_t); 241 void (*bs_rr_8_s)(void *, bus_space_handle_t, 242 bus_size_t, uint64_t *, bus_size_t); 243 244 /* write stream (single) */ 245 void (*bs_w_1_s)(void *, bus_space_handle_t, 246 bus_size_t, uint8_t); 247 void (*bs_w_2_s)(void *, bus_space_handle_t, 248 bus_size_t, uint16_t); 249 void (*bs_w_4_s)(void *, bus_space_handle_t, 250 bus_size_t, uint32_t); 251 void (*bs_w_8_s)(void *, bus_space_handle_t, 252 bus_size_t, uint64_t); 253 254 /* write multiple stream */ 255 void (*bs_wm_1_s)(void *, bus_space_handle_t, 256 bus_size_t, const uint8_t *, bus_size_t); 257 void (*bs_wm_2_s)(void *, bus_space_handle_t, 258 bus_size_t, const uint16_t *, bus_size_t); 259 void (*bs_wm_4_s)(void *, bus_space_handle_t, 260 bus_size_t, const uint32_t *, bus_size_t); 261 void (*bs_wm_8_s)(void *, bus_space_handle_t, 262 bus_size_t, const uint64_t *, bus_size_t); 263 264 /* write region stream */ 265 void (*bs_wr_1_s)(void *, bus_space_handle_t, 266 bus_size_t, const uint8_t *, bus_size_t); 267 void (*bs_wr_2_s)(void *, bus_space_handle_t, 268 bus_size_t, const uint16_t *, bus_size_t); 269 void (*bs_wr_4_s)(void *, bus_space_handle_t, 270 bus_size_t, const uint32_t *, bus_size_t); 271 void (*bs_wr_8_s)(void *, bus_space_handle_t, 272 bus_size_t, const uint64_t *, bus_size_t); 273 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 274 }; 275 276 #define BUS_SPACE_BARRIER_READ 0x01 277 #define BUS_SPACE_BARRIER_WRITE 0x02 278 279 #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) 280 281 /* Bus Space DMA macros */ 282 283 /* 284 * Flags used in various bus DMA methods. 285 */ 286 #define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */ 287 #define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */ 288 #define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */ 289 #define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */ 290 #define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */ 291 #define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */ 292 #define BUS_DMA_BUS2 0x020 293 #define BUS_DMA_BUS3 0x040 294 #define BUS_DMA_BUS4 0x080 295 #define BUS_DMA_READ 0x100 /* mapping is device -> memory only */ 296 #define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */ 297 #define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */ 298 299 /* 300 * Private flags stored in the DMA map. 301 */ 302 #define _BUS_DMAMAP_COHERENT 0x10000 /* no cache flush necessary on sync */ 303 #define _BUS_DMAMAP_IS_BOUNCING 0x20000 /* is bouncing current xfer */ 304 #define _BUS_DMAMAP_NOALLOC 0x40000 /* don't alloc memory from this range */ 305 306 /* Forwards needed by prototypes below. */ 307 struct mbuf; 308 struct uio; 309 310 /* 311 * Operations performed by bus_dmamap_sync(). 312 */ 313 #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */ 314 #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */ 315 #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */ 316 #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */ 317 318 typedef struct arm32_bus_dma_tag *bus_dma_tag_t; 319 typedef struct arm32_bus_dmamap *bus_dmamap_t; 320 321 #define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) 322 323 /* 324 * bus_dma_segment_t 325 * 326 * Describes a single contiguous DMA transaction. Values 327 * are suitable for programming into DMA registers. 328 */ 329 struct arm32_bus_dma_segment { 330 /* 331 * PUBLIC MEMBERS: these are used by machine-independent code. 332 */ 333 bus_addr_t ds_addr; /* DMA address */ 334 bus_size_t ds_len; /* length of transfer */ 335 uint32_t _ds_flags; /* _BUS_DMAMAP_COHERENT */ 336 }; 337 typedef struct arm32_bus_dma_segment bus_dma_segment_t; 338 339 /* 340 * arm32_dma_range 341 * 342 * This structure describes a valid DMA range. 343 */ 344 struct arm32_dma_range { 345 bus_addr_t dr_sysbase; /* system base address */ 346 bus_addr_t dr_busbase; /* appears here on bus */ 347 bus_size_t dr_len; /* length of range */ 348 uint32_t dr_flags; /* flags for range */ 349 }; 350 351 /* 352 * bus_dma_tag_t 353 * 354 * A machine-dependent opaque type describing the implementation of 355 * DMA for a given bus. 356 */ 357 358 struct arm32_bus_dma_tag { 359 /* 360 * DMA range for this tag. If the page doesn't fall within 361 * one of these ranges, an error is returned. The caller 362 * may then decide what to do with the transfer. If the 363 * range pointer is NULL, it is ignored. 364 */ 365 struct arm32_dma_range *_ranges; 366 int _nranges; 367 368 /* 369 * Opaque cookie for use by back-end. 370 */ 371 void *_cookie; 372 373 /* 374 * DMA mapping methods. 375 */ 376 int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int, 377 bus_size_t, bus_size_t, int, bus_dmamap_t *); 378 void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t); 379 int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *, 380 bus_size_t, struct proc *, int); 381 int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t, 382 struct mbuf *, int); 383 int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t, 384 struct uio *, int); 385 int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t, 386 bus_dma_segment_t *, int, bus_size_t, int); 387 void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t); 388 void (*_dmamap_sync_pre)(bus_dma_tag_t, bus_dmamap_t, 389 bus_addr_t, bus_size_t, int); 390 void (*_dmamap_sync_post)(bus_dma_tag_t, bus_dmamap_t, 391 bus_addr_t, bus_size_t, int); 392 393 /* 394 * DMA memory utility functions. 395 */ 396 int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t, 397 bus_size_t, bus_dma_segment_t *, int, int *, int); 398 void (*_dmamem_free)(bus_dma_tag_t, 399 bus_dma_segment_t *, int); 400 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *, 401 int, size_t, void **, int); 402 void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t); 403 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *, 404 int, off_t, int, int); 405 406 /* 407 * DMA tag utility functions 408 */ 409 int (*_dmatag_subregion)(bus_dma_tag_t, bus_addr_t, bus_addr_t, 410 bus_dma_tag_t *, int); 411 void (*_dmatag_destroy)(bus_dma_tag_t); 412 413 /* 414 * State for bounce buffers 415 */ 416 int _tag_needs_free; 417 int (*_may_bounce)(bus_dma_tag_t, bus_dmamap_t, int, int *); 418 }; 419 420 /* 421 * bus_dmamap_t 422 * 423 * Describes a DMA mapping. 424 */ 425 struct arm32_bus_dmamap { 426 /* 427 * PRIVATE MEMBERS: not for use by machine-independent code. 428 */ 429 bus_size_t _dm_size; /* largest DMA transfer mappable */ 430 int _dm_segcnt; /* number of segs this map can map */ 431 bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */ 432 bus_size_t _dm_boundary; /* don't cross this */ 433 int _dm_flags; /* misc. flags */ 434 435 void *_dm_origbuf; /* pointer to original buffer */ 436 int _dm_buftype; /* type of buffer */ 437 struct vmspace *_dm_vmspace; /* vmspace that owns the mapping */ 438 439 void *_dm_cookie; /* cookie for bus-specific functions */ 440 441 /* 442 * PUBLIC MEMBERS: these are used by machine-independent code. 443 */ 444 bus_size_t dm_maxsegsz; /* largest possible segment */ 445 bus_size_t dm_mapsize; /* size of the mapping */ 446 int dm_nsegs; /* # valid segments in mapping */ 447 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 448 }; 449 450 /* _dm_buftype */ 451 #define _BUS_DMA_BUFTYPE_INVALID 0 452 #define _BUS_DMA_BUFTYPE_LINEAR 1 453 #define _BUS_DMA_BUFTYPE_MBUF 2 454 #define _BUS_DMA_BUFTYPE_UIO 3 455 #define _BUS_DMA_BUFTYPE_RAW 4 456 457 #ifdef _ARM32_BUS_DMA_PRIVATE 458 #define _BUS_AVAIL_END physical_end 459 /* 460 * Cookie used for bounce buffers. A pointer to one of these it stashed in 461 * the DMA map. 462 */ 463 struct arm32_bus_dma_cookie { 464 int id_flags; /* flags; see below */ 465 466 /* 467 * Information about the original buffer used during 468 * DMA map syncs. Note that origibuflen is only used 469 * for ID_BUFTYPE_LINEAR. 470 */ 471 union { 472 void *un_origbuf; /* pointer to orig buffer if 473 bouncing */ 474 char *un_linearbuf; 475 struct mbuf *un_mbuf; 476 struct uio *un_uio; 477 } id_origbuf_un; 478 #define id_origbuf id_origbuf_un.un_origbuf 479 #define id_origlinearbuf id_origbuf_un.un_linearbuf 480 #define id_origmbuf id_origbuf_un.un_mbuf 481 #define id_origuio id_origbuf_un.un_uio 482 bus_size_t id_origbuflen; /* ...and size */ 483 484 void *id_bouncebuf; /* pointer to the bounce buffer */ 485 bus_size_t id_bouncebuflen; /* ...and size */ 486 int id_nbouncesegs; /* number of valid bounce segs */ 487 bus_dma_segment_t id_bouncesegs[0]; /* array of bounce buffer 488 physical memory segments */ 489 }; 490 491 /* id_flags */ 492 #define _BUS_DMA_IS_BOUNCING 0x04 /* is bouncing current xfer */ 493 #define _BUS_DMA_HAS_BOUNCE 0x02 /* has bounce buffers */ 494 #endif /* _ARM32_BUS_DMA_PRIVATE */ 495 #define _BUS_DMA_MIGHT_NEED_BOUNCE 0x01 /* may need bounce buffers */ 496 497 #endif /* _ARM32_BUS_DEFS_H_ */ 498
Indexes created Sat Nov 01 21:09:44 GMT 2025