cpu.h revision 1.1
1 /* $NetBSD: cpu.h,v 1.1 2001/02/23 21:23:47 reinoud Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1996 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * cpu.h 40 * 41 * CPU specific symbols 42 * 43 * Created : 18/09/94 44 * 45 * Based on kate/katelib/arm6.h 46 */ 47 48 #ifndef _ARM32_CPU_H_ 49 #define _ARM32_CPU_H_ 50 51 #if defined(_KERNEL) && !defined(_LKM) 52 #include "opt_cputypes.h" 53 #include "opt_lockdebug.h" 54 #endif 55 56 #ifndef _LOCORE 57 #include <machine/frame.h> 58 #endif /* !_LOCORE */ 59 #include <machine/psl.h> 60 61 #if defined(CPU_ARM7500) && !defined(CPU_ARM7) 62 #error "option CPU_ARM7 is required with CPU_ARM7500" 63 #endif 64 65 #ifdef CPU_ARM7500 66 #ifdef CPU_ARM6 67 #error "CPU options CPU_ARM6 and CPU_ARM7500 are not compatible" 68 #endif 69 #ifdef CPU_ARM8 70 #error "CPU options CPU_ARM8 and CPU_ARM7500 are not compatible" 71 #endif 72 #ifdef CPU_SA110 73 #error "CPU options CPU_SA110 and CPU_ARM7500 are not compatible" 74 #endif 75 #endif /* CPU_ARM7500 */ 76 77 #define COPY_SIGCODE /* copy sigcode above user stack in exec */ 78 79 /* 80 * ARM Process Status Register 81 * 82 * The picture in the ARM manuals looks like this: 83 * 3 3 2 2 2 84 * 1 0 9 8 7 8 7 6 5 4 0 85 * +-------+---------------------------------------+-+-+-+---------+ 86 * | flags | reserved |I|F| |M M M M M| 87 * |n z c v| | | | |4 3 2 1 0| 88 * +-------+---------------------------------------+-+-+-+---------+ 89 */ 90 91 #define PSR_FLAGS 0xf0000000 /* flags */ 92 #define PSR_N_bit (1 << 31) /* negative */ 93 #define PSR_Z_bit (1 << 30) /* zero */ 94 #define PSR_C_bit (1 << 29) /* carry */ 95 #define PSR_V_bit (1 << 28) /* overflow */ 96 97 #define I32_bit (1 << 7) /* IRQ disable */ 98 #define F32_bit (1 << 6) /* FIQ disable */ 99 100 #define PSR_MODE 0x0000001f /* mode mask */ 101 #define PSR_USR32_MODE 0x00000010 102 #define PSR_FIQ32_MODE 0x00000011 103 #define PSR_IRQ32_MODE 0x00000012 104 #define PSR_SVC32_MODE 0x00000013 105 #define PSR_ABT32_MODE 0x00000017 106 #define PSR_UND32_MODE 0x0000001b 107 #define PSR_32_MODE 0x00000010 108 109 #define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */ 110 #define PSR_IN_32_MODE(psr) ((psr) & PSR_32_MODE) 111 112 /* 113 * ARM Instructions 114 * 115 * 3 3 2 2 2 116 * 1 0 9 8 7 0 117 * +-------+-------------------------------------------------------+ 118 * | cond | instruction dependant | 119 * |c c c c| | 120 * +-------+-------------------------------------------------------+ 121 */ 122 123 #define INSN_SIZE 4 /* Always 4 bytes */ 124 #define INSN_COND_MASK 0xf0000000 /* Condition mask */ 125 #define INSN_COND_AL 0xe0000000 /* Always condition */ 126 127 /* Some of the definitions below need cleaning up for V3/V4 architectures */ 128 129 #define CPU_ID_DESIGNER_MASK 0xff000000 130 #define CPU_ID_ARM_LTD 0x41000000 131 #define CPU_ID_DEC 0x44000000 132 #define CPU_ID_TYPE_MASK 0x00ff0000 133 #define CPU_ID_ARM 0x00560000 134 #define CPU_ID_ARM7500 0x00020000 135 #define CPU_ID_CPU_MASK 0x0000fff0 136 #define ID_ARM610 0x00000610 137 #define ID_ARM700 0x00007000 138 #define ID_ARM710 0x00007100 139 #define ID_ARM810 0x00008100 140 #define ID_SA110 0x0000a100 141 #define ID_SA1100 0x0000a110 142 #define ID_SA1110 0x0000b110 143 144 #define CPU_ID_REVISION_MASK 0x0000000f 145 146 #define CPU_CONTROL_MMU_ENABLE 0x0001 147 #define CPU_CONTROL_AFLT_ENABLE 0x0002 148 #define CPU_CONTROL_DC_ENABLE 0x0004 149 #define CPU_CONTROL_WBUF_ENABLE 0x0008 150 #define CPU_CONTROL_32BP_ENABLE 0x0010 151 #define CPU_CONTROL_32BD_ENABLE 0x0020 152 #define CPU_CONTROL_LABT_ENABLE 0x0040 153 #define CPU_CONTROL_BEND_ENABLE 0x0080 154 #define CPU_CONTROL_SYST_ENABLE 0x0100 155 #define CPU_CONTROL_ROM_ENABLE 0x0200 156 #define CPU_CONTROL_CPCLK 0x0400 157 #define CPU_CONTROL_BPRD_ENABLE 0x0800 158 #define CPU_CONTROL_IC_ENABLE 0x1000 159 160 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 161 162 /* Fault status register definitions */ 163 164 #define FAULT_TYPE_MASK 0x0f 165 #define FAULT_USER 0x10 166 167 #define FAULT_WRTBUF_0 0x00 168 #define FAULT_WRTBUF_1 0x02 169 #define FAULT_BUSERR_0 0x04 170 #define FAULT_BUSERR_1 0x06 171 #define FAULT_BUSERR_2 0x08 172 #define FAULT_BUSERR_3 0x0a 173 #define FAULT_ALIGN_0 0x01 174 #define FAULT_ALIGN_1 0x03 175 #define FAULT_BUSTRNL1 0x0c 176 #define FAULT_BUSTRNL2 0x0e 177 #define FAULT_TRANS_S 0x05 178 #define FAULT_TRANS_P 0x07 179 #define FAULT_DOMAIN_S 0x09 180 #define FAULT_DOMAIN_P 0x0b 181 #define FAULT_PERM_S 0x0d 182 #define FAULT_PERM_P 0x0f 183 184 #ifdef _LOCORE 185 #define IRQdisable \ 186 stmfd sp!, {r0} ; \ 187 mrs r0, cpsr_all ; \ 188 orr r0, r0, #(I32_bit) ; \ 189 msr cpsr_all, r0 ; \ 190 ldmfd sp!, {r0} 191 192 #define IRQenable \ 193 stmfd sp!, {r0} ; \ 194 mrs r0, cpsr_all ; \ 195 bic r0, r0, #(I32_bit) ; \ 196 msr cpsr_all, r0 ; \ 197 ldmfd sp!, {r0} 198 199 #else 200 #define IRQdisable SetCPSR(I32_bit, I32_bit); 201 #define IRQenable SetCPSR(I32_bit, 0); 202 #endif /* _LOCORE */ 203 204 /* 205 * Return TRUE/FALSE (1/0) depending on whether the frame came from USR 206 * mode or not. 207 */ 208 209 #define CLKF_USERMODE(frame) ((frame->if_spsr & PSR_MODE) == PSR_USR32_MODE) 210 211 /* 212 * This needs straighening, prob is the frame does not have info on the priority 213 * a guess that needs trying is (current_spl_level == SPL0) 214 */ 215 216 #define CLKF_BASEPRI(frame) ((frame->if_spsr & PSR_MODE) == PSR_USR32_MODE) 217 218 #define CLKF_PC(frame) (frame->if_pc) 219 220 /*#define CLKF_INTR(frame) (current_intr_depth > 1)*/ 221 222 /* Hack to treat FPE time as interrupt time so we can measure it */ 223 #define CLKF_INTR(frame) ((current_intr_depth > 1) || (frame->if_spsr & PSR_MODE) == PSR_UND32_MODE) 224 225 #define PROC_PC(p) ((p)->p_md.md_regs->tf_pc) 226 227 /* 228 * definitions of cpu-dependent requirements 229 * referenced in generic code 230 */ 231 232 #ifndef _LOCORE 233 #include <sys/sched.h> 234 struct cpu_info { 235 struct schedstate_percpu ci_schedstate; /* scheduler state */ 236 #if defined(DIAGNOSTIC) || defined(LOCKDEBUG) 237 u_long ci_spin_locks; /* # of spin locks held */ 238 u_long ci_simple_locks; /* # of simple locks held */ 239 #endif 240 }; 241 #ifdef _KERNEL 242 extern struct cpu_info cpu_info_store; 243 #define curcpu() (&cpu_info_store) 244 #endif /* _KERNEL */ 245 #endif /* ! _LOCORE */ 246 247 #define cpu_wait(p) /* nothing */ 248 #define cpu_number() 0 249 250 /* 251 * Notify the current process (p) that it has a signal pending, 252 * process as soon as possible. 253 */ 254 255 #define signotify(p) setsoftast() 256 257 258 #if defined(_KERNEL) && !defined(_LOCORE) 259 extern int current_intr_depth; 260 261 /* 262 * Preempt the current process if in interrupt from user mode, 263 * or after the current trap/syscall if in system mode. 264 */ 265 int want_resched; /* resched() was called */ 266 #define need_resched(ci) (want_resched = 1, setsoftast()) 267 268 /* 269 * Give a profiling tick to the current process when the user profiling 270 * buffer pages are invalid. On the i386, request an ast to send us 271 * through trap(), marking the proc as needing a profiling tick. 272 */ 273 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, setsoftast()) 274 275 /* locore.S */ 276 void atomic_set_bit __P((u_int *address, u_int setmask)); 277 void atomic_clear_bit __P((u_int *address, u_int clearmask)); 278 279 /* cpuswitch.S */ 280 struct pcb; 281 void savectx __P((struct pcb *pcb)); 282 283 /* ast.c */ 284 void userret __P((register struct proc *p)); 285 286 /* machdep.h */ 287 void bootsync __P((void)); 288 289 /* strstr.c */ 290 char *strstr __P((const char *s1, const char *s2)); 291 292 /* syscall.c */ 293 void child_return __P((void *)); 294 295 #endif /* _KERNEL && !_LOCORE */ 296 297 /* 298 * CTL_MACHDEP definitions. 299 */ 300 #define CPU_DEBUG 1 /* int: misc kernel debug control */ 301 #define CPU_BOOTED_DEVICE 2 /* string: device we booted from */ 302 #define CPU_BOOTED_KERNEL 3 /* string: kernel we booted */ 303 #define CPU_CONSDEV 4 /* struct: dev_t of our console */ 304 #define CPU_MAXID 5 /* number of valid machdep ids */ 305 306 #define CTL_MACHDEP_NAMES { \ 307 { 0, 0 }, \ 308 { "debug", CTLTYPE_INT }, \ 309 { "booted_device", CTLTYPE_STRING }, \ 310 { "booted_kernel", CTLTYPE_STRING }, \ 311 { "console_device", CTLTYPE_STRUCT }, \ 312 } 313 314 #endif /* !_ARM32_CPU_H_ */ 315 316 /* End of cpu.h */ 317
Indexes created Thu Sep 25 06:09:39 GMT 2025