cpu.h revision 1.72
1 /* cpu.h,v 1.45.4.7 2008/01/28 18:20:39 matt Exp */ 2 3 /* 4 * Copyright (c) 1994-1996 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * cpu.h 40 * 41 * CPU specific symbols 42 * 43 * Created : 18/09/94 44 * 45 * Based on kate/katelib/arm6.h 46 */ 47 48 #ifndef _ARM_CPU_H_ 49 #define _ARM_CPU_H_ 50 51 /* 52 * User-visible definitions 53 */ 54 55 /* CTL_MACHDEP definitions. */ 56 #define CPU_DEBUG 1 /* int: misc kernel debug control */ 57 #define CPU_BOOTED_DEVICE 2 /* string: device we booted from */ 58 #define CPU_BOOTED_KERNEL 3 /* string: kernel we booted */ 59 #define CPU_CONSDEV 4 /* struct: dev_t of our console */ 60 #define CPU_POWERSAVE 5 /* int: use CPU powersave mode */ 61 #define CPU_MAXID 6 /* number of valid machdep ids */ 62 63 #if defined(_KERNEL) || defined(_KMEMUSER) 64 65 /* 66 * Kernel-only definitions 67 */ 68 69 #if !defined(_LKM) && defined(_KERNEL_OPT) 70 #include "opt_multiprocessor.h" 71 #include "opt_cpuoptions.h" 72 #include "opt_lockdebug.h" 73 #include "opt_cputypes.h" 74 #endif /* !_LKM && _KERNEL_OPT */ 75 76 #include <arm/cpuconf.h> 77 78 #ifndef _LOCORE 79 #include <machine/frame.h> 80 #endif /* !_LOCORE */ 81 82 #include <arm/armreg.h> 83 84 85 #ifndef _LOCORE 86 /* 1 == use cpu_sleep(), 0 == don't */ 87 extern int cpu_do_powersave; 88 #endif 89 90 #ifdef _LOCORE 91 92 #if defined(_ARM_ARCH_6) 93 #define IRQdisable cpsid i 94 #define IRQenable cpsie i 95 #elif defined(__PROG32) 96 #define IRQdisable \ 97 stmfd sp!, {r0} ; \ 98 mrs r0, cpsr ; \ 99 orr r0, r0, #(I32_bit) ; \ 100 msr cpsr_c, r0 ; \ 101 ldmfd sp!, {r0} 102 103 #define IRQenable \ 104 stmfd sp!, {r0} ; \ 105 mrs r0, cpsr ; \ 106 bic r0, r0, #(I32_bit) ; \ 107 msr cpsr_c, r0 ; \ 108 ldmfd sp!, {r0} 109 #else 110 /* Not yet used in 26-bit code */ 111 #endif 112 113 #if defined (TPIDRPRW_IS_CURCPU) 114 #define GET_CURCPU(rX) mrc p15, 0, rX, c13, c0, 4 115 #define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP] 116 #elif defined (TPIDRPRW_IS_CURLWP) 117 #define GET_CURLWP(rX) mrc p15, 0, rX, c13, c0, 4 118 #define GET_CURCPU(rX) GET_CURLWP(rX); ldr rX, [rX, #L_CPU] 119 #elif !defined(MULTIPROCESSOR) 120 #define GET_CURCPU(rX) ldr rX, =_C_LABEL(cpu_info_store) 121 #define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP] 122 #endif 123 #define GET_CURPCB(rX) GET_CURLWP(rX); ldr rX, [rX, #L_PCB] 124 125 #else /* !_LOCORE */ 126 127 #ifdef __PROG32 128 #define IRQdisable __set_cpsr_c(I32_bit, I32_bit); 129 #define IRQenable __set_cpsr_c(I32_bit, 0); 130 #else 131 #define IRQdisable set_r15(R15_IRQ_DISABLE, R15_IRQ_DISABLE); 132 #define IRQenable set_r15(R15_IRQ_DISABLE, 0); 133 #endif 134 135 #endif /* !_LOCORE */ 136 137 #ifndef _LOCORE 138 139 /* All the CLKF_* macros take a struct clockframe * as an argument. */ 140 141 /* 142 * CLKF_USERMODE: Return TRUE/FALSE (1/0) depending on whether the 143 * frame came from USR mode or not. 144 */ 145 #ifdef __PROG32 146 #define CLKF_USERMODE(frame) ((frame->cf_tf.tf_spsr & PSR_MODE) == PSR_USR32_MODE) 147 #else 148 #define CLKF_USERMODE(frame) ((frame->cf_if.if_r15 & R15_MODE) == R15_MODE_USR) 149 #endif 150 151 /* 152 * CLKF_INTR: True if we took the interrupt from inside another 153 * interrupt handler. 154 */ 155 #ifdef __PROG32 156 /* Hack to treat FPE time as interrupt time so we can measure it */ 157 #define CLKF_INTR(frame) \ 158 ((curcpu()->ci_intr_depth > 1) || \ 159 (frame->cf_tf.tf_spsr & PSR_MODE) == PSR_UND32_MODE) 160 #else 161 #define CLKF_INTR(frame) (curcpu()->ci_intr_depth > 1) 162 #endif 163 164 /* 165 * CLKF_PC: Extract the program counter from a clockframe 166 */ 167 #ifdef __PROG32 168 #define CLKF_PC(frame) (frame->cf_tf.tf_pc) 169 #else 170 #define CLKF_PC(frame) (frame->cf_if.if_r15 & R15_PC) 171 #endif 172 173 /* 174 * LWP_PC: Find out the program counter for the given lwp. 175 */ 176 #ifdef __PROG32 177 #define LWP_PC(l) (lwp_trapframe(l)->tf_pc) 178 #else 179 #define LWP_PC(l) (lwp_trapframe(l)->tf_r15 & R15_PC) 180 #endif 181 182 /* 183 * Validate a PC or PSR for a user process. Used by various system calls 184 * that take a context passed by the user and restore it. 185 */ 186 187 #ifdef __PROG32 188 #define VALID_R15_PSR(r15,psr) \ 189 (((psr) & PSR_MODE) == PSR_USR32_MODE && \ 190 ((psr) & (I32_bit | F32_bit)) == 0) 191 #else 192 #define VALID_R15_PSR(r15,psr) \ 193 (((r15) & R15_MODE) == R15_MODE_USR && \ 194 ((r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)) == 0) 195 #endif 196 197 198 199 /* The address of the vector page. */ 200 extern vaddr_t vector_page; 201 #ifdef __PROG32 202 void arm32_vector_init(vaddr_t, int); 203 204 #define ARM_VEC_RESET (1 << 0) 205 #define ARM_VEC_UNDEFINED (1 << 1) 206 #define ARM_VEC_SWI (1 << 2) 207 #define ARM_VEC_PREFETCH_ABORT (1 << 3) 208 #define ARM_VEC_DATA_ABORT (1 << 4) 209 #define ARM_VEC_ADDRESS_EXCEPTION (1 << 5) 210 #define ARM_VEC_IRQ (1 << 6) 211 #define ARM_VEC_FIQ (1 << 7) 212 213 #define ARM_NVEC 8 214 #define ARM_VEC_ALL 0xffffffff 215 #endif 216 217 /* 218 * Per-CPU information. For now we assume one CPU. 219 */ 220 static inline int curcpl(void); 221 static inline void set_curcpl(int); 222 static inline void cpu_dosoftints(void); 223 224 #include <sys/device_if.h> 225 #include <sys/evcnt.h> 226 #include <sys/cpu_data.h> 227 228 struct cpu_info { 229 struct cpu_data ci_data; /* MI per-cpu data */ 230 device_t ci_dev; /* Device corresponding to this CPU */ 231 cpuid_t ci_cpuid; 232 uint32_t ci_arm_cpuid; /* aggregate CPU id */ 233 uint32_t ci_arm_cputype; /* CPU type */ 234 uint32_t ci_arm_cpurev; /* CPU revision */ 235 uint32_t ci_ctrl; /* The CPU control register */ 236 int ci_cpl; /* current processor level (spl) */ 237 int ci_astpending; /* */ 238 int ci_want_resched; /* resched() was called */ 239 int ci_intr_depth; /* */ 240 struct cpu_softc *ci_softc; /* platform softc */ 241 #ifdef __HAVE_FAST_SOFTINTS 242 lwp_t *ci_softlwps[SOFTINT_COUNT]; 243 volatile uint32_t ci_softints; 244 #endif 245 lwp_t *ci_curlwp; /* current lwp */ 246 struct evcnt ci_arm700bugcount; 247 int32_t ci_mtx_count; 248 int ci_mtx_oldspl; 249 register_t ci_undefsave[3]; 250 uint32_t ci_vfp_id; 251 #if defined(_ARM_ARCH_7) 252 uint64_t ci_lastintr; 253 #endif 254 #if defined(MP_CPU_INFO_MEMBERS) 255 MP_CPU_INFO_MEMBERS 256 #endif 257 }; 258 259 extern struct cpu_info cpu_info_store; 260 #if defined(TPIDRPRW_IS_CURLWP) 261 static inline struct lwp * 262 _curlwp(void) 263 { 264 return (struct lwp *) armreg_tpidrprw_read(); 265 } 266 267 static inline void 268 _curlwp_set(struct lwp *l) 269 { 270 armreg_tpidrprw_write((uintptr_t)l); 271 } 272 273 #define curlwp (_curlwp()) 274 static inline struct cpu_info * 275 curcpu(void) 276 { 277 return curlwp->l_cpu; 278 } 279 #elif defined(TPIDRPRW_IS_CURCPU) 280 static inline struct cpu_info * 281 curcpu(void) 282 { 283 return (struct cpu_info *) armreg_tpidrprw_read(); 284 } 285 #elif !defined(MULTIPROCESSOR) 286 #define curcpu() (&cpu_info_store) 287 #else 288 #error MULTIPROCESSOR requires TPIDRPRW_IS_CURLWP or TPIDRPRW_IS_CURCPU 289 #endif /* !TPIDRPRW_IS_CURCPU && !TPIDRPRW_IS_CURLWP */ 290 291 #ifndef curlwp 292 #define curlwp (curcpu()->ci_curlwp) 293 #endif 294 295 #define CPU_INFO_ITERATOR int 296 #if defined(MULTIPROCESSOR) 297 extern struct cpu_info *cpu_info[]; 298 #define cpu_number() (curcpu()->ci_cpuid) 299 void cpu_boot_secondary_processors(void); 300 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 301 #define CPU_INFO_FOREACH(cii, ci) \ 302 cii = 0, ci = cpu_info[0]; cii < ncpu && (ci = cpu_info[cii]) != NULL; cii++ 303 #else 304 #define cpu_number() 0 305 306 #define CPU_IS_PRIMARY(ci) true 307 #define CPU_INFO_FOREACH(cii, ci) \ 308 cii = 0, ci = curcpu(); ci != NULL; ci = NULL 309 #endif 310 311 #define LWP0_CPU_INFO (&cpu_info_store) 312 313 static inline int 314 curcpl(void) 315 { 316 return curcpu()->ci_cpl; 317 } 318 319 static inline void 320 set_curcpl(int pri) 321 { 322 curcpu()->ci_cpl = pri; 323 } 324 325 static inline void 326 cpu_dosoftints(void) 327 { 328 #ifdef __HAVE_FAST_SOFTINTS 329 void dosoftints(void); 330 #ifndef __HAVE_PIC_FAST_SOFTINTS 331 struct cpu_info * const ci = curcpu(); 332 if (ci->ci_intr_depth == 0 && (ci->ci_softints >> ci->ci_cpl) > 0) 333 dosoftints(); 334 #endif 335 #endif 336 } 337 338 #ifdef __PROG32 339 void cpu_proc_fork(struct proc *, struct proc *); 340 #else 341 #define cpu_proc_fork(p1, p2) 342 #endif 343 344 /* 345 * Scheduling glue 346 */ 347 348 #define setsoftast() (curcpu()->ci_astpending = 1) 349 350 /* 351 * Notify the current process (p) that it has a signal pending, 352 * process as soon as possible. 353 */ 354 355 #define cpu_signotify(l) setsoftast() 356 357 /* 358 * Give a profiling tick to the current process when the user profiling 359 * buffer pages are invalid. On the i386, request an ast to send us 360 * through trap(), marking the proc as needing a profiling tick. 361 */ 362 #define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, setsoftast()) 363 364 /* 365 * We've already preallocated the stack for the idlelwps for additional CPUs. 366 * This hook allows to return them. 367 */ 368 vaddr_t cpu_uarea_alloc_idlelwp(struct cpu_info *); 369 370 #ifndef acorn26 371 /* 372 * cpu device glue (belongs in cpuvar.h) 373 */ 374 void cpu_attach(device_t, cpuid_t); 375 #endif 376 377 /* 378 * Random cruft 379 */ 380 381 struct lwp; 382 383 /* locore.S */ 384 void atomic_set_bit(u_int *, u_int); 385 void atomic_clear_bit(u_int *, u_int); 386 387 /* cpuswitch.S */ 388 struct pcb; 389 void savectx(struct pcb *); 390 391 /* ast.c */ 392 void userret(register struct lwp *); 393 394 /* *_machdep.c */ 395 void bootsync(void); 396 397 /* fault.c */ 398 int badaddr_read(void *, size_t, void *); 399 400 /* syscall.c */ 401 void swi_handler(trapframe_t *); 402 403 /* arm_machdep.c */ 404 void ucas_ras_check(trapframe_t *); 405 406 /* vfp_init.c */ 407 void vfp_attach(void); 408 void vfp_discardcontext(void); 409 void vfp_savecontext(void); 410 extern const pcu_ops_t arm_vfp_ops; 411 412 #endif /* !_LOCORE */ 413 414 #endif /* _KERNEL */ 415 416 #endif /* !_ARM_CPU_H_ */ 417
Indexes created Tue Sep 23 14:10:03 GMT 2025