ieee.h revision 1.10 1 /* $NetBSD: ieee.h,v 1.10 2014/01/29 01:34:44 matt Exp $ */
2
3 /*-
4 * Copyright (c) 2014 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas of 3am Software Foundry.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * ieee.h defines the machine-dependent layout of the machine's IEEE
34 * floating point. It does *not* define (yet?) any of the rounding
35 * mode bits, exceptions, and so forth.
36 */
37
38 #ifndef _ARM_IEEE_H_
39 #define _ARM_IEEE_H_
40
41 #include <sys/ieee754.h>
42
43 #if 0
44 #define SNG_QUIETNAN (1 << 22)
45 #define DBL_QUIETNAN (1 << 19)
46 #endif
47
48 #ifdef __ARM_PCS_AAPCS64
49
50 /*
51 * The AArch64 architecture defines the following IEEE 754 compliant
52 * 128-bit extended-precision format.
53 */
54
55 #define EXT_EXPBITS 15
56 #define EXT_FRACHBITS 48
57 #define EXT_FRACLBITS 64
58 #define EXT_FRACBITS (EXT_FRACLBITS + EXT_FRACHBITS)
59
60 #define EXT_TO_ARRAY32(u, a) do { \
61 (a)[0] = (uint32_t)((u).extu_ext.ext_fracl >> 0); \
62 (a)[1] = (uint32_t)((u).extu_ext.ext_fracl >> 32); \
63 (a)[2] = (uint32_t)((u).extu_ext.ext_frach >> 0); \
64 (a)[3] = (uint32_t)((u).extu_ext.ext_frach >> 32); \
65 } while(/*CONSTCOND*/0)
66
67 struct ieee_ext {
68 #ifdef __AARCH64EB__
69 uint64_t ext_sign:1;
70 uint64_t ext_exp:EXT_EXPBITS;
71 uint64_t ext_frach:EXT_FRACHBITS;
72 uint64_t ext_fracl;
73 #else
74 uint64_t ext_fracl;
75 uint64_t ext_frach:EXT_FRACHBITS;
76 uint64_t ext_exp:EXT_EXPBITS;
77 uint64_t ext_sign:1;
78 #endif
79 };
80
81 /*
82 * Floats whose exponent is in [1..INFNAN) (of whatever type) are
83 * `normal'. Floats whose exponent is INFNAN are either Inf or NaN.
84 * Floats whose exponent is zero are either zero (iff all fraction
85 * bits are zero) or subnormal values.
86 *
87 * A NaN is a `signalling NaN' if its QUIETNAN bit is clear in its
88 * high fraction; if the bit is set, it is a `quiet NaN'.
89 */
90 #define EXT_EXP_INFNAN 0x7fff
91 #define EXT_EXP_INF 0x7fff
92 #define EXT_EXP_NAN 0x7fff
93
94 #if 0
95 #define EXT_QUIETNAN (1 << 15)
96 #endif
97
98 /*
99 * Exponent biases.
100 */
101 #define EXT_EXP_BIAS 16383
102
103 /*
104 * Convenience data structures.
105 */
106 union ieee_ext_u {
107 long double extu_ld;
108 struct ieee_ext extu_ext;
109 };
110
111 #define extu_exp extu_ext.ext_exp
112 #define extu_sign extu_ext.ext_sign
113 #define extu_fracl extu_ext.ext_fracl
114 #define extu_frach extu_ext.ext_frach
115
116 #define LDBL_IMPLICIT_NBIT 1 /* our NBIT is implicit */
117
118 #endif /* __ARM_PCS_AAPCS64 */
119
120 #endif /* !_ARM_IEEE_H_ */
121