1 1.14 andvar /* $NetBSD: vidc.h,v 1.14 2024/02/05 21:39:52 andvar Exp $ */ 2 1.1 reinoud 3 1.1 reinoud /* 4 1.1 reinoud * Copyright (c) 1994,1995 Mark Brinicombe. 5 1.1 reinoud * Copyright (c) 1994,1995 Brini. 6 1.1 reinoud * All rights reserved. 7 1.1 reinoud * 8 1.1 reinoud * This code is derived from software written for Brini by Mark Brinicombe 9 1.1 reinoud * 10 1.1 reinoud * Redistribution and use in source and binary forms, with or without 11 1.1 reinoud * modification, are permitted provided that the following conditions 12 1.1 reinoud * are met: 13 1.1 reinoud * 1. Redistributions of source code must retain the above copyright 14 1.1 reinoud * notice, this list of conditions and the following disclaimer. 15 1.1 reinoud * 2. Redistributions in binary form must reproduce the above copyright 16 1.1 reinoud * notice, this list of conditions and the following disclaimer in the 17 1.1 reinoud * documentation and/or other materials provided with the distribution. 18 1.1 reinoud * 3. All advertising materials mentioning features or use of this software 19 1.1 reinoud * must display the following acknowledgement: 20 1.1 reinoud * This product includes software developed by Brini. 21 1.1 reinoud * 4. The name of the company nor the name of the author may be used to 22 1.1 reinoud * endorse or promote products derived from this software without specific 23 1.1 reinoud * prior written permission. 24 1.1 reinoud * 25 1.1 reinoud * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 1.1 reinoud * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 1.1 reinoud * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 1.1 reinoud * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 1.1 reinoud * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 1.1 reinoud * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 1.1 reinoud * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 1.1 reinoud * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 1.1 reinoud * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 1.1 reinoud * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 1.1 reinoud * SUCH DAMAGE. 36 1.1 reinoud * 37 1.1 reinoud * RiscBSD kernel project 38 1.1 reinoud * 39 1.1 reinoud * vidc.h 40 1.1 reinoud * 41 1.1 reinoud * VIDC20 registers 42 1.1 reinoud * 43 1.1 reinoud * Created : 18/09/94 44 1.1 reinoud * 45 1.1 reinoud * Based on kate/display/vidc.h 46 1.1 reinoud */ 47 1.1 reinoud 48 1.1 reinoud /* 49 1.14 andvar * This should be private to the vidc directory but there are still dependencies 50 1.1 reinoud * between the vidc and the riscpc virtual console (struct vidc_mode) that 51 1.1 reinoud * means this file must be exported to userland. 52 1.1 reinoud * With the import of the new console code this will go away. 53 1.1 reinoud */ 54 1.1 reinoud 55 1.1 reinoud #ifndef _ARM32_VIDC_H_ 56 1.1 reinoud #define _ARM32_VIDC_H_ 57 1.1 reinoud 58 1.11 bjh21 #include <dev/videomode/videomode.h> 59 1.1 reinoud #include <machine/vidc_machdep.h> 60 1.1 reinoud 61 1.1 reinoud /* 62 1.1 reinoud * Current VIDC base set in initarm() 63 1.1 reinoud * since the current code isnt busspaceified, we need to set it manually ... 64 1.1 reinoud * this is to allow the VIDC to be moved. 65 1.1 reinoud */ 66 1.1 reinoud extern int *vidc_base; 67 1.1 reinoud 68 1.1 reinoud 69 1.1 reinoud /* Video registers */ 70 1.1 reinoud 71 1.1 reinoud #define VIDC_PALETTE 0x00000000 72 1.1 reinoud #define VIDC_PALREG 0x10000000 73 1.1 reinoud 74 1.1 reinoud #define VIDC_BCOL 0x40000000 75 1.1 reinoud #define VIDC_CP0 0x40000000 76 1.1 reinoud #define VIDC_CP1 0x50000000 77 1.1 reinoud #define VIDC_CP2 0x60000000 78 1.1 reinoud #define VIDC_CP3 0x70000000 79 1.1 reinoud 80 1.1 reinoud #define VIDC_HCR 0x80000000 81 1.1 reinoud #define VIDC_HSWR 0x81000000 82 1.1 reinoud #define VIDC_HBSR 0x82000000 83 1.1 reinoud #define VIDC_HDSR 0x83000000 84 1.1 reinoud #define VIDC_HDER 0x84000000 85 1.1 reinoud #define VIDC_HBER 0x85000000 86 1.1 reinoud #define VIDC_HCSR 0x86000000 87 1.1 reinoud #define VIDC_HIR 0x87000000 88 1.1 reinoud 89 1.1 reinoud #define VIDC_VCR 0x90000000 90 1.1 reinoud #define VIDC_VSWR 0x91000000 91 1.1 reinoud #define VIDC_VBSR 0x92000000 92 1.1 reinoud #define VIDC_VDSR 0x93000000 93 1.1 reinoud #define VIDC_VDER 0x94000000 94 1.1 reinoud #define VIDC_VBER 0x95000000 95 1.1 reinoud #define VIDC_VCSR 0x96000000 96 1.1 reinoud #define VIDC_VCER 0x97000000 97 1.1 reinoud 98 1.1 reinoud #define VIDC_EREG 0xc0000000 99 1.1 reinoud #define VIDC_FSYNREG 0xd0000000 100 1.1 reinoud #define VIDC_CONREG 0xe0000000 101 1.1 reinoud #define VIDC_DCTL 0xf0000000 102 1.1 reinoud 103 1.1 reinoud /* VIDC palette macros */ 104 1.1 reinoud 105 1.1 reinoud #define VIDC_RED(r) (r) 106 1.4 bjh21 #define VIDC_GREEN(g) ((g) << 8) 107 1.4 bjh21 #define VIDC_BLUE(b) ((b) << 16) 108 1.1 reinoud #define VIDC_COL(r, g, b) (VIDC_RED(r) | VIDC_GREEN(g) | VIDC_BLUE(b)) 109 1.1 reinoud 110 1.1 reinoud 111 1.1 reinoud /* Sound registers */ 112 1.1 reinoud 113 1.1 reinoud #define VIDC_SIR0 0xa0000000 114 1.1 reinoud #define VIDC_SIR1 0xa1000000 115 1.1 reinoud #define VIDC_SIR2 0xa2000000 116 1.1 reinoud #define VIDC_SIR3 0xa3000000 117 1.1 reinoud #define VIDC_SIR4 0xa4000000 118 1.1 reinoud #define VIDC_SIR5 0xa5000000 119 1.1 reinoud #define VIDC_SIR6 0xa6000000 120 1.1 reinoud #define VIDC_SIR7 0xa7000000 121 1.1 reinoud 122 1.1 reinoud #define VIDC_SFR 0xb0000000 123 1.1 reinoud #define VIDC_SCR 0xb1000000 124 1.1 reinoud 125 1.1 reinoud #define SIR_LEFT_100 0x01 126 1.1 reinoud #define SIR_LEFT_83 0x02 127 1.1 reinoud #define SIR_LEFT_67 0x03 128 1.1 reinoud #define SIR_CENTRE 0x04 129 1.1 reinoud #define SIR_RIGHT_67 0x05 130 1.1 reinoud #define SIR_RIGHT_83 0x06 131 1.1 reinoud #define SIR_RIGHT_100 0x07 132 1.1 reinoud 133 1.7 bjh21 #define SCR_SCLR 0x08 134 1.7 bjh21 #define SCR_SDAC 0x04 135 1.7 bjh21 #define SCR_SERIAL 0x02 136 1.7 bjh21 #define SCR_CLKSEL 0x01 137 1.7 bjh21 138 1.1 reinoud /* Video display addresses */ 139 1.1 reinoud 140 1.1 reinoud /* Where the display memory is mapped */ 141 1.1 reinoud /* note that there's not normally more than 2MB */ 142 1.1 reinoud #define VMEM_VBASE 0xf7000000 143 1.1 reinoud 144 1.1 reinoud /* Where the VRAM will be found */ 145 1.1 reinoud 146 1.1 reinoud #define VRAM_BASE 0x02000000 147 1.1 reinoud 148 1.1 reinoud #ifndef _LOCORE 149 1.1 reinoud 150 1.1 reinoud /* Video memory descriptor */ 151 1.1 reinoud 152 1.1 reinoud typedef struct 153 1.1 reinoud { 154 1.1 reinoud u_int vidm_vbase; /* virtual base of video memory */ 155 1.1 reinoud u_int vidm_pbase; /* physical base of video memory */ 156 1.1 reinoud u_int vidm_size; /* video memory size */ 157 1.1 reinoud int vidm_type; /* video memory type */ 158 1.1 reinoud } videomemory_t; 159 1.1 reinoud 160 1.1 reinoud #define VIDEOMEM_TYPE_VRAM 0x01 161 1.1 reinoud #define VIDEOMEM_TYPE_DRAM 0x02 162 1.1 reinoud 163 1.1 reinoud /* Structures and prototypes for vidc handling functions */ 164 1.1 reinoud 165 1.1 reinoud struct vidc_state { 166 1.1 reinoud int palette[256]; 167 1.1 reinoud int palreg; 168 1.1 reinoud int bcol; 169 1.1 reinoud int cp1; 170 1.1 reinoud int cp2; 171 1.1 reinoud int cp3; 172 1.1 reinoud int hcr, hswr, hbsr, hdsr, hder, hber, hcsr; 173 1.1 reinoud int hir; 174 1.1 reinoud int vcr, vswr, vbsr, vdsr, vder, vber, vcsr, vcer; 175 1.1 reinoud int ereg; 176 1.1 reinoud int fsynreg; 177 1.1 reinoud int conreg; 178 1.1 reinoud int dctl; 179 1.1 reinoud }; 180 1.1 reinoud 181 1.1 reinoud extern int vidc_fref; /* reference frequency of detected VIDC */ 182 1.1 reinoud 183 1.1 reinoud extern struct vidc_state vidc_current[]; 184 1.1 reinoud 185 1.1 reinoud struct vidc_mode { 186 1.11 bjh21 struct videomode timings; 187 1.11 bjh21 int log2_bpp; 188 1.1 reinoud }; 189 1.1 reinoud 190 1.1 reinoud #endif /* !_LOCORE */ 191 1.1 reinoud 192 1.1 reinoud #endif /* !_ARM32_VIDC_H */ 193 1.1 reinoud 194 1.1 reinoud /* End of vidc.h */ 195 1.1 reinoud 196