ixp12x0.c revision 1.2.2.3
1 1.2.2.3 thorpej /* $NetBSD: ixp12x0.c,v 1.2.2.3 2002/12/11 05:53:09 thorpej Exp $ */ 2 1.2.2.2 nathanw /* 3 1.2.2.2 nathanw * Copyright (c) 2002 4 1.2.2.2 nathanw * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 5 1.2.2.2 nathanw * All rights reserved. 6 1.2.2.2 nathanw * 7 1.2.2.2 nathanw * Redistribution and use in source and binary forms, with or without 8 1.2.2.2 nathanw * modification, are permitted provided that the following conditions 9 1.2.2.2 nathanw * are met: 10 1.2.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 11 1.2.2.2 nathanw * notice, this list of conditions and the following disclaimer. 12 1.2.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 13 1.2.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 14 1.2.2.2 nathanw * documentation and/or other materials provided with the distribution. 15 1.2.2.2 nathanw * 3. All advertising materials mentioning features or use of this software 16 1.2.2.2 nathanw * must display the following acknowledgement: 17 1.2.2.2 nathanw * This product includes software developed by Ichiro FUKUHARA. 18 1.2.2.2 nathanw * 4. The name of the company nor the name of the author may be used to 19 1.2.2.2 nathanw * endorse or promote products derived from this software without specific 20 1.2.2.2 nathanw * prior written permission. 21 1.2.2.2 nathanw * 22 1.2.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 23 1.2.2.2 nathanw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 1.2.2.2 nathanw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 1.2.2.2 nathanw * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 26 1.2.2.2 nathanw * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 1.2.2.2 nathanw * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 1.2.2.2 nathanw * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 1.2.2.2 nathanw * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 1.2.2.2 nathanw * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 1.2.2.2 nathanw * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 1.2.2.2 nathanw * SUCH DAMAGE. 33 1.2.2.2 nathanw */ 34 1.2.2.2 nathanw 35 1.2.2.2 nathanw #include <sys/param.h> 36 1.2.2.2 nathanw #include <sys/systm.h> 37 1.2.2.2 nathanw #include <sys/device.h> 38 1.2.2.2 nathanw #include <uvm/uvm.h> 39 1.2.2.2 nathanw 40 1.2.2.2 nathanw #include <machine/bus.h> 41 1.2.2.2 nathanw 42 1.2.2.2 nathanw #include <arm/ixp12x0/ixp12x0reg.h> 43 1.2.2.2 nathanw #include <arm/ixp12x0/ixp12x0var.h> 44 1.2.2.2 nathanw #include <arm/ixp12x0/ixp12x0_pcireg.h> 45 1.2.2.2 nathanw 46 1.2.2.2 nathanw int ixp12x0_pcibus_print(void *, const char *); 47 1.2.2.2 nathanw 48 1.2.2.2 nathanw static struct ixp12x0_softc *ixp12x0_softc; 49 1.2.2.2 nathanw 50 1.2.2.2 nathanw void 51 1.2.2.2 nathanw ixp12x0_attach(sc) 52 1.2.2.2 nathanw struct ixp12x0_softc *sc; 53 1.2.2.2 nathanw { 54 1.2.2.2 nathanw struct pcibus_attach_args pba; 55 1.2.2.2 nathanw pcireg_t reg; 56 1.2.2.2 nathanw 57 1.2.2.2 nathanw ixp12x0_softc = sc; 58 1.2.2.2 nathanw 59 1.2.2.2 nathanw printf("\n"); 60 1.2.2.2 nathanw /* 61 1.2.2.2 nathanw * Subregion for PCI Configuration Spase Registers 62 1.2.2.2 nathanw */ 63 1.2.2.2 nathanw if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, 64 1.2.2.2 nathanw IXP12X0_PCI_SIZE, &sc->sc_pci_ioh)) 65 1.2.2.2 nathanw panic("%s: unable to subregion PCI registers", 66 1.2.2.2 nathanw sc->sc_dev.dv_xname); 67 1.2.2.2 nathanw /* 68 1.2.2.2 nathanw * PCI bus reset 69 1.2.2.2 nathanw */ 70 1.2.2.2 nathanw /* XXX assert PCI reset Mode */ 71 1.2.2.2 nathanw reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 72 1.2.2.2 nathanw SA_CONTROL) &~ SA_CONTROL_PNR; 73 1.2.2.2 nathanw bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 74 1.2.2.2 nathanw SA_CONTROL, reg); 75 1.2.2.2 nathanw DELAY(10); 76 1.2.2.2 nathanw 77 1.2.2.2 nathanw /* XXX Disable door bell and outbound interrupt */ 78 1.2.2.2 nathanw bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 79 1.2.2.2 nathanw PCI_CAP_PTR, 0xc); 80 1.2.2.2 nathanw /* Disable door bell int to PCI */ 81 1.2.2.2 nathanw bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 82 1.2.2.2 nathanw DBELL_PCI_MASK, 0x0); 83 1.2.2.2 nathanw /* Disable door bell int to SA-core */ 84 1.2.2.2 nathanw bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 85 1.2.2.2 nathanw DBELL_SA_MASK, 0x0); 86 1.2.2.2 nathanw 87 1.2.2.2 nathanw bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 88 1.2.2.2 nathanw PCI_ADDR_EXT, 0); 89 1.2.2.2 nathanw 90 1.2.2.2 nathanw /* XXX Negate PCI reset */ 91 1.2.2.2 nathanw reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 92 1.2.2.2 nathanw SA_CONTROL) | SA_CONTROL_PNR; 93 1.2.2.2 nathanw bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 94 1.2.2.2 nathanw SA_CONTROL, reg); 95 1.2.2.2 nathanw DELAY(10); 96 1.2.2.2 nathanw /* 97 1.2.2.2 nathanw * specify window size of memory access and SDRAM. 98 1.2.2.2 nathanw */ 99 1.2.2.2 nathanw reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 100 1.2.2.2 nathanw IXP_PCI_MEM_BAR) | IXP1200_PCI_MEM_BAR; 101 1.2.2.2 nathanw bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 102 1.2.2.2 nathanw IXP_PCI_MEM_BAR, reg); 103 1.2.2.2 nathanw 104 1.2.2.2 nathanw reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 105 1.2.2.2 nathanw IXP_PCI_IO_BAR) | IXP1200_PCI_IO_BAR; 106 1.2.2.2 nathanw bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 107 1.2.2.2 nathanw IXP_PCI_IO_BAR, reg); 108 1.2.2.2 nathanw 109 1.2.2.2 nathanw reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 110 1.2.2.2 nathanw IXP_PCI_DRAM_BAR) | IXP1200_PCI_DRAM_BAR; 111 1.2.2.2 nathanw bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 112 1.2.2.2 nathanw IXP_PCI_DRAM_BAR, reg); 113 1.2.2.2 nathanw 114 1.2.2.2 nathanw bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 115 1.2.2.2 nathanw CSR_BASE_ADDR_MASK, CSR_BASE_ADDR_MASK_1M); 116 1.2.2.2 nathanw bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 117 1.2.2.2 nathanw DRAM_BASE_ADDR_MASK, DRAM_BASE_ADDR_MASK_256MB); 118 1.2.2.2 nathanw 119 1.2.2.2 nathanw #if DEBUG 120 1.2.2.2 nathanw printf("IXP_PCI_MEM_BAR = 0x%08x\nIXP_PCI_IO_BAR = 0x%08x\nIXP_PCI_DRAM_BAR = 0x%08x\nCSR_BASE_ADDR_MASK = 0x%08x\n", 121 1.2.2.2 nathanw bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_MEM_BAR), 122 1.2.2.2 nathanw bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_IO_BAR), 123 1.2.2.2 nathanw bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_DRAM_BAR), 124 1.2.2.2 nathanw bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, DRAM_BASE_ADDR_MASK)); 125 1.2.2.2 nathanw #endif 126 1.2.2.2 nathanw /* Initialize complete */ 127 1.2.2.2 nathanw reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 128 1.2.2.2 nathanw SA_CONTROL) | 0x1; 129 1.2.2.2 nathanw bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 130 1.2.2.2 nathanw SA_CONTROL, reg); 131 1.2.2.2 nathanw #if DEBUG 132 1.2.2.2 nathanw printf("SA_CONTROL = 0x%08x\n", 133 1.2.2.2 nathanw bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, SA_CONTROL)); 134 1.2.2.2 nathanw #endif 135 1.2.2.2 nathanw /* 136 1.2.2.2 nathanw * Enable bus mastering and I/O,memory access 137 1.2.2.2 nathanw */ 138 1.2.2.2 nathanw /* host only */ 139 1.2.2.2 nathanw reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 140 1.2.2.2 nathanw PCI_COMMAND_STATUS_REG) | 141 1.2.2.2 nathanw PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 142 1.2.2.2 nathanw PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE; 143 1.2.2.2 nathanw bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 144 1.2.2.2 nathanw PCI_COMMAND_STATUS_REG, reg); 145 1.2.2.2 nathanw #if DEBUG 146 1.2.2.2 nathanw printf("PCI_COMMAND_STATUS_REG = 0x%08x\n", 147 1.2.2.2 nathanw bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, PCI_COMMAND_STATUS_REG)); 148 1.2.2.2 nathanw #endif 149 1.2.2.2 nathanw /* 150 1.2.2.2 nathanw * Initialize the bus space and DMA tags and the PCI chipset tag. 151 1.2.2.2 nathanw */ 152 1.2.2.2 nathanw ixp12x0_io_bs_init(&sc->ia_pci_iot, sc); 153 1.2.2.2 nathanw ixp12x0_mem_bs_init(&sc->ia_pci_memt, sc); 154 1.2.2.2 nathanw ixp12x0_pci_init(&sc->ia_pci_chipset, sc); 155 1.2.2.2 nathanw ixp12x0_pci_dma_init(&sc->ia_pci_dmat, sc); 156 1.2.2.2 nathanw 157 1.2.2.2 nathanw /* 158 1.2.2.2 nathanw * Attach the PCI bus. 159 1.2.2.2 nathanw */ 160 1.2.2.2 nathanw pba.pba_busname = "pci"; 161 1.2.2.2 nathanw pba.pba_pc = &sc->ia_pci_chipset; 162 1.2.2.2 nathanw pba.pba_iot = &sc->ia_pci_iot; 163 1.2.2.2 nathanw pba.pba_memt = &sc->ia_pci_memt; 164 1.2.2.2 nathanw pba.pba_dmat = &sc->ia_pci_dmat; 165 1.2.2.2 nathanw pba.pba_bus = 0; /* bus number = 0 */ 166 1.2.2.2 nathanw pba.pba_intrswiz = 0; /* XXX */ 167 1.2.2.2 nathanw pba.pba_intrtag = 0; 168 1.2.2.2 nathanw pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 169 1.2.2.2 nathanw PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 170 1.2.2.2 nathanw (void) config_found(&sc->sc_dev, &pba, ixp12x0_pcibus_print); 171 1.2.2.2 nathanw } 172 1.2.2.2 nathanw 173 1.2.2.2 nathanw int 174 1.2.2.2 nathanw ixp12x0_pcibus_print(void *aux, const char *pnp) 175 1.2.2.2 nathanw { 176 1.2.2.2 nathanw struct pcibus_attach_args *pba = aux; 177 1.2.2.2 nathanw 178 1.2.2.2 nathanw if (pnp) 179 1.2.2.2 nathanw printf("%s at %s", pba->pba_busname, pnp); 180 1.2.2.2 nathanw 181 1.2.2.2 nathanw printf(" bus %d", pba->pba_bus); 182 1.2.2.2 nathanw 183 1.2.2.2 nathanw return (UNCONF); 184 1.2.2.2 nathanw } 185 1.2.2.2 nathanw 186 1.2.2.2 nathanw /* 187 1.2.2.2 nathanw * IXP12x0 specific I/O registers mapping table 188 1.2.2.2 nathanw */ 189 1.2.2.2 nathanw static struct pmap_ent map_tbl_ixp12x0[] = { 190 1.2.2.2 nathanw { "StrongARM System and Peripheral Registers", 191 1.2.2.2 nathanw IXP12X0_SYS_VBASE, IXP12X0_SYS_HWBASE, 192 1.2.2.2 nathanw IXP12X0_SYS_SIZE, 193 1.2.2.2 nathanw VM_PROT_READ|VM_PROT_WRITE, 194 1.2.2.2 nathanw PTE_NOCACHE, }, 195 1.2.2.2 nathanw 196 1.2.2.2 nathanw { "PCI Registers Accessible Through StrongARM Core", 197 1.2.2.2 nathanw IXP12X0_PCI_VBASE, IXP12X0_PCI_HWBASE, 198 1.2.2.2 nathanw IXP12X0_PCI_SIZE, 199 1.2.2.2 nathanw VM_PROT_READ|VM_PROT_WRITE, 200 1.2.2.2 nathanw PTE_NOCACHE, }, 201 1.2.2.2 nathanw 202 1.2.2.2 nathanw { "PCI Registers Accessible Through I/O Cycle Access", 203 1.2.2.2 nathanw IXP12X0_PCI_IO_VBASE, IXP12X0_PCI_IO_HWBASE, 204 1.2.2.2 nathanw IXP12X0_PCI_IO_SIZE, 205 1.2.2.2 nathanw VM_PROT_READ|VM_PROT_WRITE, 206 1.2.2.2 nathanw PTE_NOCACHE, }, 207 1.2.2.2 nathanw 208 1.2.2.2 nathanw { "PCI Registers Accessible Through Memory Cycle Access", 209 1.2.2.3 thorpej IXP12X0_PCI_MEM_VBASE, IXP12X0_PCI_MEM_HWBASE, 210 1.2.2.2 nathanw IXP12X0_PCI_MEM_SIZE, 211 1.2.2.2 nathanw VM_PROT_READ|VM_PROT_WRITE, 212 1.2.2.2 nathanw PTE_NOCACHE, }, 213 1.2.2.2 nathanw 214 1.2.2.2 nathanw { "PCI Type0 Configuration Space", 215 1.2.2.3 thorpej IXP12X0_PCI_TYPE0_VBASE, IXP12X0_PCI_TYPE0_HWBASE, 216 1.2.2.2 nathanw IXP12X0_PCI_TYPEX_SIZE, 217 1.2.2.2 nathanw VM_PROT_READ|VM_PROT_WRITE, 218 1.2.2.2 nathanw PTE_NOCACHE, }, 219 1.2.2.2 nathanw 220 1.2.2.2 nathanw { "PCI Type1 Configuration Space", 221 1.2.2.3 thorpej IXP12X0_PCI_TYPE1_VBASE, IXP12X0_PCI_TYPE1_HWBASE, 222 1.2.2.2 nathanw IXP12X0_PCI_TYPEX_SIZE, 223 1.2.2.2 nathanw VM_PROT_READ|VM_PROT_WRITE, 224 1.2.2.2 nathanw PTE_NOCACHE, }, 225 1.2.2.2 nathanw 226 1.2.2.2 nathanw { NULL, 0, 0, 0, 0, 0 }, 227 1.2.2.2 nathanw }; 228 1.2.2.2 nathanw 229 1.2.2.2 nathanw /* 230 1.2.2.2 nathanw * mapping virtual memories 231 1.2.2.2 nathanw */ 232 1.2.2.2 nathanw void 233 1.2.2.2 nathanw ixp12x0_pmap_chunk_table(vaddr_t l1pt, struct pmap_ent* m) 234 1.2.2.2 nathanw { 235 1.2.2.2 nathanw int loop; 236 1.2.2.2 nathanw 237 1.2.2.2 nathanw loop = 0; 238 1.2.2.2 nathanw while (m[loop].msg) { 239 1.2.2.2 nathanw printf("mapping %s...\n", m[loop].msg); 240 1.2.2.2 nathanw pmap_map_chunk(l1pt, m[loop].va, m[loop].pa, 241 1.2.2.2 nathanw m[loop].sz, m[loop].prot, m[loop].cache); 242 1.2.2.2 nathanw ++loop; 243 1.2.2.2 nathanw } 244 1.2.2.2 nathanw } 245 1.2.2.2 nathanw 246 1.2.2.2 nathanw /* 247 1.2.2.2 nathanw * mapping I/O registers 248 1.2.2.2 nathanw */ 249 1.2.2.2 nathanw void 250 1.2.2.2 nathanw ixp12x0_pmap_io_reg(vaddr_t l1pt) 251 1.2.2.2 nathanw { 252 1.2.2.2 nathanw ixp12x0_pmap_chunk_table(l1pt, map_tbl_ixp12x0); 253 1.2.2.2 nathanw } 254 1.2.2.2 nathanw 255 1.2.2.2 nathanw void 256 1.2.2.2 nathanw ixp12x0_reset(void) 257 1.2.2.2 nathanw { 258 1.2.2.2 nathanw bus_space_write_4(ixp12x0_softc->sc_iot, ixp12x0_softc->sc_pci_ioh, 259 1.2.2.2 nathanw IXPPCI_IXP1200_RESET, RESET_FULL); 260 1.2.2.2 nathanw } 261
Indexes created Wed Oct 29 20:09:47 GMT 2025