ixp12x0.c revision 1.15
1 /* $NetBSD: ixp12x0.c,v 1.15 2009/03/14 15:36:02 dsl Exp $ */ 2 /* 3 * Copyright (c) 2002, 2003 4 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Ichiro FUKUHARA. 18 * 4. The name of the company nor the name of the author may be used to 19 * endorse or promote products derived from this software without specific 20 * prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: ixp12x0.c,v 1.15 2009/03/14 15:36:02 dsl Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <uvm/uvm.h> 42 43 #include <machine/bus.h> 44 45 #include <arm/ixp12x0/ixp12x0reg.h> 46 #include <arm/ixp12x0/ixp12x0var.h> 47 #include <arm/ixp12x0/ixp12x0_pcireg.h> 48 49 static struct ixp12x0_softc *ixp12x0_softc; 50 51 void 52 ixp12x0_attach(struct ixp12x0_softc *sc) 53 { 54 struct pcibus_attach_args pba; 55 pcireg_t reg; 56 57 ixp12x0_softc = sc; 58 59 printf("\n"); 60 61 sc->sc_iot = &ixp12x0_bs_tag; 62 63 /* 64 * Mapping for PCI Configuration Spase Registers 65 */ 66 if (bus_space_map(sc->sc_iot, IXP12X0_PCI_HWBASE, IXP12X0_PCI_SIZE, 67 0, &sc->sc_pci_ioh)) 68 panic("%s: unable to map PCI registers", sc->sc_dev.dv_xname); 69 if (bus_space_map(sc->sc_iot, IXP12X0_PCI_TYPE0_HWBASE, 70 IXP12X0_PCI_TYPE0_SIZE, 0, &sc->sc_conf0_ioh)) 71 panic("%s: unable to map PCI Configutation 0\n", 72 sc->sc_dev.dv_xname); 73 if (bus_space_map(sc->sc_iot, IXP12X0_PCI_TYPE1_HWBASE, 74 IXP12X0_PCI_TYPE0_SIZE, 1, &sc->sc_conf1_ioh)) 75 panic("%s: unable to map PCI Configutation 1\n", 76 sc->sc_dev.dv_xname); 77 78 /* 79 * PCI bus reset 80 */ 81 /* disable PCI command */ 82 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 83 PCI_COMMAND_STATUS_REG, 0xffff0000); 84 /* XXX assert PCI reset Mode */ 85 reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 86 SA_CONTROL) &~ SA_CONTROL_PNR; 87 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 88 SA_CONTROL, reg); 89 DELAY(10); 90 91 /* XXX Disable door bell and outbound interrupt */ 92 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 93 PCI_CAP_PTR, 0xc); 94 /* Disable door bell int to PCI */ 95 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 96 DBELL_PCI_MASK, 0x0); 97 /* Disable door bell int to SA-core */ 98 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 99 DBELL_SA_MASK, 0x0); 100 101 /* We setup a 1:1 memory map of bus<->physical addresses */ 102 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 103 PCI_ADDR_EXT, 104 PCI_ADDR_EXT_PMSA(IXP12X0_PCI_MEM_HWBASE)); 105 106 /* XXX Negate PCI reset */ 107 reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 108 SA_CONTROL) | SA_CONTROL_PNR; 109 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 110 SA_CONTROL, reg); 111 DELAY(10); 112 /* 113 * specify window size of memory access and SDRAM. 114 */ 115 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_MEM_BAR, 116 IXP1200_PCI_MEM_BAR & IXP_PCI_MEM_BAR_MASK); 117 118 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_IO_BAR, 119 IXP1200_PCI_IO_BAR & IXP_PCI_IO_BAR_MASK); 120 121 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_DRAM_BAR, 122 IXP1200_PCI_DRAM_BAR & IXP_PCI_DRAM_BAR_MASK); 123 124 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 125 CSR_BASE_ADDR_MASK, CSR_BASE_ADDR_MASK_1M); 126 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 127 DRAM_BASE_ADDR_MASK, DRAM_BASE_ADDR_MASK_256MB); 128 129 #ifdef PCI_DEBUG 130 printf("IXP_PCI_MEM_BAR = 0x%08x\nIXP_PCI_IO_BAR = 0x%08x\nIXP_PCI_DRAM_BAR = 0x%08x\nPCI_ADDR_EXT = 0x%08x\nCSR_BASE_ADDR_MASK = 0x%08x\nDRAM_BASE_ADDR_MASK = 0x%08x\n", 131 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_MEM_BAR), 132 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_IO_BAR), 133 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_DRAM_BAR), 134 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, PCI_ADDR_EXT), 135 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, CSR_BASE_ADDR_MASK), 136 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, DRAM_BASE_ADDR_MASK)); 137 #endif 138 /* Initialize complete */ 139 reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 140 SA_CONTROL) | 0x1; 141 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 142 SA_CONTROL, reg); 143 #ifdef PCI_DEBUG 144 printf("SA_CONTROL = 0x%08x\n", 145 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, SA_CONTROL)); 146 #endif 147 /* 148 * Enable bus mastering and I/O,memory access 149 */ 150 /* host only */ 151 reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 152 PCI_COMMAND_STATUS_REG) | 153 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 154 PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE | 155 PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE; 156 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 157 PCI_COMMAND_STATUS_REG, reg); 158 #ifdef PCI_DEBUG 159 printf("PCI_COMMAND_STATUS_REG = 0x%08x\n", 160 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, PCI_COMMAND_STATUS_REG)); 161 #endif 162 /* 163 * Initialize the PCI chipset tag. 164 */ 165 ixp12x0_pci_init(&sc->ia_pci_chipset, sc); 166 167 /* 168 * Initialize the DMA tags. 169 */ 170 ixp12x0_pci_dma_init(sc); 171 172 /* 173 * Attach the PCI bus. 174 */ 175 pba.pba_pc = &sc->ia_pci_chipset; 176 pba.pba_iot = &ixp12x0_bs_tag; 177 pba.pba_memt = &ixp12x0_bs_tag; 178 pba.pba_dmat = &sc->ia_pci_dmat; 179 pba.pba_dmat64 = NULL; 180 pba.pba_bus = 0; /* bus number = 0 */ 181 pba.pba_intrswiz = 0; /* XXX */ 182 pba.pba_intrtag = 0; 183 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 184 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 185 (void) config_found_ia(&sc->sc_dev, "pcibus", &pba, pcibusprint); 186 } 187 188 void 189 ixp12x0_reset(void) 190 { 191 bus_space_write_4(ixp12x0_softc->sc_iot, ixp12x0_softc->sc_pci_ioh, 192 IXPPCI_IXP1200_RESET, RESET_FULL); 193 } 194
Indexes created Thu Oct 02 01:09:59 GMT 2025