ixp12x0.c revision 1.5
1 /* $NetBSD: ixp12x0.c,v 1.5 2003/01/01 00:46:15 thorpej Exp $ */ 2 /* 3 * Copyright (c) 2002 4 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Ichiro FUKUHARA. 18 * 4. The name of the company nor the name of the author may be used to 19 * endorse or promote products derived from this software without specific 20 * prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <uvm/uvm.h> 39 40 #include <machine/bus.h> 41 42 #include <arm/ixp12x0/ixp12x0reg.h> 43 #include <arm/ixp12x0/ixp12x0var.h> 44 #include <arm/ixp12x0/ixp12x0_pcireg.h> 45 46 int ixp12x0_pcibus_print(void *, const char *); 47 48 static struct ixp12x0_softc *ixp12x0_softc; 49 50 void 51 ixp12x0_attach(sc) 52 struct ixp12x0_softc *sc; 53 { 54 struct pcibus_attach_args pba; 55 pcireg_t reg; 56 57 ixp12x0_softc = sc; 58 59 printf("\n"); 60 /* 61 * Subregion for PCI Configuration Spase Registers 62 */ 63 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, 64 IXP12X0_PCI_SIZE, &sc->sc_pci_ioh)) 65 panic("%s: unable to subregion PCI registers", 66 sc->sc_dev.dv_xname); 67 /* 68 * PCI bus reset 69 */ 70 /* XXX assert PCI reset Mode */ 71 reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 72 SA_CONTROL) &~ SA_CONTROL_PNR; 73 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 74 SA_CONTROL, reg); 75 DELAY(10); 76 77 /* XXX Disable door bell and outbound interrupt */ 78 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 79 PCI_CAP_PTR, 0xc); 80 /* Disable door bell int to PCI */ 81 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 82 DBELL_PCI_MASK, 0x0); 83 /* Disable door bell int to SA-core */ 84 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 85 DBELL_SA_MASK, 0x0); 86 87 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 88 PCI_ADDR_EXT, 0); 89 90 /* XXX Negate PCI reset */ 91 reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 92 SA_CONTROL) | SA_CONTROL_PNR; 93 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 94 SA_CONTROL, reg); 95 DELAY(10); 96 /* 97 * specify window size of memory access and SDRAM. 98 */ 99 reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 100 IXP_PCI_MEM_BAR) | IXP1200_PCI_MEM_BAR; 101 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 102 IXP_PCI_MEM_BAR, reg); 103 104 reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 105 IXP_PCI_IO_BAR) | IXP1200_PCI_IO_BAR; 106 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 107 IXP_PCI_IO_BAR, reg); 108 109 reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 110 IXP_PCI_DRAM_BAR) | IXP1200_PCI_DRAM_BAR; 111 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 112 IXP_PCI_DRAM_BAR, reg); 113 114 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 115 CSR_BASE_ADDR_MASK, CSR_BASE_ADDR_MASK_1M); 116 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 117 DRAM_BASE_ADDR_MASK, DRAM_BASE_ADDR_MASK_256MB); 118 119 #if DEBUG 120 printf("IXP_PCI_MEM_BAR = 0x%08x\nIXP_PCI_IO_BAR = 0x%08x\nIXP_PCI_DRAM_BAR = 0x%08x\nCSR_BASE_ADDR_MASK = 0x%08x\n", 121 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_MEM_BAR), 122 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_IO_BAR), 123 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_DRAM_BAR), 124 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, DRAM_BASE_ADDR_MASK)); 125 #endif 126 /* Initialize complete */ 127 reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 128 SA_CONTROL) | 0x1; 129 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 130 SA_CONTROL, reg); 131 #if DEBUG 132 printf("SA_CONTROL = 0x%08x\n", 133 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, SA_CONTROL)); 134 #endif 135 /* 136 * Enable bus mastering and I/O,memory access 137 */ 138 /* host only */ 139 reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, 140 PCI_COMMAND_STATUS_REG) | 141 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 142 PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE; 143 bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, 144 PCI_COMMAND_STATUS_REG, reg); 145 #if DEBUG 146 printf("PCI_COMMAND_STATUS_REG = 0x%08x\n", 147 bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, PCI_COMMAND_STATUS_REG)); 148 #endif 149 /* 150 * Initialize the bus space and DMA tags and the PCI chipset tag. 151 */ 152 ixp12x0_io_bs_init(&sc->ia_pci_iot, sc); 153 ixp12x0_mem_bs_init(&sc->ia_pci_memt, sc); 154 ixp12x0_pci_init(&sc->ia_pci_chipset, sc); 155 ixp12x0_pci_dma_init(&sc->ia_pci_dmat, sc); 156 157 /* 158 * Attach the PCI bus. 159 */ 160 pba.pba_busname = "pci"; 161 pba.pba_pc = &sc->ia_pci_chipset; 162 pba.pba_iot = &sc->ia_pci_iot; 163 pba.pba_memt = &sc->ia_pci_memt; 164 pba.pba_dmat = &sc->ia_pci_dmat; 165 pba.pba_bus = 0; /* bus number = 0 */ 166 pba.pba_intrswiz = 0; /* XXX */ 167 pba.pba_intrtag = 0; 168 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED | 169 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 170 (void) config_found(&sc->sc_dev, &pba, ixp12x0_pcibus_print); 171 } 172 173 int 174 ixp12x0_pcibus_print(void *aux, const char *pnp) 175 { 176 struct pcibus_attach_args *pba = aux; 177 178 if (pnp) 179 aprint_normal("%s at %s", pba->pba_busname, pnp); 180 181 aprint_normal(" bus %d", pba->pba_bus); 182 183 return (UNCONF); 184 } 185 186 /* 187 * IXP12x0 specific I/O registers mapping table 188 */ 189 static struct pmap_ent map_tbl_ixp12x0[] = { 190 { "StrongARM System and Peripheral Registers", 191 IXP12X0_SYS_VBASE, IXP12X0_SYS_HWBASE, 192 IXP12X0_SYS_SIZE, 193 VM_PROT_READ|VM_PROT_WRITE, 194 PTE_NOCACHE, }, 195 196 { "PCI Registers Accessible Through StrongARM Core", 197 IXP12X0_PCI_VBASE, IXP12X0_PCI_HWBASE, 198 IXP12X0_PCI_SIZE, 199 VM_PROT_READ|VM_PROT_WRITE, 200 PTE_NOCACHE, }, 201 202 { "PCI Registers Accessible Through I/O Cycle Access", 203 IXP12X0_PCI_IO_VBASE, IXP12X0_PCI_IO_HWBASE, 204 IXP12X0_PCI_IO_SIZE, 205 VM_PROT_READ|VM_PROT_WRITE, 206 PTE_NOCACHE, }, 207 208 { "PCI Registers Accessible Through Memory Cycle Access", 209 IXP12X0_PCI_MEM_VBASE, IXP12X0_PCI_MEM_HWBASE, 210 IXP12X0_PCI_MEM_SIZE, 211 VM_PROT_READ|VM_PROT_WRITE, 212 PTE_NOCACHE, }, 213 214 { "PCI Type0 Configuration Space", 215 IXP12X0_PCI_TYPE0_VBASE, IXP12X0_PCI_TYPE0_HWBASE, 216 IXP12X0_PCI_TYPEX_SIZE, 217 VM_PROT_READ|VM_PROT_WRITE, 218 PTE_NOCACHE, }, 219 220 { "PCI Type1 Configuration Space", 221 IXP12X0_PCI_TYPE1_VBASE, IXP12X0_PCI_TYPE1_HWBASE, 222 IXP12X0_PCI_TYPEX_SIZE, 223 VM_PROT_READ|VM_PROT_WRITE, 224 PTE_NOCACHE, }, 225 226 { NULL, 0, 0, 0, 0, 0 }, 227 }; 228 229 /* 230 * mapping virtual memories 231 */ 232 void 233 ixp12x0_pmap_chunk_table(vaddr_t l1pt, struct pmap_ent* m) 234 { 235 int loop; 236 237 loop = 0; 238 while (m[loop].msg) { 239 printf("mapping %s...\n", m[loop].msg); 240 pmap_map_chunk(l1pt, m[loop].va, m[loop].pa, 241 m[loop].sz, m[loop].prot, m[loop].cache); 242 ++loop; 243 } 244 } 245 246 /* 247 * mapping I/O registers 248 */ 249 void 250 ixp12x0_pmap_io_reg(vaddr_t l1pt) 251 { 252 ixp12x0_pmap_chunk_table(l1pt, map_tbl_ixp12x0); 253 } 254 255 void 256 ixp12x0_reset(void) 257 { 258 bus_space_write_4(ixp12x0_softc->sc_iot, ixp12x0_softc->sc_pci_ioh, 259 IXPPCI_IXP1200_RESET, RESET_FULL); 260 } 261
Indexes created Tue Sep 30 20:09:53 GMT 2025