ixp12x0_clkreg.h revision 1.1.2.2
1 1.1.2.2 gehenna /* $NetBSD: ixp12x0_clkreg.h,v 1.1.2.2 2002/07/21 13:00:29 gehenna Exp $ */ 2 1.1.2.2 gehenna 3 1.1.2.2 gehenna /* 4 1.1.2.2 gehenna * Copyright (c) 2002 5 1.1.2.2 gehenna * Ichiro FUKUHARA <ichiro (at) ichiro.org>. All rights reserved. 6 1.1.2.2 gehenna * 7 1.1.2.2 gehenna * Redistribution and use in source and binary forms, with or without 8 1.1.2.2 gehenna * modification, are permitted provided that the following conditions 9 1.1.2.2 gehenna * are met: 10 1.1.2.2 gehenna * 1. Redistributions of source code must retain the above copyright 11 1.1.2.2 gehenna * notice, this list of conditions and the following disclaimer. 12 1.1.2.2 gehenna * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 gehenna * notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 gehenna * documentation and/or other materials provided with the distribution. 15 1.1.2.2 gehenna * 3. All advertising materials mentioning features or use of this software 16 1.1.2.2 gehenna * must display the following acknowledgement: 17 1.1.2.2 gehenna * This product includes software developed by Ichiro FUKUHARA. 18 1.1.2.2 gehenna * 4. Neither the name of the author nor the names of any co-contributors 19 1.1.2.2 gehenna * may be used to endorse or promote products derived from this software 20 1.1.2.2 gehenna * without specific prior written permission. 21 1.1.2.2 gehenna * 22 1.1.2.2 gehenna * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA AND CONTRIBUTORS ``AS IS'' 23 1.1.2.2 gehenna * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 1.1.2.2 gehenna * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 1.1.2.2 gehenna * ARE DISCLAIMED. IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS 26 1.1.2.2 gehenna * HEAD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 27 1.1.2.2 gehenna * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 1.1.2.2 gehenna * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 1.1.2.2 gehenna * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 1.1.2.2 gehenna * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 1.1.2.2 gehenna * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 1.1.2.2 gehenna * THE POSSIBILITY OF SUCH DAMAGE. 33 1.1.2.2 gehenna */ 34 1.1.2.2 gehenna 35 1.1.2.2 gehenna /* 36 1.1.2.2 gehenna * IXP12X0 TIMER registers 37 1.1.2.2 gehenna * TIMER_1 v0xf0010300 p0x42000300 38 1.1.2.2 gehenna * TIMER_2 v0xf0010320 p0x42000320 39 1.1.2.2 gehenna * TIMER_3 v0xf0010340 p0x42000340 40 1.1.2.2 gehenna * TIMER_4 v0xf0010360 p0x42000360 41 1.1.2.2 gehenna */ 42 1.1.2.2 gehenna 43 1.1.2.2 gehenna #ifndef _IXP12X0_TIMERREG_H_ 44 1.1.2.2 gehenna #define _IXP12X0_TIMERREG_H_ 45 1.1.2.2 gehenna 46 1.1.2.2 gehenna #include <arm/ixp12x0/ixp12x0reg.h> 47 1.1.2.2 gehenna 48 1.1.2.2 gehenna /* size of I/O space */ 49 1.1.2.2 gehenna #define IXPCLK_VBASE (IXP12X0_PCI_VBASE + 0x300) 50 1.1.2.2 gehenna #define IXPCLK_SIZE 0x00000010 51 1.1.2.2 gehenna 52 1.1.2.2 gehenna /* timer load register */ 53 1.1.2.2 gehenna #define IXPCLK_LOAD 0x00000000 54 1.1.2.2 gehenna #define IXPCL_ITV 0x00ffffff 55 1.1.2.2 gehenna 56 1.1.2.2 gehenna /* timer value register */ 57 1.1.2.2 gehenna #define IXPCLK_VALUE 0x00000004 58 1.1.2.2 gehenna #define IXPCL_CTV 0x00ffffff 59 1.1.2.2 gehenna 60 1.1.2.2 gehenna /* timer control register */ 61 1.1.2.2 gehenna #define IXPCLK_CONTROL 0x00000008 62 1.1.2.2 gehenna #define IXPCL_STP 0x0c 63 1.1.2.2 gehenna #define IXPCL_STP_CORE 0x00 64 1.1.2.2 gehenna #define IXPCL_STP_DIV16 0x04 65 1.1.2.2 gehenna #define IXPCL_STP_DIV256 0x08 66 1.1.2.2 gehenna #define IXPCL_MODE 0x40 67 1.1.2.2 gehenna #define IXPCL_FREERUN 0x00 68 1.1.2.2 gehenna #define IXPCL_PERIODIC 0x40 69 1.1.2.2 gehenna #define IXPCL_EN 0x80 70 1.1.2.2 gehenna #define IXPCL_DISABLE 0x00 71 1.1.2.2 gehenna #define IXPCL_ENABLE 0x80 72 1.1.2.2 gehenna 73 1.1.2.2 gehenna /* timer clear register */ 74 1.1.2.2 gehenna #define IXPCLK_CLEAR 0x0000000c 75 1.1.2.2 gehenna #define IXPT_CLEAR 0 76 1.1.2.2 gehenna 77 1.1.2.2 gehenna /* 78 1.1.2.2 gehenna * IXP12X0 real time clock registers 79 1.1.2.2 gehenna * RTC_DIV 0x90002000 80 1.1.2.2 gehenna * RTC_TINT 0x90002400 81 1.1.2.2 gehenna * RTC_TVAL 0x90002800 82 1.1.2.2 gehenna * RTC_CNTR 0x90002c00 83 1.1.2.2 gehenna * RTC_ALM 0x90003000 84 1.1.2.2 gehenna */ 85 1.1.2.2 gehenna 86 1.1.2.2 gehenna /* RTC_DIV register */ 87 1.1.2.2 gehenna #define RTC_DIV 0x90002000 88 1.1.2.2 gehenna #define RTC_RDIV 0x0000ffff 89 1.1.2.2 gehenna #define RTC_WEN 0x00010000 90 1.1.2.2 gehenna #define RTC_WDIVISER 0x00000000 91 1.1.2.2 gehenna #define RTC_WINTONLY 0x00010000 92 1.1.2.2 gehenna #define RTC_IEN 0x00020000 93 1.1.2.2 gehenna #define RTC_IEN_E 0x00020000 94 1.1.2.2 gehenna #define RTC_IEN_D 0x00000000 95 1.1.2.2 gehenna #define RTC_IRST 0x00040000 96 1.1.2.2 gehenna #define RTC_IRST_NOCLR 0x00040000 97 1.1.2.2 gehenna #define RTC_IRST_CLR 0x00000000 98 1.1.2.2 gehenna #define RTC_IRQS 0x00080000 99 1.1.2.2 gehenna #define RTC_IRQS_IRQ 0x00080000 100 1.1.2.2 gehenna #define RTC_IRQS_FIQ 0x00000000 101 1.1.2.2 gehenna 102 1.1.2.2 gehenna 103 1.1.2.2 gehenna /* RTC_TINT register */ 104 1.1.2.2 gehenna #define RTC_TINT 0x90002400 105 1.1.2.2 gehenna #define RTC_RTINT 0x0000ffff 106 1.1.2.2 gehenna 107 1.1.2.2 gehenna /* RTC_TVAL register */ 108 1.1.2.2 gehenna #define RTC_TVAL 0x90002800 109 1.1.2.2 gehenna #define RTC_TVAL_TVAL 0x0000ffff 110 1.1.2.2 gehenna #define RTC_LD 0x00010000 111 1.1.2.2 gehenna #define RTC_LD_LOAD 0x00010000 112 1.1.2.2 gehenna #define RTC_LD_NOLOAD 0x00000000 113 1.1.2.2 gehenna #define RTC_PRE 0x00020000 114 1.1.2.2 gehenna #define RTC_PRE_SYSCLK 0x00020000 115 1.1.2.2 gehenna #define RTC_PRE_DIV128 0x00000000 116 1.1.2.2 gehenna 117 1.1.2.2 gehenna /* RTC_CNTR register */ 118 1.1.2.2 gehenna #define RTC_CNTR 0x90002c00 119 1.1.2.2 gehenna #define RTC_RCN_COUNT 0xffffffff 120 1.1.2.2 gehenna 121 1.1.2.2 gehenna /* RTC_ALM register */ 122 1.1.2.2 gehenna #define RTC_ALM 0x90003000 123 1.1.2.2 gehenna #define RTC_RTC_ALARM 0xffffffff 124 1.1.2.2 gehenna 125 1.1.2.2 gehenna #endif /* _IXP12X0_TIMERREG_H_ */ 126
Indexes created Sat Oct 25 07:10:08 GMT 2025