ixp12x0_clkreg.h revision 1.1.2.2
1 /* $NetBSD: ixp12x0_clkreg.h,v 1.1.2.2 2002/07/21 13:00:29 gehenna Exp $ */ 2 3 /* 4 * Copyright (c) 2002 5 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Ichiro FUKUHARA. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA AND CONTRIBUTORS ``AS IS'' 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS 26 * HEAD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 27 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * IXP12X0 TIMER registers 37 * TIMER_1 v0xf0010300 p0x42000300 38 * TIMER_2 v0xf0010320 p0x42000320 39 * TIMER_3 v0xf0010340 p0x42000340 40 * TIMER_4 v0xf0010360 p0x42000360 41 */ 42 43 #ifndef _IXP12X0_TIMERREG_H_ 44 #define _IXP12X0_TIMERREG_H_ 45 46 #include <arm/ixp12x0/ixp12x0reg.h> 47 48 /* size of I/O space */ 49 #define IXPCLK_VBASE (IXP12X0_PCI_VBASE + 0x300) 50 #define IXPCLK_SIZE 0x00000010 51 52 /* timer load register */ 53 #define IXPCLK_LOAD 0x00000000 54 #define IXPCL_ITV 0x00ffffff 55 56 /* timer value register */ 57 #define IXPCLK_VALUE 0x00000004 58 #define IXPCL_CTV 0x00ffffff 59 60 /* timer control register */ 61 #define IXPCLK_CONTROL 0x00000008 62 #define IXPCL_STP 0x0c 63 #define IXPCL_STP_CORE 0x00 64 #define IXPCL_STP_DIV16 0x04 65 #define IXPCL_STP_DIV256 0x08 66 #define IXPCL_MODE 0x40 67 #define IXPCL_FREERUN 0x00 68 #define IXPCL_PERIODIC 0x40 69 #define IXPCL_EN 0x80 70 #define IXPCL_DISABLE 0x00 71 #define IXPCL_ENABLE 0x80 72 73 /* timer clear register */ 74 #define IXPCLK_CLEAR 0x0000000c 75 #define IXPT_CLEAR 0 76 77 /* 78 * IXP12X0 real time clock registers 79 * RTC_DIV 0x90002000 80 * RTC_TINT 0x90002400 81 * RTC_TVAL 0x90002800 82 * RTC_CNTR 0x90002c00 83 * RTC_ALM 0x90003000 84 */ 85 86 /* RTC_DIV register */ 87 #define RTC_DIV 0x90002000 88 #define RTC_RDIV 0x0000ffff 89 #define RTC_WEN 0x00010000 90 #define RTC_WDIVISER 0x00000000 91 #define RTC_WINTONLY 0x00010000 92 #define RTC_IEN 0x00020000 93 #define RTC_IEN_E 0x00020000 94 #define RTC_IEN_D 0x00000000 95 #define RTC_IRST 0x00040000 96 #define RTC_IRST_NOCLR 0x00040000 97 #define RTC_IRST_CLR 0x00000000 98 #define RTC_IRQS 0x00080000 99 #define RTC_IRQS_IRQ 0x00080000 100 #define RTC_IRQS_FIQ 0x00000000 101 102 103 /* RTC_TINT register */ 104 #define RTC_TINT 0x90002400 105 #define RTC_RTINT 0x0000ffff 106 107 /* RTC_TVAL register */ 108 #define RTC_TVAL 0x90002800 109 #define RTC_TVAL_TVAL 0x0000ffff 110 #define RTC_LD 0x00010000 111 #define RTC_LD_LOAD 0x00010000 112 #define RTC_LD_NOLOAD 0x00000000 113 #define RTC_PRE 0x00020000 114 #define RTC_PRE_SYSCLK 0x00020000 115 #define RTC_PRE_DIV128 0x00000000 116 117 /* RTC_CNTR register */ 118 #define RTC_CNTR 0x90002c00 119 #define RTC_RCN_COUNT 0xffffffff 120 121 /* RTC_ALM register */ 122 #define RTC_ALM 0x90003000 123 #define RTC_RTC_ALARM 0xffffffff 124 125 #endif /* _IXP12X0_TIMERREG_H_ */ 126
Indexes created Thu Oct 23 22:10:10 GMT 2025