ixp12x0_intr.c revision 1.2.2.2
1 1.2.2.2 nathanw /* $NetBSD: ixp12x0_intr.c,v 1.2.2.2 2002/10/18 02:35:37 nathanw Exp $ */ 2 1.2.2.2 nathanw 3 1.2.2.2 nathanw /* 4 1.2.2.2 nathanw * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 1.2.2.2 nathanw * All rights reserved. 6 1.2.2.2 nathanw * 7 1.2.2.2 nathanw * This code is derived from software contributed to The NetBSD Foundation 8 1.2.2.2 nathanw * by Ichiro FUKUHARA and Naoto Shimazaki. 9 1.2.2.2 nathanw * 10 1.2.2.2 nathanw * Redistribution and use in source and binary forms, with or without 11 1.2.2.2 nathanw * modification, are permitted provided that the following conditions 12 1.2.2.2 nathanw * are met: 13 1.2.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 14 1.2.2.2 nathanw * notice, this list of conditions and the following disclaimer. 15 1.2.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 16 1.2.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 17 1.2.2.2 nathanw * documentation and/or other materials provided with the distribution. 18 1.2.2.2 nathanw * 3. All advertising materials mentioning features or use of this software 19 1.2.2.2 nathanw * must display the following acknowledgement: 20 1.2.2.2 nathanw * This product includes software developed by the NetBSD 21 1.2.2.2 nathanw * Foundation, Inc. and its contributors. 22 1.2.2.2 nathanw * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.2.2.2 nathanw * contributors may be used to endorse or promote products derived 24 1.2.2.2 nathanw * from this software without specific prior written permission. 25 1.2.2.2 nathanw * 26 1.2.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.2.2.2 nathanw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.2.2.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.2.2.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.2.2.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.2.2.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.2.2.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.2.2.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.2.2.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.2.2.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.2.2.2 nathanw * POSSIBILITY OF SUCH DAMAGE. 37 1.2.2.2 nathanw */ 38 1.2.2.2 nathanw 39 1.2.2.2 nathanw /* 40 1.2.2.2 nathanw * Interrupt support for the Intel ixp12x0 41 1.2.2.2 nathanw */ 42 1.2.2.2 nathanw 43 1.2.2.2 nathanw #include <sys/param.h> 44 1.2.2.2 nathanw #include <sys/systm.h> 45 1.2.2.2 nathanw #include <sys/malloc.h> 46 1.2.2.2 nathanw 47 1.2.2.2 nathanw #include <uvm/uvm_extern.h> 48 1.2.2.2 nathanw 49 1.2.2.2 nathanw #include <machine/bus.h> 50 1.2.2.2 nathanw #include <machine/intr.h> 51 1.2.2.2 nathanw 52 1.2.2.2 nathanw #include <arm/cpufunc.h> 53 1.2.2.2 nathanw 54 1.2.2.2 nathanw #include <arm/ixp12x0/ixp12x0reg.h> 55 1.2.2.2 nathanw #include <arm/ixp12x0/ixp12x0var.h> 56 1.2.2.2 nathanw 57 1.2.2.2 nathanw #include <arm/ixp12x0/ixp12x0_comreg.h> 58 1.2.2.2 nathanw #include <arm/ixp12x0/ixp12x0_pcireg.h> 59 1.2.2.2 nathanw 60 1.2.2.2 nathanw extern u_int32_t ixpcom_cr; /* current cr from *_com.c */ 61 1.2.2.2 nathanw extern u_int32_t ixpcom_imask; /* tell mask to *_com.c */ 62 1.2.2.2 nathanw 63 1.2.2.2 nathanw /* Interrupt handler queues. */ 64 1.2.2.2 nathanw struct intrq intrq[NIRQ]; 65 1.2.2.2 nathanw 66 1.2.2.2 nathanw /* Interrupts to mask at each level. */ 67 1.2.2.2 nathanw static u_int32_t imask[NIPL]; 68 1.2.2.2 nathanw static u_int32_t pci_imask[NIPL]; 69 1.2.2.2 nathanw 70 1.2.2.2 nathanw /* Current interrupt priority level. */ 71 1.2.2.2 nathanw __volatile int current_spl_level; 72 1.2.2.2 nathanw 73 1.2.2.2 nathanw /* Software copy of the IRQs we have enabled. */ 74 1.2.2.2 nathanw __volatile u_int32_t intr_enabled; 75 1.2.2.2 nathanw __volatile u_int32_t pci_intr_enabled; 76 1.2.2.2 nathanw 77 1.2.2.2 nathanw /* Interrupts pending. */ 78 1.2.2.2 nathanw static __volatile int ipending; 79 1.2.2.2 nathanw 80 1.2.2.2 nathanw /* 81 1.2.2.2 nathanw * Map a software interrupt queue index (to the unused bits in the 82 1.2.2.2 nathanw * ICU registers -- XXX will need to revisit this if those bits are 83 1.2.2.2 nathanw * ever used in future steppings). 84 1.2.2.2 nathanw */ 85 1.2.2.2 nathanw static const uint32_t si_to_irqbit[SI_NQUEUES] = { 86 1.2.2.2 nathanw IXP12X0_INTR_bit30, /* SI_SOFT */ 87 1.2.2.2 nathanw IXP12X0_INTR_bit29, /* SI_SOFTCLOCK */ 88 1.2.2.2 nathanw IXP12X0_INTR_bit28, /* SI_SOFTNET */ 89 1.2.2.2 nathanw IXP12X0_INTR_bit27, /* SI_SOFTSERIAL */ 90 1.2.2.2 nathanw }; 91 1.2.2.2 nathanw 92 1.2.2.2 nathanw #define INT_SWMASK \ 93 1.2.2.2 nathanw ((1U << IXP12X0_INTR_bit30) | (1U << IXP12X0_INTR_bit29) | \ 94 1.2.2.2 nathanw (1U << IXP12X0_INTR_bit28) | (1U << IXP12X0_INTR_bit27)) 95 1.2.2.2 nathanw 96 1.2.2.2 nathanw #define SI_TO_IRQBIT(si) (1U << si_to_irqbit[(si)]) 97 1.2.2.2 nathanw 98 1.2.2.2 nathanw /* 99 1.2.2.2 nathanw * Map a software interrupt queue to an interrupt priority level. 100 1.2.2.2 nathanw */ 101 1.2.2.2 nathanw static const int si_to_ipl[SI_NQUEUES] = { 102 1.2.2.2 nathanw IPL_SOFT, /* SI_SOFT */ 103 1.2.2.2 nathanw IPL_SOFTCLOCK, /* SI_SOFTCLOCK */ 104 1.2.2.2 nathanw IPL_SOFTNET, /* SI_SOFTNET */ 105 1.2.2.2 nathanw IPL_SOFTSERIAL, /* SI_SOFTSERIAL */ 106 1.2.2.2 nathanw }; 107 1.2.2.2 nathanw 108 1.2.2.2 nathanw void ixp12x0_intr_dispatch(struct irqframe *frame); 109 1.2.2.2 nathanw 110 1.2.2.2 nathanw static __inline u_int32_t 111 1.2.2.2 nathanw ixp12x0_irq_read(void) 112 1.2.2.2 nathanw { 113 1.2.2.2 nathanw return IXPREG(IXP12X0_IRQ_VBASE) & IXP12X0_INTR_MASK; 114 1.2.2.2 nathanw } 115 1.2.2.2 nathanw 116 1.2.2.2 nathanw static __inline u_int32_t 117 1.2.2.2 nathanw ixp12x0_pci_irq_read(void) 118 1.2.2.2 nathanw { 119 1.2.2.2 nathanw return IXPREG(IXPPCI_IRQ_STATUS); 120 1.2.2.2 nathanw } 121 1.2.2.2 nathanw 122 1.2.2.2 nathanw static void 123 1.2.2.2 nathanw ixp12x0_enable_uart_irq(void) 124 1.2.2.2 nathanw { 125 1.2.2.2 nathanw ixpcom_imask = 0; 126 1.2.2.2 nathanw IXPREG(IXPCOM_UART_BASE + IXPCOM_CR) = ixpcom_cr & ~ixpcom_imask; 127 1.2.2.2 nathanw } 128 1.2.2.2 nathanw 129 1.2.2.2 nathanw static void 130 1.2.2.2 nathanw ixp12x0_disable_uart_irq(void) 131 1.2.2.2 nathanw { 132 1.2.2.2 nathanw ixpcom_imask = CR_RIE | CR_XIE; 133 1.2.2.2 nathanw IXPREG(IXPCOM_UART_BASE + IXPCOM_CR) = ixpcom_cr & ~ixpcom_imask; 134 1.2.2.2 nathanw } 135 1.2.2.2 nathanw 136 1.2.2.2 nathanw static void 137 1.2.2.2 nathanw ixp12x0_set_intrmask(u_int32_t irqs, u_int32_t pci_irqs) 138 1.2.2.2 nathanw { 139 1.2.2.2 nathanw if (irqs & (1U << IXP12X0_INTR_UART)) { 140 1.2.2.2 nathanw ixp12x0_disable_uart_irq(); 141 1.2.2.2 nathanw } else { 142 1.2.2.2 nathanw ixp12x0_enable_uart_irq(); 143 1.2.2.2 nathanw } 144 1.2.2.2 nathanw IXPREG(IXPPCI_IRQ_ENABLE_CLEAR) = pci_irqs; 145 1.2.2.2 nathanw IXPREG(IXPPCI_IRQ_ENABLE_SET) = pci_intr_enabled & ~pci_irqs; 146 1.2.2.2 nathanw } 147 1.2.2.2 nathanw 148 1.2.2.2 nathanw static void 149 1.2.2.2 nathanw ixp12x0_enable_irq(int irq) 150 1.2.2.2 nathanw { 151 1.2.2.2 nathanw if (irq < SYS_NIRQ) { 152 1.2.2.2 nathanw intr_enabled |= (1U << irq); 153 1.2.2.2 nathanw switch (irq) { 154 1.2.2.2 nathanw case IXP12X0_INTR_UART: 155 1.2.2.2 nathanw ixp12x0_enable_uart_irq(); 156 1.2.2.2 nathanw break; 157 1.2.2.2 nathanw 158 1.2.2.2 nathanw case IXP12X0_INTR_PCI: 159 1.2.2.2 nathanw /* nothing to do */ 160 1.2.2.2 nathanw break; 161 1.2.2.2 nathanw default: 162 1.2.2.2 nathanw panic("enable_irq:bad IRQ %d", irq); 163 1.2.2.2 nathanw } 164 1.2.2.2 nathanw } else { 165 1.2.2.2 nathanw pci_intr_enabled |= (1U << (irq - SYS_NIRQ)); 166 1.2.2.2 nathanw IXPREG(IXPPCI_IRQ_ENABLE_SET) = (1U << (irq - SYS_NIRQ)); 167 1.2.2.2 nathanw } 168 1.2.2.2 nathanw } 169 1.2.2.2 nathanw 170 1.2.2.2 nathanw static __inline void 171 1.2.2.2 nathanw ixp12x0_disable_irq(int irq) 172 1.2.2.2 nathanw { 173 1.2.2.2 nathanw if (irq < SYS_NIRQ) { 174 1.2.2.2 nathanw intr_enabled ^= ~(1U << irq); 175 1.2.2.2 nathanw switch (irq) { 176 1.2.2.2 nathanw case IXP12X0_INTR_UART: 177 1.2.2.2 nathanw ixp12x0_disable_uart_irq(); 178 1.2.2.2 nathanw break; 179 1.2.2.2 nathanw 180 1.2.2.2 nathanw case IXP12X0_INTR_PCI: 181 1.2.2.2 nathanw /* nothing to do */ 182 1.2.2.2 nathanw break; 183 1.2.2.2 nathanw default: 184 1.2.2.2 nathanw /* nothing to do */ 185 1.2.2.2 nathanw } 186 1.2.2.2 nathanw } else { 187 1.2.2.2 nathanw pci_intr_enabled &= ~(1U << (irq - SYS_NIRQ)); 188 1.2.2.2 nathanw IXPREG(IXPPCI_IRQ_ENABLE_CLEAR) = (1U << (irq - SYS_NIRQ)); 189 1.2.2.2 nathanw } 190 1.2.2.2 nathanw } 191 1.2.2.2 nathanw 192 1.2.2.2 nathanw /* 193 1.2.2.2 nathanw * NOTE: This routine must be called with interrupts disabled in the CPSR. 194 1.2.2.2 nathanw */ 195 1.2.2.2 nathanw static void 196 1.2.2.2 nathanw ixp12x0_intr_calculate_masks(void) 197 1.2.2.2 nathanw { 198 1.2.2.2 nathanw struct intrq *iq; 199 1.2.2.2 nathanw struct intrhand *ih; 200 1.2.2.2 nathanw int irq, ipl; 201 1.2.2.2 nathanw 202 1.2.2.2 nathanw /* First, figure out which IPLs each IRQ has. */ 203 1.2.2.2 nathanw for (irq = 0; irq < NIRQ; irq++) { 204 1.2.2.2 nathanw int levels = 0; 205 1.2.2.2 nathanw iq = &intrq[irq]; 206 1.2.2.2 nathanw ixp12x0_disable_irq(irq); 207 1.2.2.2 nathanw for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 208 1.2.2.2 nathanw ih = TAILQ_NEXT(ih, ih_list)) 209 1.2.2.2 nathanw levels |= (1U << ih->ih_ipl); 210 1.2.2.2 nathanw iq->iq_levels = levels; 211 1.2.2.2 nathanw } 212 1.2.2.2 nathanw 213 1.2.2.2 nathanw /* Next, figure out which IRQs are used by each IPL. */ 214 1.2.2.2 nathanw for (ipl = 0; ipl < NIPL; ipl++) { 215 1.2.2.2 nathanw int irqs = 0; 216 1.2.2.2 nathanw int pci_irqs = 0; 217 1.2.2.2 nathanw for (irq = 0; irq < SYS_NIRQ; irq++) { 218 1.2.2.2 nathanw if (intrq[irq].iq_levels & (1U << ipl)) 219 1.2.2.2 nathanw irqs |= (1U << irq); 220 1.2.2.2 nathanw } 221 1.2.2.2 nathanw imask[ipl] = irqs; 222 1.2.2.2 nathanw for (irq = 0; irq < SYS_NIRQ; irq++) { 223 1.2.2.2 nathanw if (intrq[irq + SYS_NIRQ].iq_levels & (1U << ipl)) 224 1.2.2.2 nathanw pci_irqs |= (1U << irq); 225 1.2.2.2 nathanw } 226 1.2.2.2 nathanw pci_imask[ipl] = pci_irqs; 227 1.2.2.2 nathanw } 228 1.2.2.2 nathanw 229 1.2.2.2 nathanw imask[IPL_NONE] = 0; 230 1.2.2.2 nathanw pci_imask[IPL_NONE] = 0; 231 1.2.2.2 nathanw 232 1.2.2.2 nathanw /* 233 1.2.2.2 nathanw * Initialize the soft interrupt masks to block themselves. 234 1.2.2.2 nathanw */ 235 1.2.2.2 nathanw imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFT); 236 1.2.2.2 nathanw imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK); 237 1.2.2.2 nathanw imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET); 238 1.2.2.2 nathanw imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL); 239 1.2.2.2 nathanw 240 1.2.2.2 nathanw /* 241 1.2.2.2 nathanw * splsoftclock() is the only interface that users of the 242 1.2.2.2 nathanw * generic software interrupt facility have to block their 243 1.2.2.2 nathanw * soft intrs, so splsoftclock() must also block IPL_SOFT. 244 1.2.2.2 nathanw */ 245 1.2.2.2 nathanw imask[IPL_SOFTCLOCK] |= imask[IPL_SOFT]; 246 1.2.2.2 nathanw pci_imask[IPL_SOFTCLOCK] |= pci_imask[IPL_SOFT]; 247 1.2.2.2 nathanw 248 1.2.2.2 nathanw /* 249 1.2.2.2 nathanw * splsoftnet() must also block splsoftclock(), since we don't 250 1.2.2.2 nathanw * want timer-driven network events to occur while we're 251 1.2.2.2 nathanw * processing incoming packets. 252 1.2.2.2 nathanw */ 253 1.2.2.2 nathanw imask[IPL_SOFTNET] |= imask[IPL_SOFTCLOCK]; 254 1.2.2.2 nathanw pci_imask[IPL_SOFTNET] |= pci_imask[IPL_SOFTCLOCK]; 255 1.2.2.2 nathanw 256 1.2.2.2 nathanw /* 257 1.2.2.2 nathanw * Enforce a heirarchy that gives "slow" device (or devices with 258 1.2.2.2 nathanw * limited input buffer space/"real-time" requirements) a better 259 1.2.2.2 nathanw * chance at not dropping data. 260 1.2.2.2 nathanw */ 261 1.2.2.2 nathanw imask[IPL_BIO] |= imask[IPL_SOFTNET]; 262 1.2.2.2 nathanw pci_imask[IPL_BIO] |= pci_imask[IPL_SOFTNET]; 263 1.2.2.2 nathanw imask[IPL_NET] |= imask[IPL_BIO]; 264 1.2.2.2 nathanw pci_imask[IPL_NET] |= pci_imask[IPL_BIO]; 265 1.2.2.2 nathanw imask[IPL_SOFTSERIAL] |= pci_imask[IPL_NET]; 266 1.2.2.2 nathanw pci_imask[IPL_SOFTSERIAL] |= pci_imask[IPL_NET]; 267 1.2.2.2 nathanw imask[IPL_TTY] |= imask[IPL_SOFTSERIAL]; 268 1.2.2.2 nathanw pci_imask[IPL_TTY] |= pci_imask[IPL_SOFTSERIAL]; 269 1.2.2.2 nathanw 270 1.2.2.2 nathanw /* 271 1.2.2.2 nathanw * splvm() blocks all interrupts that use the kernel memory 272 1.2.2.2 nathanw * allocation facilities. 273 1.2.2.2 nathanw */ 274 1.2.2.2 nathanw imask[IPL_IMP] |= imask[IPL_TTY]; 275 1.2.2.2 nathanw pci_imask[IPL_IMP] |= pci_imask[IPL_TTY]; 276 1.2.2.2 nathanw 277 1.2.2.2 nathanw /* 278 1.2.2.2 nathanw * Audio devices are not allowed to perform memory allocation 279 1.2.2.2 nathanw * in their interrupt routines, and they have fairly "real-time" 280 1.2.2.2 nathanw * requirements, so give them a high interrupt priority. 281 1.2.2.2 nathanw */ 282 1.2.2.2 nathanw imask[IPL_AUDIO] |= imask[IPL_IMP]; 283 1.2.2.2 nathanw pci_imask[IPL_AUDIO] |= pci_imask[IPL_IMP]; 284 1.2.2.2 nathanw 285 1.2.2.2 nathanw /* 286 1.2.2.2 nathanw * splclock() must block anything that uses the scheduler. 287 1.2.2.2 nathanw */ 288 1.2.2.2 nathanw imask[IPL_CLOCK] |= imask[IPL_AUDIO]; 289 1.2.2.2 nathanw pci_imask[IPL_CLOCK] |= pci_imask[IPL_AUDIO]; 290 1.2.2.2 nathanw 291 1.2.2.2 nathanw /* 292 1.2.2.2 nathanw * No separate statclock on the IQ80310. 293 1.2.2.2 nathanw */ 294 1.2.2.2 nathanw imask[IPL_STATCLOCK] |= imask[IPL_CLOCK]; 295 1.2.2.2 nathanw pci_imask[IPL_STATCLOCK] |= pci_imask[IPL_CLOCK]; 296 1.2.2.2 nathanw 297 1.2.2.2 nathanw /* 298 1.2.2.2 nathanw * splhigh() must block "everything". 299 1.2.2.2 nathanw */ 300 1.2.2.2 nathanw imask[IPL_HIGH] |= imask[IPL_STATCLOCK]; 301 1.2.2.2 nathanw pci_imask[IPL_HIGH] |= pci_imask[IPL_STATCLOCK]; 302 1.2.2.2 nathanw 303 1.2.2.2 nathanw /* 304 1.2.2.2 nathanw * XXX We need serial drivers to run at the absolute highest priority 305 1.2.2.2 nathanw * in order to avoid overruns, so serial > high. 306 1.2.2.2 nathanw */ 307 1.2.2.2 nathanw imask[IPL_SERIAL] |= imask[IPL_HIGH]; 308 1.2.2.2 nathanw pci_imask[IPL_SERIAL] |= pci_imask[IPL_HIGH]; 309 1.2.2.2 nathanw 310 1.2.2.2 nathanw /* 311 1.2.2.2 nathanw * Now compute which IRQs must be blocked when servicing any 312 1.2.2.2 nathanw * given IRQ. 313 1.2.2.2 nathanw */ 314 1.2.2.2 nathanw for (irq = 0; irq < NIRQ; irq++) { 315 1.2.2.2 nathanw int irqs; 316 1.2.2.2 nathanw int pci_irqs; 317 1.2.2.2 nathanw 318 1.2.2.2 nathanw if (irq < SYS_NIRQ) { 319 1.2.2.2 nathanw irqs = (1U << irq); 320 1.2.2.2 nathanw pci_irqs = 0; 321 1.2.2.2 nathanw } else { 322 1.2.2.2 nathanw irqs = 0; 323 1.2.2.2 nathanw pci_irqs = (1U << (irq - SYS_NIRQ)); 324 1.2.2.2 nathanw } 325 1.2.2.2 nathanw iq = &intrq[irq]; 326 1.2.2.2 nathanw if (TAILQ_FIRST(&iq->iq_list) != NULL) 327 1.2.2.2 nathanw ixp12x0_enable_irq(irq); 328 1.2.2.2 nathanw for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 329 1.2.2.2 nathanw ih = TAILQ_NEXT(ih, ih_list)) { 330 1.2.2.2 nathanw irqs |= imask[ih->ih_ipl]; 331 1.2.2.2 nathanw pci_irqs |= pci_imask[ih->ih_ipl]; 332 1.2.2.2 nathanw } 333 1.2.2.2 nathanw iq->iq_mask = irqs; 334 1.2.2.2 nathanw iq->iq_pci_mask = pci_irqs; 335 1.2.2.2 nathanw } 336 1.2.2.2 nathanw } 337 1.2.2.2 nathanw 338 1.2.2.2 nathanw static void 339 1.2.2.2 nathanw ixp12x0_do_pending(void) 340 1.2.2.2 nathanw { 341 1.2.2.2 nathanw static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED; 342 1.2.2.2 nathanw int new; 343 1.2.2.2 nathanw u_int oldirqstate; 344 1.2.2.2 nathanw 345 1.2.2.2 nathanw if (__cpu_simple_lock_try(&processing) == 0) 346 1.2.2.2 nathanw return; 347 1.2.2.2 nathanw 348 1.2.2.2 nathanw new = current_spl_level; 349 1.2.2.2 nathanw 350 1.2.2.2 nathanw oldirqstate = disable_interrupts(I32_bit); 351 1.2.2.2 nathanw 352 1.2.2.2 nathanw #define DO_SOFTINT(si) \ 353 1.2.2.2 nathanw if ((ipending & ~imask[new]) & SI_TO_IRQBIT(si)) { \ 354 1.2.2.2 nathanw ipending &= ~SI_TO_IRQBIT(si); \ 355 1.2.2.2 nathanw current_spl_level = si_to_ipl[(si)]; \ 356 1.2.2.2 nathanw restore_interrupts(oldirqstate); \ 357 1.2.2.2 nathanw softintr_dispatch(si); \ 358 1.2.2.2 nathanw oldirqstate = disable_interrupts(I32_bit); \ 359 1.2.2.2 nathanw current_spl_level = new; \ 360 1.2.2.2 nathanw } 361 1.2.2.2 nathanw 362 1.2.2.2 nathanw DO_SOFTINT(SI_SOFTSERIAL); 363 1.2.2.2 nathanw DO_SOFTINT(SI_SOFTNET); 364 1.2.2.2 nathanw DO_SOFTINT(SI_SOFTCLOCK); 365 1.2.2.2 nathanw DO_SOFTINT(SI_SOFT); 366 1.2.2.2 nathanw 367 1.2.2.2 nathanw __cpu_simple_unlock(&processing); 368 1.2.2.2 nathanw 369 1.2.2.2 nathanw restore_interrupts(oldirqstate); 370 1.2.2.2 nathanw } 371 1.2.2.2 nathanw 372 1.2.2.2 nathanw __inline void 373 1.2.2.2 nathanw splx(int new) 374 1.2.2.2 nathanw { 375 1.2.2.2 nathanw int old; 376 1.2.2.2 nathanw u_int oldirqstate; 377 1.2.2.2 nathanw 378 1.2.2.2 nathanw if (current_spl_level == new) 379 1.2.2.2 nathanw return; 380 1.2.2.2 nathanw oldirqstate = disable_interrupts(I32_bit); 381 1.2.2.2 nathanw old = current_spl_level; 382 1.2.2.2 nathanw current_spl_level = new; 383 1.2.2.2 nathanw ixp12x0_set_intrmask(imask[new], pci_imask[new]); 384 1.2.2.2 nathanw restore_interrupts(oldirqstate); 385 1.2.2.2 nathanw 386 1.2.2.2 nathanw /* If there are software interrupts to process, do it. */ 387 1.2.2.2 nathanw if ((ipending & INT_SWMASK) & ~imask[new]) 388 1.2.2.2 nathanw ixp12x0_do_pending(); 389 1.2.2.2 nathanw } 390 1.2.2.2 nathanw 391 1.2.2.2 nathanw int 392 1.2.2.2 nathanw _splraise(int ipl) 393 1.2.2.2 nathanw { 394 1.2.2.2 nathanw int old = current_spl_level; 395 1.2.2.2 nathanw 396 1.2.2.2 nathanw if (old >= ipl) 397 1.2.2.2 nathanw return (old); 398 1.2.2.2 nathanw splx(ipl); 399 1.2.2.2 nathanw return (old); 400 1.2.2.2 nathanw } 401 1.2.2.2 nathanw 402 1.2.2.2 nathanw int 403 1.2.2.2 nathanw _spllower(int ipl) 404 1.2.2.2 nathanw { 405 1.2.2.2 nathanw int old = current_spl_level; 406 1.2.2.2 nathanw 407 1.2.2.2 nathanw if (old <= ipl) 408 1.2.2.2 nathanw return (old); 409 1.2.2.2 nathanw splx(ipl); 410 1.2.2.2 nathanw return (old); 411 1.2.2.2 nathanw } 412 1.2.2.2 nathanw 413 1.2.2.2 nathanw void 414 1.2.2.2 nathanw _setsoftintr(int si) 415 1.2.2.2 nathanw { 416 1.2.2.2 nathanw u_int oldirqstate; 417 1.2.2.2 nathanw 418 1.2.2.2 nathanw oldirqstate = disable_interrupts(I32_bit); 419 1.2.2.2 nathanw ipending |= SI_TO_IRQBIT(si); 420 1.2.2.2 nathanw restore_interrupts(oldirqstate); 421 1.2.2.2 nathanw 422 1.2.2.2 nathanw /* Process unmasked pending soft interrupts. */ 423 1.2.2.2 nathanw if ((ipending & INT_SWMASK) & ~imask[current_spl_level]) 424 1.2.2.2 nathanw ixp12x0_do_pending(); 425 1.2.2.2 nathanw } 426 1.2.2.2 nathanw 427 1.2.2.2 nathanw /* 428 1.2.2.2 nathanw * ixp12x0_intr_init: 429 1.2.2.2 nathanw * 430 1.2.2.2 nathanw * Initialize the rest of the interrupt subsystem, making it 431 1.2.2.2 nathanw * ready to handle interrupts from devices. 432 1.2.2.2 nathanw */ 433 1.2.2.2 nathanw void 434 1.2.2.2 nathanw ixp12x0_intr_init(void) 435 1.2.2.2 nathanw { 436 1.2.2.2 nathanw struct intrq *iq; 437 1.2.2.2 nathanw int i; 438 1.2.2.2 nathanw 439 1.2.2.2 nathanw intr_enabled = 0; 440 1.2.2.2 nathanw pci_intr_enabled = 0; 441 1.2.2.2 nathanw 442 1.2.2.2 nathanw for (i = 0; i < NIRQ; i++) { 443 1.2.2.2 nathanw iq = &intrq[i]; 444 1.2.2.2 nathanw TAILQ_INIT(&iq->iq_list); 445 1.2.2.2 nathanw 446 1.2.2.2 nathanw sprintf(iq->iq_name, "ipl %d", i); 447 1.2.2.2 nathanw evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 448 1.2.2.2 nathanw NULL, "ixpintr", iq->iq_name); 449 1.2.2.2 nathanw } 450 1.2.2.2 nathanw current_intr_depth = 0; 451 1.2.2.2 nathanw current_spl_level = 0; 452 1.2.2.2 nathanw 453 1.2.2.2 nathanw /* Enable IRQs (don't yet use FIQs). */ 454 1.2.2.2 nathanw enable_interrupts(I32_bit); 455 1.2.2.2 nathanw } 456 1.2.2.2 nathanw 457 1.2.2.2 nathanw void * 458 1.2.2.2 nathanw ixp12x0_intr_establish(int irq, int ipl, int (*ih_func)(void *), void *arg) 459 1.2.2.2 nathanw { 460 1.2.2.2 nathanw struct intrq* iq; 461 1.2.2.2 nathanw struct intrhand* ih; 462 1.2.2.2 nathanw u_int oldirqstate; 463 1.2.2.2 nathanw #ifdef DEBUG 464 1.2.2.2 nathanw printf("ixp12x0_intr_establish(%d, %d, %08x, %08x)\n", 465 1.2.2.2 nathanw irq, ipl, (u_int32_t) ih_func, (u_int32_t) arg); 466 1.2.2.2 nathanw #endif 467 1.2.2.2 nathanw if (irq < 0 || irq > NIRQ) 468 1.2.2.2 nathanw panic("ixp12x0_intr_establish: IRQ %d out of range", ipl); 469 1.2.2.2 nathanw if (ipl < 0 || ipl > NIPL) 470 1.2.2.2 nathanw panic("ixp12x0_intr_establish: IPL %d out of range", ipl); 471 1.2.2.2 nathanw 472 1.2.2.2 nathanw ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 473 1.2.2.2 nathanw if (ih == NULL) 474 1.2.2.2 nathanw return (NULL); 475 1.2.2.2 nathanw 476 1.2.2.2 nathanw ih->ih_func = ih_func; 477 1.2.2.2 nathanw ih->ih_arg = arg; 478 1.2.2.2 nathanw ih->ih_irq = irq; 479 1.2.2.2 nathanw ih->ih_ipl = ipl; 480 1.2.2.2 nathanw 481 1.2.2.2 nathanw iq = &intrq[irq]; 482 1.2.2.2 nathanw 483 1.2.2.2 nathanw oldirqstate = disable_interrupts(I32_bit); 484 1.2.2.2 nathanw TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 485 1.2.2.2 nathanw ixp12x0_intr_calculate_masks(); 486 1.2.2.2 nathanw restore_interrupts(oldirqstate); 487 1.2.2.2 nathanw 488 1.2.2.2 nathanw return (ih); 489 1.2.2.2 nathanw } 490 1.2.2.2 nathanw 491 1.2.2.2 nathanw void 492 1.2.2.2 nathanw ixp12x0_intr_disestablish(void *cookie) 493 1.2.2.2 nathanw { 494 1.2.2.2 nathanw struct intrhand* ih = cookie; 495 1.2.2.2 nathanw struct intrq* iq = &intrq[ih->ih_ipl]; 496 1.2.2.2 nathanw u_int oldirqstate; 497 1.2.2.2 nathanw 498 1.2.2.2 nathanw oldirqstate = disable_interrupts(I32_bit); 499 1.2.2.2 nathanw TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 500 1.2.2.2 nathanw ixp12x0_intr_calculate_masks(); 501 1.2.2.2 nathanw restore_interrupts(oldirqstate); 502 1.2.2.2 nathanw } 503 1.2.2.2 nathanw 504 1.2.2.2 nathanw void 505 1.2.2.2 nathanw ixp12x0_intr_dispatch(struct clockframe *frame) 506 1.2.2.2 nathanw { 507 1.2.2.2 nathanw struct intrq* iq; 508 1.2.2.2 nathanw struct intrhand* ih; 509 1.2.2.2 nathanw u_int oldirqstate; 510 1.2.2.2 nathanw int pcpl; 511 1.2.2.2 nathanw u_int32_t hwpend; 512 1.2.2.2 nathanw u_int32_t pci_hwpend; 513 1.2.2.2 nathanw int irq; 514 1.2.2.2 nathanw u_int32_t ibit; 515 1.2.2.2 nathanw 516 1.2.2.2 nathanw pcpl = current_spl_level; 517 1.2.2.2 nathanw 518 1.2.2.2 nathanw hwpend = ixp12x0_irq_read(); 519 1.2.2.2 nathanw pci_hwpend = ixp12x0_pci_irq_read(); 520 1.2.2.2 nathanw 521 1.2.2.2 nathanw while (hwpend) { 522 1.2.2.2 nathanw irq = ffs(hwpend) - 1; 523 1.2.2.2 nathanw ibit = (1U << irq); 524 1.2.2.2 nathanw 525 1.2.2.2 nathanw iq = &intrq[irq]; 526 1.2.2.2 nathanw iq->iq_ev.ev_count++; 527 1.2.2.2 nathanw uvmexp.intrs++; 528 1.2.2.2 nathanw for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 529 1.2.2.2 nathanw ih = TAILQ_NEXT(ih, ih_list)) { 530 1.2.2.2 nathanw int ipl; 531 1.2.2.2 nathanw current_spl_level = ipl = ih->ih_ipl; 532 1.2.2.2 nathanw ixp12x0_set_intrmask(imask[ipl] | hwpend, 533 1.2.2.2 nathanw pci_imask[ipl] | pci_hwpend); 534 1.2.2.2 nathanw oldirqstate = enable_interrupts(I32_bit); 535 1.2.2.2 nathanw (void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 536 1.2.2.2 nathanw restore_interrupts(oldirqstate); 537 1.2.2.2 nathanw hwpend &= ~ibit; 538 1.2.2.2 nathanw } 539 1.2.2.2 nathanw } 540 1.2.2.2 nathanw while (pci_hwpend) { 541 1.2.2.2 nathanw irq = ffs(pci_hwpend) - 1; 542 1.2.2.2 nathanw ibit = (1U << irq); 543 1.2.2.2 nathanw 544 1.2.2.2 nathanw iq = &intrq[irq + SYS_NIRQ]; 545 1.2.2.2 nathanw iq->iq_ev.ev_count++; 546 1.2.2.2 nathanw uvmexp.intrs++; 547 1.2.2.2 nathanw for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 548 1.2.2.2 nathanw ih = TAILQ_NEXT(ih, ih_list)) { 549 1.2.2.2 nathanw int ipl; 550 1.2.2.2 nathanw 551 1.2.2.2 nathanw current_spl_level = ipl = ih->ih_ipl; 552 1.2.2.2 nathanw ixp12x0_set_intrmask(imask[ipl] | hwpend, 553 1.2.2.2 nathanw pci_imask[ipl] | pci_hwpend); 554 1.2.2.2 nathanw oldirqstate = enable_interrupts(I32_bit); 555 1.2.2.2 nathanw (void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 556 1.2.2.2 nathanw restore_interrupts(oldirqstate); 557 1.2.2.2 nathanw pci_hwpend &= ~ibit; 558 1.2.2.2 nathanw } 559 1.2.2.2 nathanw } 560 1.2.2.2 nathanw 561 1.2.2.2 nathanw splx(pcpl); 562 1.2.2.2 nathanw 563 1.2.2.2 nathanw /* Check for pendings soft intrs. */ 564 1.2.2.2 nathanw if ((ipending & INT_SWMASK) & ~imask[pcpl]) { 565 1.2.2.2 nathanw oldirqstate = enable_interrupts(I32_bit); 566 1.2.2.2 nathanw ixp12x0_do_pending(); 567 1.2.2.2 nathanw restore_interrupts(oldirqstate); 568 1.2.2.2 nathanw } 569 1.2.2.2 nathanw } 570
Indexes created Sat Nov 01 05:10:12 GMT 2025