ixp12x0_intr.c revision 1.2.2.3
1 1.2.2.3 thorpej /* $NetBSD: ixp12x0_intr.c,v 1.2.2.3 2002/12/11 05:53:10 thorpej Exp $ */ 2 1.2.2.2 nathanw 3 1.2.2.2 nathanw /* 4 1.2.2.2 nathanw * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 1.2.2.2 nathanw * All rights reserved. 6 1.2.2.2 nathanw * 7 1.2.2.2 nathanw * This code is derived from software contributed to The NetBSD Foundation 8 1.2.2.2 nathanw * by Ichiro FUKUHARA and Naoto Shimazaki. 9 1.2.2.2 nathanw * 10 1.2.2.2 nathanw * Redistribution and use in source and binary forms, with or without 11 1.2.2.2 nathanw * modification, are permitted provided that the following conditions 12 1.2.2.2 nathanw * are met: 13 1.2.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 14 1.2.2.2 nathanw * notice, this list of conditions and the following disclaimer. 15 1.2.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 16 1.2.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 17 1.2.2.2 nathanw * documentation and/or other materials provided with the distribution. 18 1.2.2.2 nathanw * 3. All advertising materials mentioning features or use of this software 19 1.2.2.2 nathanw * must display the following acknowledgement: 20 1.2.2.2 nathanw * This product includes software developed by the NetBSD 21 1.2.2.2 nathanw * Foundation, Inc. and its contributors. 22 1.2.2.2 nathanw * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.2.2.2 nathanw * contributors may be used to endorse or promote products derived 24 1.2.2.2 nathanw * from this software without specific prior written permission. 25 1.2.2.2 nathanw * 26 1.2.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.2.2.2 nathanw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.2.2.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.2.2.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.2.2.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.2.2.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.2.2.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.2.2.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.2.2.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.2.2.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.2.2.2 nathanw * POSSIBILITY OF SUCH DAMAGE. 37 1.2.2.2 nathanw */ 38 1.2.2.2 nathanw 39 1.2.2.2 nathanw /* 40 1.2.2.2 nathanw * Interrupt support for the Intel ixp12x0 41 1.2.2.2 nathanw */ 42 1.2.2.2 nathanw 43 1.2.2.2 nathanw #include <sys/param.h> 44 1.2.2.2 nathanw #include <sys/systm.h> 45 1.2.2.2 nathanw #include <sys/malloc.h> 46 1.2.2.3 thorpej #include <sys/termios.h> 47 1.2.2.2 nathanw 48 1.2.2.2 nathanw #include <uvm/uvm_extern.h> 49 1.2.2.2 nathanw 50 1.2.2.2 nathanw #include <machine/bus.h> 51 1.2.2.2 nathanw #include <machine/intr.h> 52 1.2.2.2 nathanw 53 1.2.2.2 nathanw #include <arm/cpufunc.h> 54 1.2.2.2 nathanw 55 1.2.2.2 nathanw #include <arm/ixp12x0/ixp12x0reg.h> 56 1.2.2.2 nathanw #include <arm/ixp12x0/ixp12x0var.h> 57 1.2.2.2 nathanw #include <arm/ixp12x0/ixp12x0_comreg.h> 58 1.2.2.3 thorpej #include <arm/ixp12x0/ixp12x0_comvar.h> 59 1.2.2.2 nathanw #include <arm/ixp12x0/ixp12x0_pcireg.h> 60 1.2.2.2 nathanw 61 1.2.2.2 nathanw extern u_int32_t ixpcom_cr; /* current cr from *_com.c */ 62 1.2.2.2 nathanw extern u_int32_t ixpcom_imask; /* tell mask to *_com.c */ 63 1.2.2.2 nathanw 64 1.2.2.2 nathanw /* Interrupt handler queues. */ 65 1.2.2.2 nathanw struct intrq intrq[NIRQ]; 66 1.2.2.2 nathanw 67 1.2.2.2 nathanw /* Interrupts to mask at each level. */ 68 1.2.2.2 nathanw static u_int32_t imask[NIPL]; 69 1.2.2.2 nathanw static u_int32_t pci_imask[NIPL]; 70 1.2.2.2 nathanw 71 1.2.2.2 nathanw /* Current interrupt priority level. */ 72 1.2.2.2 nathanw __volatile int current_spl_level; 73 1.2.2.2 nathanw 74 1.2.2.2 nathanw /* Software copy of the IRQs we have enabled. */ 75 1.2.2.2 nathanw __volatile u_int32_t intr_enabled; 76 1.2.2.2 nathanw __volatile u_int32_t pci_intr_enabled; 77 1.2.2.2 nathanw 78 1.2.2.2 nathanw /* Interrupts pending. */ 79 1.2.2.2 nathanw static __volatile int ipending; 80 1.2.2.2 nathanw 81 1.2.2.2 nathanw /* 82 1.2.2.2 nathanw * Map a software interrupt queue index (to the unused bits in the 83 1.2.2.2 nathanw * ICU registers -- XXX will need to revisit this if those bits are 84 1.2.2.2 nathanw * ever used in future steppings). 85 1.2.2.2 nathanw */ 86 1.2.2.2 nathanw static const uint32_t si_to_irqbit[SI_NQUEUES] = { 87 1.2.2.2 nathanw IXP12X0_INTR_bit30, /* SI_SOFT */ 88 1.2.2.2 nathanw IXP12X0_INTR_bit29, /* SI_SOFTCLOCK */ 89 1.2.2.2 nathanw IXP12X0_INTR_bit28, /* SI_SOFTNET */ 90 1.2.2.2 nathanw IXP12X0_INTR_bit27, /* SI_SOFTSERIAL */ 91 1.2.2.2 nathanw }; 92 1.2.2.2 nathanw 93 1.2.2.2 nathanw #define INT_SWMASK \ 94 1.2.2.2 nathanw ((1U << IXP12X0_INTR_bit30) | (1U << IXP12X0_INTR_bit29) | \ 95 1.2.2.2 nathanw (1U << IXP12X0_INTR_bit28) | (1U << IXP12X0_INTR_bit27)) 96 1.2.2.2 nathanw 97 1.2.2.2 nathanw #define SI_TO_IRQBIT(si) (1U << si_to_irqbit[(si)]) 98 1.2.2.2 nathanw 99 1.2.2.2 nathanw /* 100 1.2.2.2 nathanw * Map a software interrupt queue to an interrupt priority level. 101 1.2.2.2 nathanw */ 102 1.2.2.2 nathanw static const int si_to_ipl[SI_NQUEUES] = { 103 1.2.2.2 nathanw IPL_SOFT, /* SI_SOFT */ 104 1.2.2.2 nathanw IPL_SOFTCLOCK, /* SI_SOFTCLOCK */ 105 1.2.2.2 nathanw IPL_SOFTNET, /* SI_SOFTNET */ 106 1.2.2.2 nathanw IPL_SOFTSERIAL, /* SI_SOFTSERIAL */ 107 1.2.2.2 nathanw }; 108 1.2.2.2 nathanw 109 1.2.2.2 nathanw void ixp12x0_intr_dispatch(struct irqframe *frame); 110 1.2.2.2 nathanw 111 1.2.2.2 nathanw static __inline u_int32_t 112 1.2.2.2 nathanw ixp12x0_irq_read(void) 113 1.2.2.2 nathanw { 114 1.2.2.2 nathanw return IXPREG(IXP12X0_IRQ_VBASE) & IXP12X0_INTR_MASK; 115 1.2.2.2 nathanw } 116 1.2.2.2 nathanw 117 1.2.2.2 nathanw static __inline u_int32_t 118 1.2.2.2 nathanw ixp12x0_pci_irq_read(void) 119 1.2.2.2 nathanw { 120 1.2.2.2 nathanw return IXPREG(IXPPCI_IRQ_STATUS); 121 1.2.2.2 nathanw } 122 1.2.2.2 nathanw 123 1.2.2.2 nathanw static void 124 1.2.2.2 nathanw ixp12x0_enable_uart_irq(void) 125 1.2.2.2 nathanw { 126 1.2.2.2 nathanw ixpcom_imask = 0; 127 1.2.2.3 thorpej if (ixpcom_sc) 128 1.2.2.3 thorpej bus_space_write_4(ixpcom_sc->sc_iot, ixpcom_sc->sc_ioh, 129 1.2.2.3 thorpej IXPCOM_CR, ixpcom_cr & ~ixpcom_imask); 130 1.2.2.2 nathanw } 131 1.2.2.2 nathanw 132 1.2.2.2 nathanw static void 133 1.2.2.2 nathanw ixp12x0_disable_uart_irq(void) 134 1.2.2.2 nathanw { 135 1.2.2.2 nathanw ixpcom_imask = CR_RIE | CR_XIE; 136 1.2.2.3 thorpej if (ixpcom_sc) 137 1.2.2.3 thorpej bus_space_write_4(ixpcom_sc->sc_iot, ixpcom_sc->sc_ioh, 138 1.2.2.3 thorpej IXPCOM_CR, ixpcom_cr & ~ixpcom_imask); 139 1.2.2.2 nathanw } 140 1.2.2.2 nathanw 141 1.2.2.2 nathanw static void 142 1.2.2.2 nathanw ixp12x0_set_intrmask(u_int32_t irqs, u_int32_t pci_irqs) 143 1.2.2.2 nathanw { 144 1.2.2.2 nathanw if (irqs & (1U << IXP12X0_INTR_UART)) { 145 1.2.2.2 nathanw ixp12x0_disable_uart_irq(); 146 1.2.2.2 nathanw } else { 147 1.2.2.2 nathanw ixp12x0_enable_uart_irq(); 148 1.2.2.2 nathanw } 149 1.2.2.2 nathanw IXPREG(IXPPCI_IRQ_ENABLE_CLEAR) = pci_irqs; 150 1.2.2.2 nathanw IXPREG(IXPPCI_IRQ_ENABLE_SET) = pci_intr_enabled & ~pci_irqs; 151 1.2.2.2 nathanw } 152 1.2.2.2 nathanw 153 1.2.2.2 nathanw static void 154 1.2.2.2 nathanw ixp12x0_enable_irq(int irq) 155 1.2.2.2 nathanw { 156 1.2.2.2 nathanw if (irq < SYS_NIRQ) { 157 1.2.2.2 nathanw intr_enabled |= (1U << irq); 158 1.2.2.2 nathanw switch (irq) { 159 1.2.2.2 nathanw case IXP12X0_INTR_UART: 160 1.2.2.2 nathanw ixp12x0_enable_uart_irq(); 161 1.2.2.2 nathanw break; 162 1.2.2.2 nathanw 163 1.2.2.2 nathanw case IXP12X0_INTR_PCI: 164 1.2.2.2 nathanw /* nothing to do */ 165 1.2.2.2 nathanw break; 166 1.2.2.2 nathanw default: 167 1.2.2.2 nathanw panic("enable_irq:bad IRQ %d", irq); 168 1.2.2.2 nathanw } 169 1.2.2.2 nathanw } else { 170 1.2.2.2 nathanw pci_intr_enabled |= (1U << (irq - SYS_NIRQ)); 171 1.2.2.2 nathanw IXPREG(IXPPCI_IRQ_ENABLE_SET) = (1U << (irq - SYS_NIRQ)); 172 1.2.2.2 nathanw } 173 1.2.2.2 nathanw } 174 1.2.2.2 nathanw 175 1.2.2.2 nathanw static __inline void 176 1.2.2.2 nathanw ixp12x0_disable_irq(int irq) 177 1.2.2.2 nathanw { 178 1.2.2.2 nathanw if (irq < SYS_NIRQ) { 179 1.2.2.2 nathanw intr_enabled ^= ~(1U << irq); 180 1.2.2.2 nathanw switch (irq) { 181 1.2.2.2 nathanw case IXP12X0_INTR_UART: 182 1.2.2.2 nathanw ixp12x0_disable_uart_irq(); 183 1.2.2.2 nathanw break; 184 1.2.2.2 nathanw 185 1.2.2.2 nathanw case IXP12X0_INTR_PCI: 186 1.2.2.2 nathanw /* nothing to do */ 187 1.2.2.2 nathanw break; 188 1.2.2.2 nathanw default: 189 1.2.2.2 nathanw /* nothing to do */ 190 1.2.2.2 nathanw } 191 1.2.2.2 nathanw } else { 192 1.2.2.2 nathanw pci_intr_enabled &= ~(1U << (irq - SYS_NIRQ)); 193 1.2.2.2 nathanw IXPREG(IXPPCI_IRQ_ENABLE_CLEAR) = (1U << (irq - SYS_NIRQ)); 194 1.2.2.2 nathanw } 195 1.2.2.2 nathanw } 196 1.2.2.2 nathanw 197 1.2.2.2 nathanw /* 198 1.2.2.2 nathanw * NOTE: This routine must be called with interrupts disabled in the CPSR. 199 1.2.2.2 nathanw */ 200 1.2.2.2 nathanw static void 201 1.2.2.2 nathanw ixp12x0_intr_calculate_masks(void) 202 1.2.2.2 nathanw { 203 1.2.2.2 nathanw struct intrq *iq; 204 1.2.2.2 nathanw struct intrhand *ih; 205 1.2.2.2 nathanw int irq, ipl; 206 1.2.2.2 nathanw 207 1.2.2.2 nathanw /* First, figure out which IPLs each IRQ has. */ 208 1.2.2.2 nathanw for (irq = 0; irq < NIRQ; irq++) { 209 1.2.2.2 nathanw int levels = 0; 210 1.2.2.2 nathanw iq = &intrq[irq]; 211 1.2.2.2 nathanw ixp12x0_disable_irq(irq); 212 1.2.2.2 nathanw for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 213 1.2.2.2 nathanw ih = TAILQ_NEXT(ih, ih_list)) 214 1.2.2.2 nathanw levels |= (1U << ih->ih_ipl); 215 1.2.2.2 nathanw iq->iq_levels = levels; 216 1.2.2.2 nathanw } 217 1.2.2.2 nathanw 218 1.2.2.2 nathanw /* Next, figure out which IRQs are used by each IPL. */ 219 1.2.2.2 nathanw for (ipl = 0; ipl < NIPL; ipl++) { 220 1.2.2.2 nathanw int irqs = 0; 221 1.2.2.2 nathanw int pci_irqs = 0; 222 1.2.2.2 nathanw for (irq = 0; irq < SYS_NIRQ; irq++) { 223 1.2.2.2 nathanw if (intrq[irq].iq_levels & (1U << ipl)) 224 1.2.2.2 nathanw irqs |= (1U << irq); 225 1.2.2.2 nathanw } 226 1.2.2.2 nathanw imask[ipl] = irqs; 227 1.2.2.2 nathanw for (irq = 0; irq < SYS_NIRQ; irq++) { 228 1.2.2.2 nathanw if (intrq[irq + SYS_NIRQ].iq_levels & (1U << ipl)) 229 1.2.2.2 nathanw pci_irqs |= (1U << irq); 230 1.2.2.2 nathanw } 231 1.2.2.2 nathanw pci_imask[ipl] = pci_irqs; 232 1.2.2.2 nathanw } 233 1.2.2.2 nathanw 234 1.2.2.2 nathanw imask[IPL_NONE] = 0; 235 1.2.2.2 nathanw pci_imask[IPL_NONE] = 0; 236 1.2.2.2 nathanw 237 1.2.2.2 nathanw /* 238 1.2.2.2 nathanw * Initialize the soft interrupt masks to block themselves. 239 1.2.2.2 nathanw */ 240 1.2.2.2 nathanw imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFT); 241 1.2.2.2 nathanw imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK); 242 1.2.2.2 nathanw imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET); 243 1.2.2.2 nathanw imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL); 244 1.2.2.2 nathanw 245 1.2.2.2 nathanw /* 246 1.2.2.2 nathanw * splsoftclock() is the only interface that users of the 247 1.2.2.2 nathanw * generic software interrupt facility have to block their 248 1.2.2.2 nathanw * soft intrs, so splsoftclock() must also block IPL_SOFT. 249 1.2.2.2 nathanw */ 250 1.2.2.2 nathanw imask[IPL_SOFTCLOCK] |= imask[IPL_SOFT]; 251 1.2.2.2 nathanw pci_imask[IPL_SOFTCLOCK] |= pci_imask[IPL_SOFT]; 252 1.2.2.2 nathanw 253 1.2.2.2 nathanw /* 254 1.2.2.2 nathanw * splsoftnet() must also block splsoftclock(), since we don't 255 1.2.2.2 nathanw * want timer-driven network events to occur while we're 256 1.2.2.2 nathanw * processing incoming packets. 257 1.2.2.2 nathanw */ 258 1.2.2.2 nathanw imask[IPL_SOFTNET] |= imask[IPL_SOFTCLOCK]; 259 1.2.2.2 nathanw pci_imask[IPL_SOFTNET] |= pci_imask[IPL_SOFTCLOCK]; 260 1.2.2.2 nathanw 261 1.2.2.2 nathanw /* 262 1.2.2.2 nathanw * Enforce a heirarchy that gives "slow" device (or devices with 263 1.2.2.2 nathanw * limited input buffer space/"real-time" requirements) a better 264 1.2.2.2 nathanw * chance at not dropping data. 265 1.2.2.2 nathanw */ 266 1.2.2.2 nathanw imask[IPL_BIO] |= imask[IPL_SOFTNET]; 267 1.2.2.2 nathanw pci_imask[IPL_BIO] |= pci_imask[IPL_SOFTNET]; 268 1.2.2.2 nathanw imask[IPL_NET] |= imask[IPL_BIO]; 269 1.2.2.2 nathanw pci_imask[IPL_NET] |= pci_imask[IPL_BIO]; 270 1.2.2.2 nathanw imask[IPL_SOFTSERIAL] |= pci_imask[IPL_NET]; 271 1.2.2.2 nathanw pci_imask[IPL_SOFTSERIAL] |= pci_imask[IPL_NET]; 272 1.2.2.2 nathanw imask[IPL_TTY] |= imask[IPL_SOFTSERIAL]; 273 1.2.2.2 nathanw pci_imask[IPL_TTY] |= pci_imask[IPL_SOFTSERIAL]; 274 1.2.2.2 nathanw 275 1.2.2.2 nathanw /* 276 1.2.2.2 nathanw * splvm() blocks all interrupts that use the kernel memory 277 1.2.2.2 nathanw * allocation facilities. 278 1.2.2.2 nathanw */ 279 1.2.2.2 nathanw imask[IPL_IMP] |= imask[IPL_TTY]; 280 1.2.2.2 nathanw pci_imask[IPL_IMP] |= pci_imask[IPL_TTY]; 281 1.2.2.2 nathanw 282 1.2.2.2 nathanw /* 283 1.2.2.2 nathanw * Audio devices are not allowed to perform memory allocation 284 1.2.2.2 nathanw * in their interrupt routines, and they have fairly "real-time" 285 1.2.2.2 nathanw * requirements, so give them a high interrupt priority. 286 1.2.2.2 nathanw */ 287 1.2.2.2 nathanw imask[IPL_AUDIO] |= imask[IPL_IMP]; 288 1.2.2.2 nathanw pci_imask[IPL_AUDIO] |= pci_imask[IPL_IMP]; 289 1.2.2.2 nathanw 290 1.2.2.2 nathanw /* 291 1.2.2.2 nathanw * splclock() must block anything that uses the scheduler. 292 1.2.2.2 nathanw */ 293 1.2.2.2 nathanw imask[IPL_CLOCK] |= imask[IPL_AUDIO]; 294 1.2.2.2 nathanw pci_imask[IPL_CLOCK] |= pci_imask[IPL_AUDIO]; 295 1.2.2.2 nathanw 296 1.2.2.2 nathanw /* 297 1.2.2.2 nathanw * No separate statclock on the IQ80310. 298 1.2.2.2 nathanw */ 299 1.2.2.2 nathanw imask[IPL_STATCLOCK] |= imask[IPL_CLOCK]; 300 1.2.2.2 nathanw pci_imask[IPL_STATCLOCK] |= pci_imask[IPL_CLOCK]; 301 1.2.2.2 nathanw 302 1.2.2.2 nathanw /* 303 1.2.2.2 nathanw * splhigh() must block "everything". 304 1.2.2.2 nathanw */ 305 1.2.2.2 nathanw imask[IPL_HIGH] |= imask[IPL_STATCLOCK]; 306 1.2.2.2 nathanw pci_imask[IPL_HIGH] |= pci_imask[IPL_STATCLOCK]; 307 1.2.2.2 nathanw 308 1.2.2.2 nathanw /* 309 1.2.2.2 nathanw * XXX We need serial drivers to run at the absolute highest priority 310 1.2.2.2 nathanw * in order to avoid overruns, so serial > high. 311 1.2.2.2 nathanw */ 312 1.2.2.2 nathanw imask[IPL_SERIAL] |= imask[IPL_HIGH]; 313 1.2.2.2 nathanw pci_imask[IPL_SERIAL] |= pci_imask[IPL_HIGH]; 314 1.2.2.2 nathanw 315 1.2.2.2 nathanw /* 316 1.2.2.2 nathanw * Now compute which IRQs must be blocked when servicing any 317 1.2.2.2 nathanw * given IRQ. 318 1.2.2.2 nathanw */ 319 1.2.2.2 nathanw for (irq = 0; irq < NIRQ; irq++) { 320 1.2.2.2 nathanw int irqs; 321 1.2.2.2 nathanw int pci_irqs; 322 1.2.2.2 nathanw 323 1.2.2.2 nathanw if (irq < SYS_NIRQ) { 324 1.2.2.2 nathanw irqs = (1U << irq); 325 1.2.2.2 nathanw pci_irqs = 0; 326 1.2.2.2 nathanw } else { 327 1.2.2.2 nathanw irqs = 0; 328 1.2.2.2 nathanw pci_irqs = (1U << (irq - SYS_NIRQ)); 329 1.2.2.2 nathanw } 330 1.2.2.2 nathanw iq = &intrq[irq]; 331 1.2.2.2 nathanw if (TAILQ_FIRST(&iq->iq_list) != NULL) 332 1.2.2.2 nathanw ixp12x0_enable_irq(irq); 333 1.2.2.2 nathanw for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 334 1.2.2.2 nathanw ih = TAILQ_NEXT(ih, ih_list)) { 335 1.2.2.2 nathanw irqs |= imask[ih->ih_ipl]; 336 1.2.2.2 nathanw pci_irqs |= pci_imask[ih->ih_ipl]; 337 1.2.2.2 nathanw } 338 1.2.2.2 nathanw iq->iq_mask = irqs; 339 1.2.2.2 nathanw iq->iq_pci_mask = pci_irqs; 340 1.2.2.2 nathanw } 341 1.2.2.2 nathanw } 342 1.2.2.2 nathanw 343 1.2.2.2 nathanw static void 344 1.2.2.2 nathanw ixp12x0_do_pending(void) 345 1.2.2.2 nathanw { 346 1.2.2.2 nathanw static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED; 347 1.2.2.2 nathanw int new; 348 1.2.2.2 nathanw u_int oldirqstate; 349 1.2.2.2 nathanw 350 1.2.2.2 nathanw if (__cpu_simple_lock_try(&processing) == 0) 351 1.2.2.2 nathanw return; 352 1.2.2.2 nathanw 353 1.2.2.2 nathanw new = current_spl_level; 354 1.2.2.2 nathanw 355 1.2.2.2 nathanw oldirqstate = disable_interrupts(I32_bit); 356 1.2.2.2 nathanw 357 1.2.2.2 nathanw #define DO_SOFTINT(si) \ 358 1.2.2.2 nathanw if ((ipending & ~imask[new]) & SI_TO_IRQBIT(si)) { \ 359 1.2.2.2 nathanw ipending &= ~SI_TO_IRQBIT(si); \ 360 1.2.2.2 nathanw current_spl_level = si_to_ipl[(si)]; \ 361 1.2.2.2 nathanw restore_interrupts(oldirqstate); \ 362 1.2.2.2 nathanw softintr_dispatch(si); \ 363 1.2.2.2 nathanw oldirqstate = disable_interrupts(I32_bit); \ 364 1.2.2.2 nathanw current_spl_level = new; \ 365 1.2.2.2 nathanw } 366 1.2.2.2 nathanw 367 1.2.2.2 nathanw DO_SOFTINT(SI_SOFTSERIAL); 368 1.2.2.2 nathanw DO_SOFTINT(SI_SOFTNET); 369 1.2.2.2 nathanw DO_SOFTINT(SI_SOFTCLOCK); 370 1.2.2.2 nathanw DO_SOFTINT(SI_SOFT); 371 1.2.2.2 nathanw 372 1.2.2.2 nathanw __cpu_simple_unlock(&processing); 373 1.2.2.2 nathanw 374 1.2.2.2 nathanw restore_interrupts(oldirqstate); 375 1.2.2.2 nathanw } 376 1.2.2.2 nathanw 377 1.2.2.2 nathanw __inline void 378 1.2.2.2 nathanw splx(int new) 379 1.2.2.2 nathanw { 380 1.2.2.2 nathanw int old; 381 1.2.2.2 nathanw u_int oldirqstate; 382 1.2.2.2 nathanw 383 1.2.2.2 nathanw if (current_spl_level == new) 384 1.2.2.2 nathanw return; 385 1.2.2.2 nathanw oldirqstate = disable_interrupts(I32_bit); 386 1.2.2.2 nathanw old = current_spl_level; 387 1.2.2.2 nathanw current_spl_level = new; 388 1.2.2.2 nathanw ixp12x0_set_intrmask(imask[new], pci_imask[new]); 389 1.2.2.2 nathanw restore_interrupts(oldirqstate); 390 1.2.2.2 nathanw 391 1.2.2.2 nathanw /* If there are software interrupts to process, do it. */ 392 1.2.2.2 nathanw if ((ipending & INT_SWMASK) & ~imask[new]) 393 1.2.2.2 nathanw ixp12x0_do_pending(); 394 1.2.2.2 nathanw } 395 1.2.2.2 nathanw 396 1.2.2.2 nathanw int 397 1.2.2.2 nathanw _splraise(int ipl) 398 1.2.2.2 nathanw { 399 1.2.2.2 nathanw int old = current_spl_level; 400 1.2.2.2 nathanw 401 1.2.2.2 nathanw if (old >= ipl) 402 1.2.2.2 nathanw return (old); 403 1.2.2.2 nathanw splx(ipl); 404 1.2.2.2 nathanw return (old); 405 1.2.2.2 nathanw } 406 1.2.2.2 nathanw 407 1.2.2.2 nathanw int 408 1.2.2.2 nathanw _spllower(int ipl) 409 1.2.2.2 nathanw { 410 1.2.2.2 nathanw int old = current_spl_level; 411 1.2.2.2 nathanw 412 1.2.2.2 nathanw if (old <= ipl) 413 1.2.2.2 nathanw return (old); 414 1.2.2.2 nathanw splx(ipl); 415 1.2.2.2 nathanw return (old); 416 1.2.2.2 nathanw } 417 1.2.2.2 nathanw 418 1.2.2.2 nathanw void 419 1.2.2.2 nathanw _setsoftintr(int si) 420 1.2.2.2 nathanw { 421 1.2.2.2 nathanw u_int oldirqstate; 422 1.2.2.2 nathanw 423 1.2.2.2 nathanw oldirqstate = disable_interrupts(I32_bit); 424 1.2.2.2 nathanw ipending |= SI_TO_IRQBIT(si); 425 1.2.2.2 nathanw restore_interrupts(oldirqstate); 426 1.2.2.2 nathanw 427 1.2.2.2 nathanw /* Process unmasked pending soft interrupts. */ 428 1.2.2.2 nathanw if ((ipending & INT_SWMASK) & ~imask[current_spl_level]) 429 1.2.2.2 nathanw ixp12x0_do_pending(); 430 1.2.2.2 nathanw } 431 1.2.2.2 nathanw 432 1.2.2.2 nathanw /* 433 1.2.2.2 nathanw * ixp12x0_intr_init: 434 1.2.2.2 nathanw * 435 1.2.2.2 nathanw * Initialize the rest of the interrupt subsystem, making it 436 1.2.2.2 nathanw * ready to handle interrupts from devices. 437 1.2.2.2 nathanw */ 438 1.2.2.2 nathanw void 439 1.2.2.2 nathanw ixp12x0_intr_init(void) 440 1.2.2.2 nathanw { 441 1.2.2.2 nathanw struct intrq *iq; 442 1.2.2.2 nathanw int i; 443 1.2.2.2 nathanw 444 1.2.2.2 nathanw intr_enabled = 0; 445 1.2.2.2 nathanw pci_intr_enabled = 0; 446 1.2.2.2 nathanw 447 1.2.2.2 nathanw for (i = 0; i < NIRQ; i++) { 448 1.2.2.2 nathanw iq = &intrq[i]; 449 1.2.2.2 nathanw TAILQ_INIT(&iq->iq_list); 450 1.2.2.2 nathanw 451 1.2.2.2 nathanw sprintf(iq->iq_name, "ipl %d", i); 452 1.2.2.2 nathanw evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 453 1.2.2.2 nathanw NULL, "ixpintr", iq->iq_name); 454 1.2.2.2 nathanw } 455 1.2.2.2 nathanw current_intr_depth = 0; 456 1.2.2.2 nathanw current_spl_level = 0; 457 1.2.2.2 nathanw 458 1.2.2.2 nathanw /* Enable IRQs (don't yet use FIQs). */ 459 1.2.2.2 nathanw enable_interrupts(I32_bit); 460 1.2.2.2 nathanw } 461 1.2.2.2 nathanw 462 1.2.2.2 nathanw void * 463 1.2.2.2 nathanw ixp12x0_intr_establish(int irq, int ipl, int (*ih_func)(void *), void *arg) 464 1.2.2.2 nathanw { 465 1.2.2.2 nathanw struct intrq* iq; 466 1.2.2.2 nathanw struct intrhand* ih; 467 1.2.2.2 nathanw u_int oldirqstate; 468 1.2.2.2 nathanw #ifdef DEBUG 469 1.2.2.2 nathanw printf("ixp12x0_intr_establish(%d, %d, %08x, %08x)\n", 470 1.2.2.2 nathanw irq, ipl, (u_int32_t) ih_func, (u_int32_t) arg); 471 1.2.2.2 nathanw #endif 472 1.2.2.2 nathanw if (irq < 0 || irq > NIRQ) 473 1.2.2.2 nathanw panic("ixp12x0_intr_establish: IRQ %d out of range", ipl); 474 1.2.2.2 nathanw if (ipl < 0 || ipl > NIPL) 475 1.2.2.2 nathanw panic("ixp12x0_intr_establish: IPL %d out of range", ipl); 476 1.2.2.2 nathanw 477 1.2.2.2 nathanw ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 478 1.2.2.2 nathanw if (ih == NULL) 479 1.2.2.2 nathanw return (NULL); 480 1.2.2.2 nathanw 481 1.2.2.2 nathanw ih->ih_func = ih_func; 482 1.2.2.2 nathanw ih->ih_arg = arg; 483 1.2.2.2 nathanw ih->ih_irq = irq; 484 1.2.2.2 nathanw ih->ih_ipl = ipl; 485 1.2.2.2 nathanw 486 1.2.2.2 nathanw iq = &intrq[irq]; 487 1.2.2.2 nathanw 488 1.2.2.2 nathanw oldirqstate = disable_interrupts(I32_bit); 489 1.2.2.2 nathanw TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 490 1.2.2.2 nathanw ixp12x0_intr_calculate_masks(); 491 1.2.2.2 nathanw restore_interrupts(oldirqstate); 492 1.2.2.2 nathanw 493 1.2.2.2 nathanw return (ih); 494 1.2.2.2 nathanw } 495 1.2.2.2 nathanw 496 1.2.2.2 nathanw void 497 1.2.2.2 nathanw ixp12x0_intr_disestablish(void *cookie) 498 1.2.2.2 nathanw { 499 1.2.2.2 nathanw struct intrhand* ih = cookie; 500 1.2.2.2 nathanw struct intrq* iq = &intrq[ih->ih_ipl]; 501 1.2.2.2 nathanw u_int oldirqstate; 502 1.2.2.2 nathanw 503 1.2.2.2 nathanw oldirqstate = disable_interrupts(I32_bit); 504 1.2.2.2 nathanw TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 505 1.2.2.2 nathanw ixp12x0_intr_calculate_masks(); 506 1.2.2.2 nathanw restore_interrupts(oldirqstate); 507 1.2.2.2 nathanw } 508 1.2.2.2 nathanw 509 1.2.2.2 nathanw void 510 1.2.2.2 nathanw ixp12x0_intr_dispatch(struct clockframe *frame) 511 1.2.2.2 nathanw { 512 1.2.2.2 nathanw struct intrq* iq; 513 1.2.2.2 nathanw struct intrhand* ih; 514 1.2.2.2 nathanw u_int oldirqstate; 515 1.2.2.2 nathanw int pcpl; 516 1.2.2.2 nathanw u_int32_t hwpend; 517 1.2.2.2 nathanw u_int32_t pci_hwpend; 518 1.2.2.2 nathanw int irq; 519 1.2.2.2 nathanw u_int32_t ibit; 520 1.2.2.2 nathanw 521 1.2.2.2 nathanw pcpl = current_spl_level; 522 1.2.2.2 nathanw 523 1.2.2.2 nathanw hwpend = ixp12x0_irq_read(); 524 1.2.2.2 nathanw pci_hwpend = ixp12x0_pci_irq_read(); 525 1.2.2.2 nathanw 526 1.2.2.2 nathanw while (hwpend) { 527 1.2.2.2 nathanw irq = ffs(hwpend) - 1; 528 1.2.2.2 nathanw ibit = (1U << irq); 529 1.2.2.2 nathanw 530 1.2.2.2 nathanw iq = &intrq[irq]; 531 1.2.2.2 nathanw iq->iq_ev.ev_count++; 532 1.2.2.2 nathanw uvmexp.intrs++; 533 1.2.2.2 nathanw for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 534 1.2.2.2 nathanw ih = TAILQ_NEXT(ih, ih_list)) { 535 1.2.2.2 nathanw int ipl; 536 1.2.2.2 nathanw current_spl_level = ipl = ih->ih_ipl; 537 1.2.2.2 nathanw ixp12x0_set_intrmask(imask[ipl] | hwpend, 538 1.2.2.2 nathanw pci_imask[ipl] | pci_hwpend); 539 1.2.2.2 nathanw oldirqstate = enable_interrupts(I32_bit); 540 1.2.2.2 nathanw (void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 541 1.2.2.2 nathanw restore_interrupts(oldirqstate); 542 1.2.2.2 nathanw hwpend &= ~ibit; 543 1.2.2.2 nathanw } 544 1.2.2.2 nathanw } 545 1.2.2.2 nathanw while (pci_hwpend) { 546 1.2.2.2 nathanw irq = ffs(pci_hwpend) - 1; 547 1.2.2.2 nathanw ibit = (1U << irq); 548 1.2.2.2 nathanw 549 1.2.2.2 nathanw iq = &intrq[irq + SYS_NIRQ]; 550 1.2.2.2 nathanw iq->iq_ev.ev_count++; 551 1.2.2.2 nathanw uvmexp.intrs++; 552 1.2.2.2 nathanw for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 553 1.2.2.2 nathanw ih = TAILQ_NEXT(ih, ih_list)) { 554 1.2.2.2 nathanw int ipl; 555 1.2.2.2 nathanw 556 1.2.2.2 nathanw current_spl_level = ipl = ih->ih_ipl; 557 1.2.2.2 nathanw ixp12x0_set_intrmask(imask[ipl] | hwpend, 558 1.2.2.2 nathanw pci_imask[ipl] | pci_hwpend); 559 1.2.2.2 nathanw oldirqstate = enable_interrupts(I32_bit); 560 1.2.2.2 nathanw (void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 561 1.2.2.2 nathanw restore_interrupts(oldirqstate); 562 1.2.2.2 nathanw pci_hwpend &= ~ibit; 563 1.2.2.2 nathanw } 564 1.2.2.2 nathanw } 565 1.2.2.2 nathanw 566 1.2.2.2 nathanw splx(pcpl); 567 1.2.2.2 nathanw 568 1.2.2.2 nathanw /* Check for pendings soft intrs. */ 569 1.2.2.2 nathanw if ((ipending & INT_SWMASK) & ~imask[pcpl]) { 570 1.2.2.2 nathanw oldirqstate = enable_interrupts(I32_bit); 571 1.2.2.2 nathanw ixp12x0_do_pending(); 572 1.2.2.2 nathanw restore_interrupts(oldirqstate); 573 1.2.2.2 nathanw } 574 1.2.2.2 nathanw } 575
Indexes created Wed Oct 29 03:09:52 GMT 2025