ixp12x0_intr.c revision 1.15.30.1
1 /* $NetBSD: ixp12x0_intr.c,v 1.15.30.1 2007/11/09 05:37:40 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Ichiro FUKUHARA and Naoto Shimazaki. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: ixp12x0_intr.c,v 1.15.30.1 2007/11/09 05:37:40 matt Exp $"); 41 42 /* 43 * Interrupt support for the Intel ixp12x0 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 #include <sys/termios.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include <machine/bus.h> 54 #include <machine/intr.h> 55 56 #include <arm/cpufunc.h> 57 58 #include <arm/ixp12x0/ixp12x0reg.h> 59 #include <arm/ixp12x0/ixp12x0var.h> 60 #include <arm/ixp12x0/ixp12x0_comreg.h> 61 #include <arm/ixp12x0/ixp12x0_comvar.h> 62 #include <arm/ixp12x0/ixp12x0_pcireg.h> 63 64 65 extern u_int32_t ixpcom_cr; /* current cr from *_com.c */ 66 extern u_int32_t ixpcom_imask; /* tell mask to *_com.c */ 67 68 /* Interrupt handler queues. */ 69 struct intrq intrq[NIRQ]; 70 71 /* Interrupts to mask at each level. */ 72 static u_int32_t imask[NIPL]; 73 static u_int32_t pci_imask[NIPL]; 74 75 /* Current interrupt priority level. */ 76 volatile int hardware_spl_level; 77 78 /* Software copy of the IRQs we have enabled. */ 79 volatile u_int32_t intr_enabled; 80 volatile u_int32_t pci_intr_enabled; 81 82 /* Interrupts pending. */ 83 static volatile int ipending; 84 85 /* 86 * Map a software interrupt queue index (to the unused bits in the 87 * ICU registers -- XXX will need to revisit this if those bits are 88 * ever used in future steppings). 89 */ 90 static const u_int32_t si_to_irqbit[SI_NQUEUES] = { 91 IXP12X0_INTR_bit30, /* SI_SOFT */ 92 IXP12X0_INTR_bit29, /* SI_SOFTCLOCK */ 93 IXP12X0_INTR_bit28, /* SI_SOFTNET */ 94 IXP12X0_INTR_bit27, /* SI_SOFTSERIAL */ 95 }; 96 97 #define INT_SWMASK \ 98 ((1U << IXP12X0_INTR_bit30) | (1U << IXP12X0_INTR_bit29) | \ 99 (1U << IXP12X0_INTR_bit28) | (1U << IXP12X0_INTR_bit27)) 100 101 #define SI_TO_IRQBIT(si) (1U << si_to_irqbit[(si)]) 102 103 /* 104 * Map a software interrupt queue to an interrupt priority level. 105 */ 106 static const int si_to_ipl[SI_NQUEUES] = { 107 IPL_SOFT, /* SI_SOFT */ 108 IPL_SOFTCLOCK, /* SI_SOFTCLOCK */ 109 IPL_SOFTNET, /* SI_SOFTNET */ 110 IPL_SOFTSERIAL, /* SI_SOFTSERIAL */ 111 }; 112 113 void ixp12x0_intr_dispatch(struct irqframe *frame); 114 115 #define IXPREG(reg) *((volatile u_int32_t*) (reg)) 116 117 static inline u_int32_t 118 ixp12x0_irq_read(void) 119 { 120 return IXPREG(IXP12X0_IRQ_VBASE) & IXP12X0_INTR_MASK; 121 } 122 123 static inline u_int32_t 124 ixp12x0_pci_irq_read(void) 125 { 126 return IXPREG(IXPPCI_IRQ_STATUS); 127 } 128 129 static void 130 ixp12x0_enable_uart_irq(void) 131 { 132 ixpcom_imask = 0; 133 if (ixpcom_sc) 134 bus_space_write_4(ixpcom_sc->sc_iot, ixpcom_sc->sc_ioh, 135 IXPCOM_CR, ixpcom_cr & ~ixpcom_imask); 136 } 137 138 static void 139 ixp12x0_disable_uart_irq(void) 140 { 141 ixpcom_imask = CR_RIE | CR_XIE; 142 if (ixpcom_sc) 143 bus_space_write_4(ixpcom_sc->sc_iot, ixpcom_sc->sc_ioh, 144 IXPCOM_CR, ixpcom_cr & ~ixpcom_imask); 145 } 146 147 static void 148 ixp12x0_set_intrmask(u_int32_t irqs, u_int32_t pci_irqs) 149 { 150 if (irqs & (1U << IXP12X0_INTR_UART)) { 151 ixp12x0_disable_uart_irq(); 152 } else { 153 ixp12x0_enable_uart_irq(); 154 } 155 IXPREG(IXPPCI_IRQ_ENABLE_CLEAR) = pci_irqs; 156 IXPREG(IXPPCI_IRQ_ENABLE_SET) = pci_intr_enabled & ~pci_irqs; 157 } 158 159 static void 160 ixp12x0_enable_irq(int irq) 161 { 162 if (irq < SYS_NIRQ) { 163 intr_enabled |= (1U << irq); 164 switch (irq) { 165 case IXP12X0_INTR_UART: 166 ixp12x0_enable_uart_irq(); 167 break; 168 169 case IXP12X0_INTR_PCI: 170 /* nothing to do */ 171 break; 172 default: 173 panic("enable_irq:bad IRQ %d", irq); 174 } 175 } else { 176 pci_intr_enabled |= (1U << (irq - SYS_NIRQ)); 177 IXPREG(IXPPCI_IRQ_ENABLE_SET) = (1U << (irq - SYS_NIRQ)); 178 } 179 } 180 181 static inline void 182 ixp12x0_disable_irq(int irq) 183 { 184 if (irq < SYS_NIRQ) { 185 intr_enabled ^= ~(1U << irq); 186 switch (irq) { 187 case IXP12X0_INTR_UART: 188 ixp12x0_disable_uart_irq(); 189 break; 190 191 case IXP12X0_INTR_PCI: 192 /* nothing to do */ 193 break; 194 default: 195 /* nothing to do */ 196 break; 197 } 198 } else { 199 pci_intr_enabled &= ~(1U << (irq - SYS_NIRQ)); 200 IXPREG(IXPPCI_IRQ_ENABLE_CLEAR) = (1U << (irq - SYS_NIRQ)); 201 } 202 } 203 204 /* 205 * NOTE: This routine must be called with interrupts disabled in the CPSR. 206 */ 207 static void 208 ixp12x0_intr_calculate_masks(void) 209 { 210 struct intrq *iq; 211 struct intrhand *ih; 212 int irq, ipl; 213 214 /* First, figure out which IPLs each IRQ has. */ 215 for (irq = 0; irq < NIRQ; irq++) { 216 int levels = 0; 217 iq = &intrq[irq]; 218 ixp12x0_disable_irq(irq); 219 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 220 ih = TAILQ_NEXT(ih, ih_list)) 221 levels |= (1U << ih->ih_ipl); 222 iq->iq_levels = levels; 223 } 224 225 /* Next, figure out which IRQs are used by each IPL. */ 226 for (ipl = 0; ipl < NIPL; ipl++) { 227 int irqs = 0; 228 int pci_irqs = 0; 229 for (irq = 0; irq < SYS_NIRQ; irq++) { 230 if (intrq[irq].iq_levels & (1U << ipl)) 231 irqs |= (1U << irq); 232 } 233 imask[ipl] = irqs; 234 for (irq = 0; irq < SYS_NIRQ; irq++) { 235 if (intrq[irq + SYS_NIRQ].iq_levels & (1U << ipl)) 236 pci_irqs |= (1U << irq); 237 } 238 pci_imask[ipl] = pci_irqs; 239 } 240 241 imask[IPL_NONE] = 0; 242 pci_imask[IPL_NONE] = 0; 243 244 /* 245 * Initialize the soft interrupt masks to block themselves. 246 */ 247 imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFT); 248 imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK); 249 imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET); 250 imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL); 251 252 /* 253 * splsoftclock() is the only interface that users of the 254 * generic software interrupt facility have to block their 255 * soft intrs, so splsoftclock() must also block IPL_SOFT. 256 */ 257 imask[IPL_SOFTCLOCK] |= imask[IPL_SOFT]; 258 pci_imask[IPL_SOFTCLOCK] |= pci_imask[IPL_SOFT]; 259 260 /* 261 * splsoftnet() must also block splsoftclock(), since we don't 262 * want timer-driven network events to occur while we're 263 * processing incoming packets. 264 */ 265 imask[IPL_SOFTNET] |= imask[IPL_SOFTCLOCK]; 266 pci_imask[IPL_SOFTNET] |= pci_imask[IPL_SOFTCLOCK]; 267 268 /* 269 * Enforce a hierarchy that gives "slow" device (or devices with 270 * limited input buffer space/"real-time" requirements) a better 271 * chance at not dropping data. 272 */ 273 imask[IPL_BIO] |= imask[IPL_SOFTNET]; 274 pci_imask[IPL_BIO] |= pci_imask[IPL_SOFTNET]; 275 imask[IPL_NET] |= imask[IPL_BIO]; 276 pci_imask[IPL_NET] |= pci_imask[IPL_BIO]; 277 imask[IPL_SOFTSERIAL] |= imask[IPL_NET]; 278 pci_imask[IPL_SOFTSERIAL] |= pci_imask[IPL_NET]; 279 imask[IPL_TTY] |= imask[IPL_SOFTSERIAL]; 280 pci_imask[IPL_TTY] |= pci_imask[IPL_SOFTSERIAL]; 281 282 /* 283 * splvm() blocks all interrupts that use the kernel memory 284 * allocation facilities. 285 */ 286 imask[IPL_VM] |= imask[IPL_TTY]; 287 pci_imask[IPL_VM] |= pci_imask[IPL_TTY]; 288 289 /* 290 * Audio devices are not allowed to perform memory allocation 291 * in their interrupt routines, and they have fairly "real-time" 292 * requirements, so give them a high interrupt priority. 293 */ 294 imask[IPL_AUDIO] |= imask[IPL_VM]; 295 pci_imask[IPL_AUDIO] |= pci_imask[IPL_VM]; 296 297 /* 298 * splclock() must block anything that uses the scheduler. 299 */ 300 imask[IPL_CLOCK] |= imask[IPL_AUDIO]; 301 pci_imask[IPL_CLOCK] |= pci_imask[IPL_AUDIO]; 302 303 /* 304 * No separate statclock on the IXP12x0. 305 */ 306 imask[IPL_STATCLOCK] |= imask[IPL_CLOCK]; 307 pci_imask[IPL_STATCLOCK] |= pci_imask[IPL_CLOCK]; 308 309 /* 310 * splhigh() must block "everything". 311 */ 312 imask[IPL_HIGH] |= imask[IPL_STATCLOCK]; 313 pci_imask[IPL_HIGH] |= pci_imask[IPL_STATCLOCK]; 314 315 /* 316 * XXX We need serial drivers to run at the absolute highest priority 317 * in order to avoid overruns, so serial > high. 318 */ 319 imask[IPL_SERIAL] |= imask[IPL_HIGH]; 320 pci_imask[IPL_SERIAL] |= pci_imask[IPL_HIGH]; 321 322 /* 323 * Now compute which IRQs must be blocked when servicing any 324 * given IRQ. 325 */ 326 for (irq = 0; irq < NIRQ; irq++) { 327 int irqs; 328 int pci_irqs; 329 330 if (irq < SYS_NIRQ) { 331 irqs = (1U << irq); 332 pci_irqs = 0; 333 } else { 334 irqs = 0; 335 pci_irqs = (1U << (irq - SYS_NIRQ)); 336 } 337 iq = &intrq[irq]; 338 if (TAILQ_FIRST(&iq->iq_list) != NULL) 339 ixp12x0_enable_irq(irq); 340 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 341 ih = TAILQ_NEXT(ih, ih_list)) { 342 irqs |= imask[ih->ih_ipl]; 343 pci_irqs |= pci_imask[ih->ih_ipl]; 344 } 345 iq->iq_mask = irqs; 346 iq->iq_pci_mask = pci_irqs; 347 } 348 } 349 350 static void 351 ixp12x0_do_pending(void) 352 { 353 static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED; 354 int new; 355 u_int oldirqstate; 356 357 if (__cpu_simple_lock_try(&processing) == 0) 358 return; 359 360 new = curcpl(); 361 362 oldirqstate = disable_interrupts(I32_bit); 363 364 #define DO_SOFTINT(si) \ 365 if ((ipending & ~imask[new]) & SI_TO_IRQBIT(si)) { \ 366 ipending &= ~SI_TO_IRQBIT(si); \ 367 set_curcpl(si_to_ipl[(si)]); \ 368 restore_interrupts(oldirqstate); \ 369 softintr_dispatch(si); \ 370 oldirqstate = disable_interrupts(I32_bit); \ 371 set_curcpl(new); \ 372 } 373 374 DO_SOFTINT(SI_SOFTSERIAL); 375 DO_SOFTINT(SI_SOFTNET); 376 DO_SOFTINT(SI_SOFTCLOCK); 377 DO_SOFTINT(SI_SOFT); 378 379 __cpu_simple_unlock(&processing); 380 381 restore_interrupts(oldirqstate); 382 } 383 384 inline void 385 splx(int new) 386 { 387 int old; 388 u_int oldirqstate; 389 390 oldirqstate = disable_interrupts(I32_bit); 391 old = curcpl(); 392 set_curcpl(new); 393 if (new != hardware_spl_level) { 394 hardware_spl_level = new; 395 ixp12x0_set_intrmask(imask[new], pci_imask[new]); 396 } 397 restore_interrupts(oldirqstate); 398 399 /* If there are software interrupts to process, do it. */ 400 if ((ipending & INT_SWMASK) & ~imask[new]) 401 ixp12x0_do_pending(); 402 } 403 404 int 405 _splraise(int ipl) 406 { 407 int old; 408 u_int oldirqstate; 409 410 oldirqstate = disable_interrupts(I32_bit); 411 old = curcpl(); 412 set_curcpl(ipl); 413 restore_interrupts(oldirqstate); 414 return (old); 415 } 416 417 int 418 _spllower(int ipl) 419 { 420 int old = curcpl(); 421 422 if (old <= ipl) 423 return (old); 424 splx(ipl); 425 return (old); 426 } 427 428 void 429 _setsoftintr(int si) 430 { 431 u_int oldirqstate; 432 433 oldirqstate = disable_interrupts(I32_bit); 434 ipending |= SI_TO_IRQBIT(si); 435 restore_interrupts(oldirqstate); 436 437 /* Process unmasked pending soft interrupts. */ 438 if ((ipending & INT_SWMASK) & ~imask[curcpl()]) 439 ixp12x0_do_pending(); 440 } 441 442 /* 443 * ixp12x0_intr_init: 444 * 445 * Initialize the rest of the interrupt subsystem, making it 446 * ready to handle interrupts from devices. 447 */ 448 void 449 ixp12x0_intr_init(void) 450 { 451 struct intrq *iq; 452 int i; 453 454 intr_enabled = 0; 455 pci_intr_enabled = 0; 456 457 for (i = 0; i < NIRQ; i++) { 458 iq = &intrq[i]; 459 TAILQ_INIT(&iq->iq_list); 460 461 sprintf(iq->iq_name, "ipl %d", i); 462 evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 463 NULL, "ixpintr", iq->iq_name); 464 } 465 curcpu()->ci_intr_depth = 0; 466 curcpu()->ci_cpl = 0; 467 hardware_spl_level = 0; 468 469 ixp12x0_intr_calculate_masks(); 470 471 /* Enable IRQs (don't yet use FIQs). */ 472 enable_interrupts(I32_bit); 473 } 474 475 void * 476 ixp12x0_intr_establish(int irq, int ipl, int (*ih_func)(void *), void *arg) 477 { 478 struct intrq* iq; 479 struct intrhand* ih; 480 u_int oldirqstate; 481 #ifdef DEBUG 482 printf("ixp12x0_intr_establish(irq=%d, ipl=%d, ih_func=%08x, arg=%08x)\n", 483 irq, ipl, (u_int32_t) ih_func, (u_int32_t) arg); 484 #endif 485 if (irq < 0 || irq > NIRQ) 486 panic("ixp12x0_intr_establish: IRQ %d out of range", ipl); 487 if (ipl < 0 || ipl > NIPL) 488 panic("ixp12x0_intr_establish: IPL %d out of range", ipl); 489 490 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 491 if (ih == NULL) 492 return (NULL); 493 494 ih->ih_func = ih_func; 495 ih->ih_arg = arg; 496 ih->ih_irq = irq; 497 ih->ih_ipl = ipl; 498 499 iq = &intrq[irq]; 500 iq->iq_ist = IST_LEVEL; 501 502 oldirqstate = disable_interrupts(I32_bit); 503 TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 504 ixp12x0_intr_calculate_masks(); 505 restore_interrupts(oldirqstate); 506 507 return (ih); 508 } 509 510 void 511 ixp12x0_intr_disestablish(void *cookie) 512 { 513 struct intrhand* ih = cookie; 514 struct intrq* iq = &intrq[ih->ih_ipl]; 515 u_int oldirqstate; 516 517 oldirqstate = disable_interrupts(I32_bit); 518 TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 519 ixp12x0_intr_calculate_masks(); 520 restore_interrupts(oldirqstate); 521 } 522 523 void 524 ixp12x0_intr_dispatch(struct irqframe *frame) 525 { 526 struct intrq* iq; 527 struct intrhand* ih; 528 u_int oldirqstate; 529 int pcpl; 530 u_int32_t hwpend; 531 u_int32_t pci_hwpend; 532 int irq; 533 u_int32_t ibit; 534 535 pcpl = curcpl(); 536 537 hwpend = ixp12x0_irq_read(); 538 pci_hwpend = ixp12x0_pci_irq_read(); 539 540 hardware_spl_level = pcpl; 541 ixp12x0_set_intrmask(imask[pcpl] | hwpend, 542 pci_imask[pcpl] | pci_hwpend); 543 544 hwpend &= ~imask[pcpl]; 545 pci_hwpend &= ~pci_imask[pcpl]; 546 547 while (hwpend) { 548 irq = ffs(hwpend) - 1; 549 ibit = (1U << irq); 550 551 iq = &intrq[irq]; 552 iq->iq_ev.ev_count++; 553 uvmexp.intrs++; 554 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 555 ih = TAILQ_NEXT(ih, ih_list)) { 556 int ipl; 557 558 curcpu()->ci_cpl = ipl = ih->ih_ipl; 559 oldirqstate = enable_interrupts(I32_bit); 560 (void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 561 restore_interrupts(oldirqstate); 562 hwpend &= ~ibit; 563 } 564 } 565 while (pci_hwpend) { 566 irq = ffs(pci_hwpend) - 1; 567 ibit = (1U << irq); 568 569 iq = &intrq[irq + SYS_NIRQ]; 570 iq->iq_ev.ev_count++; 571 uvmexp.intrs++; 572 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 573 ih = TAILQ_NEXT(ih, ih_list)) { 574 int ipl; 575 576 curcpu()->ci_cpl = ipl = ih->ih_ipl; 577 oldirqstate = enable_interrupts(I32_bit); 578 (void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 579 restore_interrupts(oldirqstate); 580 pci_hwpend &= ~ibit; 581 } 582 } 583 584 curcpu()->ci_cpl = pcpl; 585 hardware_spl_level = pcpl; 586 ixp12x0_set_intrmask(imask[pcpl], pci_imask[pcpl]); 587 588 /* Check for pendings soft intrs. */ 589 if ((ipending & INT_SWMASK) & ~imask[pcpl]) { 590 oldirqstate = enable_interrupts(I32_bit); 591 ixp12x0_do_pending(); 592 restore_interrupts(oldirqstate); 593 } 594 } 595
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