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ixp12x0_intr.c revision 1.19.20.1 
      1 /* $NetBSD: ixp12x0_intr.c,v 1.19.20.1 2010/08/17 06:44:04 uebayasi Exp $ */
      2 
      3 /*
      4  * Copyright (c) 2002 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Ichiro FUKUHARA and Naoto Shimazaki.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #include <sys/cdefs.h>
     33 __KERNEL_RCSID(0, "$NetBSD: ixp12x0_intr.c,v 1.19.20.1 2010/08/17 06:44:04 uebayasi Exp $");
     34 
     35 /*
     36  * Interrupt support for the Intel ixp12x0
     37  */
     38 
     39 #include <sys/param.h>
     40 #include <sys/systm.h>
     41 #include <sys/malloc.h>
     42 #include <sys/simplelock.h>
     43 #include <sys/termios.h>
     44 
     45 #include <uvm/uvm_extern.h>
     46 
     47 #include <machine/bus.h>
     48 #include <machine/intr.h>
     49 
     50 #include <arm/cpufunc.h>
     51 
     52 #include <arm/ixp12x0/ixp12x0reg.h>
     53 #include <arm/ixp12x0/ixp12x0var.h>
     54 #include <arm/ixp12x0/ixp12x0_comreg.h>
     55 #include <arm/ixp12x0/ixp12x0_comvar.h>
     56 #include <arm/ixp12x0/ixp12x0_pcireg.h>
     57 
     58 
     59 extern u_int32_t	ixpcom_cr;	/* current cr from *_com.c */
     60 extern u_int32_t	ixpcom_imask;	/* tell mask to *_com.c */
     61 
     62 /* Interrupt handler queues. */
     63 struct intrq intrq[NIRQ];
     64 
     65 /* Interrupts to mask at each level. */
     66 static u_int32_t imask[NIPL];
     67 static u_int32_t pci_imask[NIPL];
     68 
     69 /* Current interrupt priority level. */
     70 volatile int hardware_spl_level;
     71 
     72 /* Software copy of the IRQs we have enabled. */
     73 volatile u_int32_t intr_enabled;
     74 volatile u_int32_t pci_intr_enabled;
     75 
     76 /* Interrupts pending. */
     77 static volatile int ipending;
     78 
     79 void	ixp12x0_intr_dispatch(struct irqframe *frame);
     80 
     81 #define IXPREG(reg)	*((volatile u_int32_t*) (reg))
     82 
     83 static inline u_int32_t
     84 ixp12x0_irq_read(void)
     85 {
     86 	return IXPREG(IXP12X0_IRQ_VBASE) & IXP12X0_INTR_MASK;
     87 }
     88 
     89 static inline u_int32_t
     90 ixp12x0_pci_irq_read(void)
     91 {
     92 	return IXPREG(IXPPCI_IRQ_STATUS);
     93 }
     94 
     95 static void
     96 ixp12x0_enable_uart_irq(void)
     97 {
     98 	ixpcom_imask = 0;
     99 	if (ixpcom_sc)
    100 		bus_space_write_4(ixpcom_sc->sc_iot, ixpcom_sc->sc_ioh,
    101 				  IXPCOM_CR, ixpcom_cr & ~ixpcom_imask);
    102 }
    103 
    104 static void
    105 ixp12x0_disable_uart_irq(void)
    106 {
    107 	ixpcom_imask = CR_RIE | CR_XIE;
    108 	if (ixpcom_sc)
    109 		bus_space_write_4(ixpcom_sc->sc_iot, ixpcom_sc->sc_ioh,
    110 				  IXPCOM_CR, ixpcom_cr & ~ixpcom_imask);
    111 }
    112 
    113 static void
    114 ixp12x0_set_intrmask(u_int32_t irqs, u_int32_t pci_irqs)
    115 {
    116 	if (irqs & (1U << IXP12X0_INTR_UART)) {
    117 		ixp12x0_disable_uart_irq();
    118 	} else {
    119 		ixp12x0_enable_uart_irq();
    120 	}
    121 	IXPREG(IXPPCI_IRQ_ENABLE_CLEAR) = pci_irqs;
    122 	IXPREG(IXPPCI_IRQ_ENABLE_SET) = pci_intr_enabled & ~pci_irqs;
    123 }
    124 
    125 static void
    126 ixp12x0_enable_irq(int irq)
    127 {
    128 	if (irq < SYS_NIRQ) {
    129 		intr_enabled |= (1U << irq);
    130 		switch (irq) {
    131 		case IXP12X0_INTR_UART:
    132 			ixp12x0_enable_uart_irq();
    133 			break;
    134 
    135 		case IXP12X0_INTR_PCI:
    136 			/* nothing to do */
    137 			break;
    138 		default:
    139 			panic("enable_irq:bad IRQ %d", irq);
    140 		}
    141 	} else {
    142 		pci_intr_enabled |= (1U << (irq - SYS_NIRQ));
    143 		IXPREG(IXPPCI_IRQ_ENABLE_SET) = (1U << (irq - SYS_NIRQ));
    144 	}
    145 }
    146 
    147 static inline void
    148 ixp12x0_disable_irq(int irq)
    149 {
    150 	if (irq < SYS_NIRQ) {
    151 		intr_enabled ^= ~(1U << irq);
    152 		switch (irq) {
    153 		case IXP12X0_INTR_UART:
    154 			ixp12x0_disable_uart_irq();
    155 			break;
    156 
    157 		case IXP12X0_INTR_PCI:
    158 			/* nothing to do */
    159 			break;
    160 		default:
    161 			/* nothing to do */
    162 			break;
    163 		}
    164 	} else {
    165 		pci_intr_enabled &= ~(1U << (irq - SYS_NIRQ));
    166 		IXPREG(IXPPCI_IRQ_ENABLE_CLEAR) = (1U << (irq - SYS_NIRQ));
    167 	}
    168 }
    169 
    170 /*
    171  * NOTE: This routine must be called with interrupts disabled in the CPSR.
    172  */
    173 static void
    174 ixp12x0_intr_calculate_masks(void)
    175 {
    176 	struct intrq *iq;
    177 	struct intrhand *ih;
    178 	int irq, ipl;
    179 
    180 	/* First, figure out which IPLs each IRQ has. */
    181 	for (irq = 0; irq < NIRQ; irq++) {
    182 		int levels = 0;
    183 		iq = &intrq[irq];
    184 		ixp12x0_disable_irq(irq);
    185 		for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
    186 		     ih = TAILQ_NEXT(ih, ih_list))
    187 			levels |= (1U << ih->ih_ipl);
    188 		iq->iq_levels = levels;
    189 	}
    190 
    191 	/* Next, figure out which IRQs are used by each IPL. */
    192 	for (ipl = 0; ipl < NIPL; ipl++) {
    193 		int irqs = 0;
    194 		int pci_irqs = 0;
    195 		for (irq = 0; irq < SYS_NIRQ; irq++) {
    196 			if (intrq[irq].iq_levels & (1U << ipl))
    197 				irqs |= (1U << irq);
    198 		}
    199 		imask[ipl] = irqs;
    200 		for (irq = 0; irq < SYS_NIRQ; irq++) {
    201 			if (intrq[irq + SYS_NIRQ].iq_levels & (1U << ipl))
    202 				pci_irqs |= (1U << irq);
    203 		}
    204 		pci_imask[ipl] = pci_irqs;
    205 	}
    206 
    207 	KASSERT(imask[IPL_NONE] == 0);
    208 	KASSERT(pci_imask[IPL_NONE] == 0);
    209 	KASSERT(imask[IPL_SOFTCLOCK] == 0);
    210 	KASSERT(pci_imask[IPL_SOFTCLOCK] == 0);
    211 	KASSERT(imask[IPL_SOFTBIO] == 0);
    212 	KASSERT(pci_imask[IPL_SOFTBIO] == 0);
    213 	KASSERT(imask[IPL_SOFTNET] == 0);
    214 	KASSERT(pci_imask[IPL_SOFTNET] == 0);
    215 	KASSERT(imask[IPL_SOFTSERIAL] == 0);
    216 	KASSERT(pci_imask[IPL_SOFTSERIAL] == 0);
    217 
    218 	KASSERT(imask[IPL_VM] != 0);
    219 	KASSERT(pci_imask[IPL_VM] != 0);
    220 
    221 	/*
    222 	 * splsched() must block anything that uses the scheduler.
    223 	 */
    224 	imask[IPL_SCHED] |= imask[IPL_VM];
    225 	pci_imask[IPL_SCHED] |= pci_imask[IPL_VM];
    226 
    227 	/*
    228 	 * splhigh() must block "everything".
    229 	 */
    230 	imask[IPL_HIGH] |= imask[IPL_SCHED];
    231 	pci_imask[IPL_HIGH] |= pci_imask[IPL_SCHED];
    232 
    233 	/*
    234 	 * Now compute which IRQs must be blocked when servicing any
    235 	 * given IRQ.
    236 	 */
    237 	for (irq = 0; irq < NIRQ; irq++) {
    238 		int	irqs;
    239 		int	pci_irqs;
    240 
    241 		if (irq < SYS_NIRQ) {
    242 			irqs = (1U << irq);
    243 			pci_irqs = 0;
    244 		} else {
    245 			irqs = 0;
    246 			pci_irqs = (1U << (irq - SYS_NIRQ));
    247 		}
    248 		iq = &intrq[irq];
    249 		if (TAILQ_FIRST(&iq->iq_list) != NULL)
    250 			ixp12x0_enable_irq(irq);
    251 		for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
    252 		     ih = TAILQ_NEXT(ih, ih_list)) {
    253 			irqs |= imask[ih->ih_ipl];
    254 			pci_irqs |= pci_imask[ih->ih_ipl];
    255 		}
    256 		iq->iq_mask = irqs;
    257 		iq->iq_pci_mask = pci_irqs;
    258 	}
    259 }
    260 
    261 inline void
    262 splx(int new)
    263 {
    264 	int	old;
    265 	u_int	oldirqstate;
    266 
    267 	oldirqstate = disable_interrupts(I32_bit);
    268 	old = curcpl();
    269 	set_curcpl(new);
    270 	if (new != hardware_spl_level) {
    271 		hardware_spl_level = new;
    272 		ixp12x0_set_intrmask(imask[new], pci_imask[new]);
    273 	}
    274 	restore_interrupts(oldirqstate);
    275 
    276 #ifdef __HAVE_FAST_SOFTINTS
    277 	cpu_dosoftints();
    278 #endif
    279 }
    280 
    281 int
    282 _splraise(int ipl)
    283 {
    284 	int	old;
    285 	u_int	oldirqstate;
    286 
    287 	oldirqstate = disable_interrupts(I32_bit);
    288 	old = curcpl();
    289 	set_curcpl(ipl);
    290 	restore_interrupts(oldirqstate);
    291 	return (old);
    292 }
    293 
    294 int
    295 _spllower(int ipl)
    296 {
    297 	int	old = curcpl();
    298 
    299 	if (old <= ipl)
    300 		return (old);
    301 	splx(ipl);
    302 	return (old);
    303 }
    304 
    305 /*
    306  * ixp12x0_intr_init:
    307  *
    308  *	Initialize the rest of the interrupt subsystem, making it
    309  *	ready to handle interrupts from devices.
    310  */
    311 void
    312 ixp12x0_intr_init(void)
    313 {
    314 	struct intrq *iq;
    315 	int i;
    316 
    317 	intr_enabled = 0;
    318 	pci_intr_enabled = 0;
    319 
    320 	for (i = 0; i < NIRQ; i++) {
    321 		iq = &intrq[i];
    322 		TAILQ_INIT(&iq->iq_list);
    323 
    324 		sprintf(iq->iq_name, "ipl %d", i);
    325 		evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR,
    326 				     NULL, "ixpintr", iq->iq_name);
    327 	}
    328 	curcpu()->ci_intr_depth = 0;
    329 	curcpu()->ci_cpl = 0;
    330 	hardware_spl_level = 0;
    331 
    332 	ixp12x0_intr_calculate_masks();
    333 
    334 	/* Enable IRQs (don't yet use FIQs). */
    335 	enable_interrupts(I32_bit);
    336 }
    337 
    338 void *
    339 ixp12x0_intr_establish(int irq, int ipl, int (*ih_func)(void *), void *arg)
    340 {
    341 	struct intrq*		iq;
    342 	struct intrhand*	ih;
    343 	u_int			oldirqstate;
    344 #ifdef DEBUG
    345 	printf("ixp12x0_intr_establish(irq=%d, ipl=%d, ih_func=%08x, arg=%08x)\n",
    346 	       irq, ipl, (u_int32_t) ih_func, (u_int32_t) arg);
    347 #endif
    348 	if (irq < 0 || irq > NIRQ)
    349 		panic("ixp12x0_intr_establish: IRQ %d out of range", ipl);
    350 	if (ipl < 0 || ipl > NIPL)
    351 		panic("ixp12x0_intr_establish: IPL %d out of range", ipl);
    352 
    353 	ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT);
    354 	if (ih == NULL)
    355 		return (NULL);
    356 
    357 	ih->ih_func = ih_func;
    358 	ih->ih_arg = arg;
    359 	ih->ih_irq = irq;
    360 	ih->ih_ipl = ipl;
    361 
    362 	iq = &intrq[irq];
    363 	iq->iq_ist = IST_LEVEL;
    364 
    365 	oldirqstate = disable_interrupts(I32_bit);
    366 	TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list);
    367 	ixp12x0_intr_calculate_masks();
    368 	restore_interrupts(oldirqstate);
    369 
    370 	return (ih);
    371 }
    372 
    373 void
    374 ixp12x0_intr_disestablish(void *cookie)
    375 {
    376 	struct intrhand*	ih = cookie;
    377 	struct intrq*		iq = &intrq[ih->ih_ipl];
    378 	u_int			oldirqstate;
    379 
    380 	oldirqstate = disable_interrupts(I32_bit);
    381 	TAILQ_REMOVE(&iq->iq_list, ih, ih_list);
    382 	ixp12x0_intr_calculate_masks();
    383 	restore_interrupts(oldirqstate);
    384 }
    385 
    386 void
    387 ixp12x0_intr_dispatch(struct irqframe *frame)
    388 {
    389 	struct intrq*		iq;
    390 	struct intrhand*	ih;
    391 	struct cpu_info* const	ci = curcpu();
    392 	const int		ppl = ci->ci_cpl;
    393 	u_int			oldirqstate;
    394 	u_int32_t		hwpend;
    395 	u_int32_t		pci_hwpend;
    396 	int			irq;
    397 	u_int32_t		ibit;
    398 
    399 
    400 	hwpend = ixp12x0_irq_read();
    401 	pci_hwpend = ixp12x0_pci_irq_read();
    402 
    403 	hardware_spl_level = ppl;
    404 	ixp12x0_set_intrmask(imask[ppl] | hwpend, pci_imask[ppl] | pci_hwpend);
    405 
    406 	hwpend &= ~imask[ppl];
    407 	pci_hwpend &= ~pci_imask[ppl];
    408 
    409 	while (hwpend) {
    410 		irq = ffs(hwpend) - 1;
    411 		ibit = (1U << irq);
    412 
    413 		iq = &intrq[irq];
    414 		iq->iq_ev.ev_count++;
    415 		uvmexp.intrs++;
    416 		TAILQ_FOREACH(ih, &iq->iq_list, ih_list) {
    417 			ci->ci_cpl = ih->ih_ipl;
    418 			oldirqstate = enable_interrupts(I32_bit);
    419 			(void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame);
    420 			restore_interrupts(oldirqstate);
    421 			hwpend &= ~ibit;
    422 		}
    423 	}
    424 	while (pci_hwpend) {
    425 		irq = ffs(pci_hwpend) - 1;
    426 		ibit = (1U << irq);
    427 
    428 		iq = &intrq[irq + SYS_NIRQ];
    429 		iq->iq_ev.ev_count++;
    430 		uvmexp.intrs++;
    431 		TAILQ_FOREACH(ih, &iq->iq_list, ih_list) {
    432 			ci->ci_cpl = ih->ih_ipl;
    433 			oldirqstate = enable_interrupts(I32_bit);
    434 			(void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame);
    435 			restore_interrupts(oldirqstate);
    436 		}
    437 		pci_hwpend &= ~ibit;
    438 	}
    439 
    440 	ci->ci_cpl = ppl;
    441 	hardware_spl_level = ppl;
    442 	ixp12x0_set_intrmask(imask[ppl], pci_imask[ppl]);
    443 
    444 #ifdef __HAVE_FAST_SOFTINTS
    445 	cpu_dosoftints();
    446 #endif
    447 }
    448