ixp12x0_intr.c revision 1.9
1 /* $NetBSD: ixp12x0_intr.c,v 1.9 2003/07/13 08:56:16 igy Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Ichiro FUKUHARA and Naoto Shimazaki. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: ixp12x0_intr.c,v 1.9 2003/07/13 08:56:16 igy Exp $"); 41 42 /* 43 * Interrupt support for the Intel ixp12x0 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 #include <sys/termios.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include <machine/bus.h> 54 #include <machine/intr.h> 55 56 #include <arm/cpufunc.h> 57 58 #include <arm/ixp12x0/ixp12x0reg.h> 59 #include <arm/ixp12x0/ixp12x0var.h> 60 #include <arm/ixp12x0/ixp12x0_comreg.h> 61 #include <arm/ixp12x0/ixp12x0_comvar.h> 62 #include <arm/ixp12x0/ixp12x0_pcireg.h> 63 64 extern u_int32_t ixpcom_cr; /* current cr from *_com.c */ 65 extern u_int32_t ixpcom_imask; /* tell mask to *_com.c */ 66 67 /* Interrupt handler queues. */ 68 struct intrq intrq[NIRQ]; 69 70 /* Interrupts to mask at each level. */ 71 static u_int32_t imask[NIPL]; 72 static u_int32_t pci_imask[NIPL]; 73 74 /* Current interrupt priority level. */ 75 __volatile int current_spl_level; 76 77 /* Software copy of the IRQs we have enabled. */ 78 __volatile u_int32_t intr_enabled; 79 __volatile u_int32_t pci_intr_enabled; 80 81 /* Interrupts pending. */ 82 static __volatile int ipending; 83 84 /* 85 * Map a software interrupt queue index (to the unused bits in the 86 * ICU registers -- XXX will need to revisit this if those bits are 87 * ever used in future steppings). 88 */ 89 static const u_int32_t si_to_irqbit[SI_NQUEUES] = { 90 IXP12X0_INTR_bit30, /* SI_SOFT */ 91 IXP12X0_INTR_bit29, /* SI_SOFTCLOCK */ 92 IXP12X0_INTR_bit28, /* SI_SOFTNET */ 93 IXP12X0_INTR_bit27, /* SI_SOFTSERIAL */ 94 }; 95 96 #define INT_SWMASK \ 97 ((1U << IXP12X0_INTR_bit30) | (1U << IXP12X0_INTR_bit29) | \ 98 (1U << IXP12X0_INTR_bit28) | (1U << IXP12X0_INTR_bit27)) 99 100 #define SI_TO_IRQBIT(si) (1U << si_to_irqbit[(si)]) 101 102 /* 103 * Map a software interrupt queue to an interrupt priority level. 104 */ 105 static const int si_to_ipl[SI_NQUEUES] = { 106 IPL_SOFT, /* SI_SOFT */ 107 IPL_SOFTCLOCK, /* SI_SOFTCLOCK */ 108 IPL_SOFTNET, /* SI_SOFTNET */ 109 IPL_SOFTSERIAL, /* SI_SOFTSERIAL */ 110 }; 111 112 void ixp12x0_intr_dispatch(struct irqframe *frame); 113 114 #define IXPREG(reg) *((volatile u_int32_t*) (reg)) 115 116 static __inline u_int32_t 117 ixp12x0_irq_read(void) 118 { 119 return IXPREG(IXP12X0_IRQ_VBASE) & IXP12X0_INTR_MASK; 120 } 121 122 static __inline u_int32_t 123 ixp12x0_pci_irq_read(void) 124 { 125 return IXPREG(IXPPCI_IRQ_STATUS); 126 } 127 128 static void 129 ixp12x0_enable_uart_irq(void) 130 { 131 ixpcom_imask = 0; 132 if (ixpcom_sc) 133 bus_space_write_4(ixpcom_sc->sc_iot, ixpcom_sc->sc_ioh, 134 IXPCOM_CR, ixpcom_cr & ~ixpcom_imask); 135 } 136 137 static void 138 ixp12x0_disable_uart_irq(void) 139 { 140 ixpcom_imask = CR_RIE | CR_XIE; 141 if (ixpcom_sc) 142 bus_space_write_4(ixpcom_sc->sc_iot, ixpcom_sc->sc_ioh, 143 IXPCOM_CR, ixpcom_cr & ~ixpcom_imask); 144 } 145 146 static void 147 ixp12x0_set_intrmask(u_int32_t irqs, u_int32_t pci_irqs) 148 { 149 if (irqs & (1U << IXP12X0_INTR_UART)) { 150 ixp12x0_disable_uart_irq(); 151 } else { 152 ixp12x0_enable_uart_irq(); 153 } 154 IXPREG(IXPPCI_IRQ_ENABLE_CLEAR) = pci_irqs; 155 IXPREG(IXPPCI_IRQ_ENABLE_SET) = pci_intr_enabled & ~pci_irqs; 156 } 157 158 static void 159 ixp12x0_enable_irq(int irq) 160 { 161 if (irq < SYS_NIRQ) { 162 intr_enabled |= (1U << irq); 163 switch (irq) { 164 case IXP12X0_INTR_UART: 165 ixp12x0_enable_uart_irq(); 166 break; 167 168 case IXP12X0_INTR_PCI: 169 /* nothing to do */ 170 break; 171 default: 172 panic("enable_irq:bad IRQ %d", irq); 173 } 174 } else { 175 pci_intr_enabled |= (1U << (irq - SYS_NIRQ)); 176 IXPREG(IXPPCI_IRQ_ENABLE_SET) = (1U << (irq - SYS_NIRQ)); 177 } 178 } 179 180 static __inline void 181 ixp12x0_disable_irq(int irq) 182 { 183 if (irq < SYS_NIRQ) { 184 intr_enabled ^= ~(1U << irq); 185 switch (irq) { 186 case IXP12X0_INTR_UART: 187 ixp12x0_disable_uart_irq(); 188 break; 189 190 case IXP12X0_INTR_PCI: 191 /* nothing to do */ 192 break; 193 default: 194 /* nothing to do */ 195 } 196 } else { 197 pci_intr_enabled &= ~(1U << (irq - SYS_NIRQ)); 198 IXPREG(IXPPCI_IRQ_ENABLE_CLEAR) = (1U << (irq - SYS_NIRQ)); 199 } 200 } 201 202 /* 203 * NOTE: This routine must be called with interrupts disabled in the CPSR. 204 */ 205 static void 206 ixp12x0_intr_calculate_masks(void) 207 { 208 struct intrq *iq; 209 struct intrhand *ih; 210 int irq, ipl; 211 212 /* First, figure out which IPLs each IRQ has. */ 213 for (irq = 0; irq < NIRQ; irq++) { 214 int levels = 0; 215 iq = &intrq[irq]; 216 ixp12x0_disable_irq(irq); 217 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 218 ih = TAILQ_NEXT(ih, ih_list)) 219 levels |= (1U << ih->ih_ipl); 220 iq->iq_levels = levels; 221 } 222 223 /* Next, figure out which IRQs are used by each IPL. */ 224 for (ipl = 0; ipl < NIPL; ipl++) { 225 int irqs = 0; 226 int pci_irqs = 0; 227 for (irq = 0; irq < SYS_NIRQ; irq++) { 228 if (intrq[irq].iq_levels & (1U << ipl)) 229 irqs |= (1U << irq); 230 } 231 imask[ipl] = irqs; 232 for (irq = 0; irq < SYS_NIRQ; irq++) { 233 if (intrq[irq + SYS_NIRQ].iq_levels & (1U << ipl)) 234 pci_irqs |= (1U << irq); 235 } 236 pci_imask[ipl] = pci_irqs; 237 } 238 239 imask[IPL_NONE] = 0; 240 pci_imask[IPL_NONE] = 0; 241 242 /* 243 * Initialize the soft interrupt masks to block themselves. 244 */ 245 imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFT); 246 imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK); 247 imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET); 248 imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL); 249 250 /* 251 * splsoftclock() is the only interface that users of the 252 * generic software interrupt facility have to block their 253 * soft intrs, so splsoftclock() must also block IPL_SOFT. 254 */ 255 imask[IPL_SOFTCLOCK] |= imask[IPL_SOFT]; 256 pci_imask[IPL_SOFTCLOCK] |= pci_imask[IPL_SOFT]; 257 258 /* 259 * splsoftnet() must also block splsoftclock(), since we don't 260 * want timer-driven network events to occur while we're 261 * processing incoming packets. 262 */ 263 imask[IPL_SOFTNET] |= imask[IPL_SOFTCLOCK]; 264 pci_imask[IPL_SOFTNET] |= pci_imask[IPL_SOFTCLOCK]; 265 266 /* 267 * Enforce a heirarchy that gives "slow" device (or devices with 268 * limited input buffer space/"real-time" requirements) a better 269 * chance at not dropping data. 270 */ 271 imask[IPL_BIO] |= imask[IPL_SOFTNET]; 272 pci_imask[IPL_BIO] |= pci_imask[IPL_SOFTNET]; 273 imask[IPL_NET] |= imask[IPL_BIO]; 274 pci_imask[IPL_NET] |= pci_imask[IPL_BIO]; 275 imask[IPL_SOFTSERIAL] |= imask[IPL_NET]; 276 pci_imask[IPL_SOFTSERIAL] |= pci_imask[IPL_NET]; 277 imask[IPL_TTY] |= imask[IPL_SOFTSERIAL]; 278 pci_imask[IPL_TTY] |= pci_imask[IPL_SOFTSERIAL]; 279 280 /* 281 * splvm() blocks all interrupts that use the kernel memory 282 * allocation facilities. 283 */ 284 imask[IPL_VM] |= imask[IPL_TTY]; 285 pci_imask[IPL_VM] |= pci_imask[IPL_TTY]; 286 287 /* 288 * Audio devices are not allowed to perform memory allocation 289 * in their interrupt routines, and they have fairly "real-time" 290 * requirements, so give them a high interrupt priority. 291 */ 292 imask[IPL_AUDIO] |= imask[IPL_VM]; 293 pci_imask[IPL_AUDIO] |= pci_imask[IPL_VM]; 294 295 /* 296 * splclock() must block anything that uses the scheduler. 297 */ 298 imask[IPL_CLOCK] |= imask[IPL_AUDIO]; 299 pci_imask[IPL_CLOCK] |= pci_imask[IPL_AUDIO]; 300 301 /* 302 * No separate statclock on the IXP12x0. 303 */ 304 imask[IPL_STATCLOCK] |= imask[IPL_CLOCK]; 305 pci_imask[IPL_STATCLOCK] |= pci_imask[IPL_CLOCK]; 306 307 /* 308 * splhigh() must block "everything". 309 */ 310 imask[IPL_HIGH] |= imask[IPL_STATCLOCK]; 311 pci_imask[IPL_HIGH] |= pci_imask[IPL_STATCLOCK]; 312 313 /* 314 * XXX We need serial drivers to run at the absolute highest priority 315 * in order to avoid overruns, so serial > high. 316 */ 317 imask[IPL_SERIAL] |= imask[IPL_HIGH]; 318 pci_imask[IPL_SERIAL] |= pci_imask[IPL_HIGH]; 319 320 /* 321 * Now compute which IRQs must be blocked when servicing any 322 * given IRQ. 323 */ 324 for (irq = 0; irq < NIRQ; irq++) { 325 int irqs; 326 int pci_irqs; 327 328 if (irq < SYS_NIRQ) { 329 irqs = (1U << irq); 330 pci_irqs = 0; 331 } else { 332 irqs = 0; 333 pci_irqs = (1U << (irq - SYS_NIRQ)); 334 } 335 iq = &intrq[irq]; 336 if (TAILQ_FIRST(&iq->iq_list) != NULL) 337 ixp12x0_enable_irq(irq); 338 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 339 ih = TAILQ_NEXT(ih, ih_list)) { 340 irqs |= imask[ih->ih_ipl]; 341 pci_irqs |= pci_imask[ih->ih_ipl]; 342 } 343 iq->iq_mask = irqs; 344 iq->iq_pci_mask = pci_irqs; 345 } 346 } 347 348 static void 349 ixp12x0_do_pending(void) 350 { 351 static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED; 352 int new; 353 u_int oldirqstate; 354 355 if (__cpu_simple_lock_try(&processing) == 0) 356 return; 357 358 new = current_spl_level; 359 360 oldirqstate = disable_interrupts(I32_bit); 361 362 #define DO_SOFTINT(si) \ 363 if ((ipending & ~imask[new]) & SI_TO_IRQBIT(si)) { \ 364 ipending &= ~SI_TO_IRQBIT(si); \ 365 current_spl_level = si_to_ipl[(si)]; \ 366 restore_interrupts(oldirqstate); \ 367 softintr_dispatch(si); \ 368 oldirqstate = disable_interrupts(I32_bit); \ 369 current_spl_level = new; \ 370 } 371 372 DO_SOFTINT(SI_SOFTSERIAL); 373 DO_SOFTINT(SI_SOFTNET); 374 DO_SOFTINT(SI_SOFTCLOCK); 375 DO_SOFTINT(SI_SOFT); 376 377 __cpu_simple_unlock(&processing); 378 379 restore_interrupts(oldirqstate); 380 } 381 382 __inline void 383 splx(int new) 384 { 385 int old; 386 u_int oldirqstate; 387 388 if (current_spl_level == new) 389 return; 390 oldirqstate = disable_interrupts(I32_bit); 391 old = current_spl_level; 392 current_spl_level = new; 393 ixp12x0_set_intrmask(imask[new], pci_imask[new]); 394 restore_interrupts(oldirqstate); 395 396 /* If there are software interrupts to process, do it. */ 397 if ((ipending & INT_SWMASK) & ~imask[new]) 398 ixp12x0_do_pending(); 399 } 400 401 int 402 _splraise(int ipl) 403 { 404 int old = current_spl_level; 405 406 if (old >= ipl) 407 return (old); 408 splx(ipl); 409 return (old); 410 } 411 412 int 413 _spllower(int ipl) 414 { 415 int old = current_spl_level; 416 417 if (old <= ipl) 418 return (old); 419 splx(ipl); 420 return (old); 421 } 422 423 void 424 _setsoftintr(int si) 425 { 426 u_int oldirqstate; 427 428 oldirqstate = disable_interrupts(I32_bit); 429 ipending |= SI_TO_IRQBIT(si); 430 restore_interrupts(oldirqstate); 431 432 /* Process unmasked pending soft interrupts. */ 433 if ((ipending & INT_SWMASK) & ~imask[current_spl_level]) 434 ixp12x0_do_pending(); 435 } 436 437 /* 438 * ixp12x0_intr_init: 439 * 440 * Initialize the rest of the interrupt subsystem, making it 441 * ready to handle interrupts from devices. 442 */ 443 void 444 ixp12x0_intr_init(void) 445 { 446 struct intrq *iq; 447 int i; 448 449 intr_enabled = 0; 450 pci_intr_enabled = 0; 451 452 for (i = 0; i < NIRQ; i++) { 453 iq = &intrq[i]; 454 TAILQ_INIT(&iq->iq_list); 455 456 sprintf(iq->iq_name, "ipl %d", i); 457 evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 458 NULL, "ixpintr", iq->iq_name); 459 } 460 current_intr_depth = 0; 461 current_spl_level = 0; 462 463 ixp12x0_intr_calculate_masks(); 464 465 /* Enable IRQs (don't yet use FIQs). */ 466 enable_interrupts(I32_bit); 467 } 468 469 void * 470 ixp12x0_intr_establish(int irq, int ipl, int (*ih_func)(void *), void *arg) 471 { 472 struct intrq* iq; 473 struct intrhand* ih; 474 u_int oldirqstate; 475 #ifdef DEBUG 476 printf("ixp12x0_intr_establish(irq=%d, ipl=%d, ih_func=%08x, arg=%08x)\n", 477 irq, ipl, (u_int32_t) ih_func, (u_int32_t) arg); 478 #endif 479 if (irq < 0 || irq > NIRQ) 480 panic("ixp12x0_intr_establish: IRQ %d out of range", ipl); 481 if (ipl < 0 || ipl > NIPL) 482 panic("ixp12x0_intr_establish: IPL %d out of range", ipl); 483 484 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 485 if (ih == NULL) 486 return (NULL); 487 488 ih->ih_func = ih_func; 489 ih->ih_arg = arg; 490 ih->ih_irq = irq; 491 ih->ih_ipl = ipl; 492 493 iq = &intrq[irq]; 494 iq->iq_ist = IST_LEVEL; 495 496 oldirqstate = disable_interrupts(I32_bit); 497 TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 498 ixp12x0_intr_calculate_masks(); 499 restore_interrupts(oldirqstate); 500 501 return (ih); 502 } 503 504 void 505 ixp12x0_intr_disestablish(void *cookie) 506 { 507 struct intrhand* ih = cookie; 508 struct intrq* iq = &intrq[ih->ih_ipl]; 509 u_int oldirqstate; 510 511 oldirqstate = disable_interrupts(I32_bit); 512 TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 513 ixp12x0_intr_calculate_masks(); 514 restore_interrupts(oldirqstate); 515 } 516 517 void 518 ixp12x0_intr_dispatch(struct clockframe *frame) 519 { 520 struct intrq* iq; 521 struct intrhand* ih; 522 u_int oldirqstate; 523 int pcpl; 524 u_int32_t hwpend; 525 u_int32_t pci_hwpend; 526 int irq; 527 u_int32_t ibit; 528 529 pcpl = current_spl_level; 530 531 hwpend = ixp12x0_irq_read(); 532 pci_hwpend = ixp12x0_pci_irq_read(); 533 534 while (hwpend) { 535 irq = ffs(hwpend) - 1; 536 ibit = (1U << irq); 537 538 iq = &intrq[irq]; 539 iq->iq_ev.ev_count++; 540 uvmexp.intrs++; 541 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 542 ih = TAILQ_NEXT(ih, ih_list)) { 543 int ipl; 544 current_spl_level = ipl = ih->ih_ipl; 545 ixp12x0_set_intrmask(imask[ipl] | hwpend, 546 pci_imask[ipl] | pci_hwpend); 547 oldirqstate = enable_interrupts(I32_bit); 548 (void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 549 restore_interrupts(oldirqstate); 550 hwpend &= ~ibit; 551 } 552 } 553 while (pci_hwpend) { 554 irq = ffs(pci_hwpend) - 1; 555 ibit = (1U << irq); 556 557 iq = &intrq[irq + SYS_NIRQ]; 558 iq->iq_ev.ev_count++; 559 uvmexp.intrs++; 560 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 561 ih = TAILQ_NEXT(ih, ih_list)) { 562 int ipl; 563 564 current_spl_level = ipl = ih->ih_ipl; 565 ixp12x0_set_intrmask(imask[ipl] | hwpend, 566 pci_imask[ipl] | pci_hwpend); 567 oldirqstate = enable_interrupts(I32_bit); 568 (void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 569 restore_interrupts(oldirqstate); 570 pci_hwpend &= ~ibit; 571 } 572 } 573 574 splx(pcpl); 575 576 /* Check for pendings soft intrs. */ 577 if ((ipending & INT_SWMASK) & ~imask[pcpl]) { 578 oldirqstate = enable_interrupts(I32_bit); 579 ixp12x0_do_pending(); 580 restore_interrupts(oldirqstate); 581 } 582 } 583
Indexes created Tue Oct 28 12:10:06 GMT 2025