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ixp12x0_pci.c revision 1.10
      1  1.10      dsl /* $NetBSD: ixp12x0_pci.c,v 1.10 2009/03/14 21:04:05 dsl Exp $ */
      2   1.1   ichiro /*
      3   1.4   ichiro  * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc.
      4   1.1   ichiro  * All rights reserved.
      5   1.1   ichiro  *
      6   1.1   ichiro  * This code is derived from software contributed to The NetBSD Foundation
      7   1.1   ichiro  * by Ichiro FUKUHARA and Naoto Shimazaki.
      8   1.1   ichiro  *
      9   1.1   ichiro  * Redistribution and use in source and binary forms, with or without
     10   1.1   ichiro  * modification, are permitted provided that the following conditions
     11   1.1   ichiro  * are met:
     12   1.1   ichiro  * 1. Redistributions of source code must retain the above copyright
     13   1.1   ichiro  *    notice, this list of conditions and the following disclaimer.
     14   1.1   ichiro  * 2. Redistributions in binary form must reproduce the above copyright
     15   1.1   ichiro  *    notice, this list of conditions and the following disclaimer in the
     16   1.1   ichiro  *    documentation and/or other materials provided with the distribution.
     17   1.1   ichiro  *
     18   1.1   ichiro  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     19   1.1   ichiro  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     20   1.1   ichiro  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     21   1.1   ichiro  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     22   1.1   ichiro  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     23   1.1   ichiro  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     24   1.1   ichiro  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     25   1.1   ichiro  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     26   1.1   ichiro  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     27   1.1   ichiro  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     28   1.1   ichiro  * POSSIBILITY OF SUCH DAMAGE.
     29   1.1   ichiro  */
     30   1.5      igy 
     31   1.5      igy #include <sys/cdefs.h>
     32  1.10      dsl __KERNEL_RCSID(0, "$NetBSD: ixp12x0_pci.c,v 1.10 2009/03/14 21:04:05 dsl Exp $");
     33   1.1   ichiro 
     34   1.1   ichiro /*
     35   1.1   ichiro  * PCI configuration support for IXP12x0 Network Processor chip.
     36   1.1   ichiro  */
     37   1.1   ichiro 
     38   1.1   ichiro #include <sys/param.h>
     39   1.1   ichiro #include <sys/systm.h>
     40   1.1   ichiro #include <sys/device.h>
     41   1.1   ichiro #include <sys/extent.h>
     42   1.1   ichiro #include <sys/malloc.h>
     43   1.1   ichiro 
     44   1.1   ichiro #include <uvm/uvm_extern.h>
     45   1.1   ichiro 
     46   1.1   ichiro #include <arm/ixp12x0/ixp12x0reg.h>
     47   1.1   ichiro #include <arm/ixp12x0/ixp12x0var.h>
     48   1.1   ichiro 
     49   1.1   ichiro #include <dev/pci/pcireg.h>
     50   1.1   ichiro #include <dev/pci/pcivar.h>
     51   1.2  thorpej #include <dev/pci/pciconf.h>
     52   1.1   ichiro 
     53   1.1   ichiro #include "opt_pci.h"
     54   1.1   ichiro #include "pci.h"
     55   1.1   ichiro 
     56   1.1   ichiro void ixp12x0_pci_attach_hook(struct device *, struct device *,
     57   1.1   ichiro 	struct pcibus_attach_args *);
     58   1.1   ichiro int ixp12x0_pci_bus_maxdevs(void *, int);
     59   1.1   ichiro pcitag_t ixp12x0_pci_make_tag(void *, int, int, int);
     60   1.1   ichiro void ixp12x0_pci_decompose_tag(void *, pcitag_t, int *, int *, int *);
     61   1.1   ichiro pcireg_t ixp12x0_pci_conf_read(void *, pcitag_t, int);
     62   1.1   ichiro void ixp12x0_pci_conf_write(void *, pcitag_t, int, pcireg_t);
     63   1.1   ichiro 
     64   1.4   ichiro static vaddr_t ixp12x0_pci_conf_setup(void *, struct ixp12x0_softc *, pcitag_t, int);
     65   1.4   ichiro 
     66   1.4   ichiro #define PCI_CONF_LOCK(s)	(s) = disable_interrupts(I32_bit)
     67   1.4   ichiro #define PCI_CONF_UNLOCK(s)	restore_interrupts((s))
     68   1.4   ichiro 
     69   1.3   ichiro #define	MAX_PCI_DEVICES	4
     70   1.3   ichiro 
     71   1.3   ichiro /*
     72   1.3   ichiro  * IXM1200 PCI configuration Cycles
     73   1.3   ichiro  *  Device               Address
     74   1.3   ichiro  * -------------------------------------
     75   1.3   ichiro  *   0    IXP1200        0x0800 - 0x08FF
     76   1.3   ichiro  *   1    i21555         0x1000 - 0x10FF
     77   1.3   ichiro  *   2    i82559         0x2000 - 0x20FF
     78   1.3   ichiro  *   3    PMC expansion  0x4000 - 0x40FF
     79   1.3   ichiro  */
     80   1.1   ichiro 
     81   1.1   ichiro void
     82   1.9      dsl ixp12x0_pci_init(pci_chipset_tag_t pc, void *cookie)
     83   1.1   ichiro {
     84   1.4   ichiro #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
     85   1.4   ichiro 	struct ixp12x0_softc *sc = cookie;
     86   1.4   ichiro 	struct extent *ioext, *memext;
     87   1.4   ichiro #endif
     88   1.1   ichiro 	pc->pc_conf_v = cookie;
     89   1.1   ichiro 	pc->pc_attach_hook = ixp12x0_pci_attach_hook;
     90   1.1   ichiro 	pc->pc_bus_maxdevs = ixp12x0_pci_bus_maxdevs;
     91   1.1   ichiro 	pc->pc_make_tag = ixp12x0_pci_make_tag;
     92   1.1   ichiro 	pc->pc_decompose_tag = ixp12x0_pci_decompose_tag;
     93   1.1   ichiro 	pc->pc_conf_read = ixp12x0_pci_conf_read;
     94   1.1   ichiro 	pc->pc_conf_write = ixp12x0_pci_conf_write;
     95   1.4   ichiro 
     96   1.4   ichiro #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
     97   1.4   ichiro 	ioext  = extent_create("pciio", 0, IXP12X0_PCI_IO_SIZE - 1,
     98   1.4   ichiro 				M_DEVBUF, NULL, 0, EX_NOWAIT);
     99   1.4   ichiro 	/* PCI MEM space is mapped same address as real memory */
    100   1.4   ichiro 	memext = extent_create("pcimem", IXP12X0_PCI_MEM_HWBASE,
    101   1.4   ichiro 				IXP12X0_PCI_MEM_HWBASE +
    102   1.4   ichiro 				IXP12X0_PCI_MEM_SIZE - 1,
    103   1.4   ichiro 				M_DEVBUF, NULL, 0, EX_NOWAIT);
    104   1.4   ichiro 	printf("%s: configuring PCI bus\n", sc->sc_dev.dv_xname);
    105   1.4   ichiro 	pci_configure_bus(pc, ioext, memext, NULL, 0 /* XXX bus = 0 */,
    106   1.4   ichiro 			  arm_dcache_align);
    107   1.4   ichiro 
    108   1.4   ichiro 	extent_destroy(ioext);
    109   1.4   ichiro 	extent_destroy(memext);
    110   1.4   ichiro #endif
    111   1.1   ichiro }
    112   1.1   ichiro 
    113   1.1   ichiro void
    114  1.10      dsl pci_conf_interrupt(pci_chipset_tag_t pc, int a, int b, int c, int d, int *p)
    115   1.1   ichiro {
    116   1.1   ichiro 	/* Nothing */
    117   1.1   ichiro }
    118   1.1   ichiro 
    119   1.1   ichiro void
    120   1.9      dsl ixp12x0_pci_attach_hook(struct device *parent, struct device *self, struct pcibus_attach_args *pba)
    121   1.1   ichiro {
    122   1.1   ichiro 	/* Nothing to do. */
    123   1.1   ichiro }
    124   1.1   ichiro 
    125   1.1   ichiro int
    126   1.9      dsl ixp12x0_pci_bus_maxdevs(void *v, int busno)
    127   1.1   ichiro {
    128   1.1   ichiro 	return(MAX_PCI_DEVICES);
    129   1.1   ichiro }
    130   1.1   ichiro 
    131   1.1   ichiro pcitag_t
    132  1.10      dsl ixp12x0_pci_make_tag(void *v, int bus, int device, int function)
    133   1.1   ichiro {
    134   1.1   ichiro #ifdef PCI_DEBUG
    135   1.1   ichiro 	printf("ixp12x0_pci_make_tag(v=%p, bus=%d, device=%d, function=%d)\n",
    136   1.1   ichiro 		v, bus, device, function);
    137   1.1   ichiro #endif
    138   1.1   ichiro 	return ((bus << 16) | (device << 11) | (function << 8));
    139   1.1   ichiro }
    140   1.1   ichiro 
    141   1.1   ichiro void
    142  1.10      dsl ixp12x0_pci_decompose_tag(void *v, pcitag_t tag, int *busp, int *devicep, int *functionp)
    143   1.1   ichiro {
    144   1.1   ichiro #ifdef PCI_DEBUG
    145   1.1   ichiro 	printf("ixp12x0_pci_decompose_tag(v=%p, tag=0x%08lx, bp=%x, dp=%x, fp=%x)\n",
    146   1.1   ichiro 		v, tag, (int)busp, (int)devicep, (int)functionp);
    147   1.1   ichiro #endif
    148   1.1   ichiro 
    149   1.1   ichiro 	if (busp != NULL)
    150   1.1   ichiro 		*busp = (tag >> 16) & 0xff;
    151   1.1   ichiro 	if (devicep != NULL)
    152   1.1   ichiro 		*devicep = (tag >> 11) & 0x1f;
    153   1.1   ichiro 	if (functionp != NULL)
    154   1.1   ichiro 		*functionp = (tag >> 8) & 0x7;
    155   1.1   ichiro }
    156   1.1   ichiro 
    157   1.4   ichiro static vaddr_t
    158   1.9      dsl ixp12x0_pci_conf_setup(void *v, struct ixp12x0_softc *sc, pcitag_t tag, int offset)
    159   1.1   ichiro {
    160   1.1   ichiro 	int bus, device, function;
    161   1.4   ichiro 	vaddr_t addr;
    162   1.1   ichiro 
    163   1.1   ichiro 	ixp12x0_pci_decompose_tag(v, tag, &bus, &device, &function);
    164   1.1   ichiro 
    165   1.4   ichiro 	if (bus == 0) {
    166   1.4   ichiro 		/* configuration type 0 */
    167   1.4   ichiro 		addr = (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_conf0_ioh) +
    168   1.6   ichiro 			((1 << (device + 10)) | (offset & ~3));
    169   1.4   ichiro 	} else {
    170   1.6   ichiro 		/* configuration type 1 */
    171   1.6   ichiro 		addr = (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_conf1_ioh) +
    172   1.6   ichiro 			((bus << 16) | (device << 11) |
    173   1.6   ichiro 			 (function << 8) | (offset & ~3) | 1);
    174   1.4   ichiro 	}
    175   1.6   ichiro 		return addr;
    176   1.4   ichiro }
    177   1.1   ichiro 
    178   1.4   ichiro pcireg_t
    179   1.9      dsl ixp12x0_pci_conf_read(void *v, pcitag_t tag, int offset)
    180   1.4   ichiro {
    181   1.4   ichiro 	struct ixp12x0_softc *sc = v;
    182   1.4   ichiro 	vaddr_t va = ixp12x0_pci_conf_setup(v, sc, tag, offset);
    183   1.4   ichiro 	pcireg_t rv;
    184   1.4   ichiro 	int s;
    185   1.1   ichiro 
    186   1.1   ichiro #ifdef PCI_DEBUG
    187   1.4   ichiro 	printf("ixp12x0_pci_conf_read: base=%lx,va=%lx,tag=%lx,offset=%x\n",
    188   1.4   ichiro 		sc->sc_conf0_ioh, va, tag, offset);
    189   1.1   ichiro #endif
    190   1.4   ichiro 	if (va == 0)
    191   1.4   ichiro 		return -1;
    192   1.4   ichiro 
    193   1.4   ichiro 	PCI_CONF_LOCK(s);
    194   1.4   ichiro 
    195   1.4   ichiro 	if (badaddr_read((void *) va, sizeof(rv), &rv)) {
    196   1.4   ichiro #ifdef PCI_DEBUG
    197   1.4   ichiro 		printf("conf_read: %lx bad address\n", va);
    198   1.3   ichiro #endif
    199   1.4   ichiro 		rv = (pcireg_t) - 1;
    200   1.4   ichiro 	}
    201   1.4   ichiro 
    202   1.4   ichiro 	PCI_CONF_UNLOCK(s);
    203   1.4   ichiro 
    204   1.4   ichiro 	return rv;
    205   1.1   ichiro }
    206   1.1   ichiro 
    207   1.1   ichiro void
    208   1.9      dsl ixp12x0_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
    209   1.1   ichiro {
    210   1.4   ichiro 	struct ixp12x0_softc *sc = v;
    211   1.4   ichiro 	vaddr_t va = ixp12x0_pci_conf_setup(v, sc, tag, offset);
    212   1.4   ichiro 	int s;
    213   1.1   ichiro 
    214   1.4   ichiro #ifdef PCI_DEBUG
    215   1.4   ichiro 	printf("ixp12x0_pci_conf_write: tag=%lx offset=%x -> va=%lx (base=%lx)\n",
    216   1.4   ichiro 		tag, offset, va, sc->sc_conf0_ioh);
    217   1.4   ichiro #endif
    218   1.1   ichiro 
    219   1.4   ichiro 	PCI_CONF_LOCK(s);
    220   1.3   ichiro 
    221   1.4   ichiro 	*(pcireg_t *) va = val;
    222   1.1   ichiro 
    223   1.4   ichiro 	PCI_CONF_UNLOCK(s);
    224   1.1   ichiro }
    225