ixp12x0_pci.c revision 1.13
1 /* $NetBSD: ixp12x0_pci.c,v 1.13 2012/10/27 17:17:39 chs Exp $ */ 2 /* 3 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Ichiro FUKUHARA and Naoto Shimazaki. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: ixp12x0_pci.c,v 1.13 2012/10/27 17:17:39 chs Exp $"); 33 34 /* 35 * PCI configuration support for IXP12x0 Network Processor chip. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/extent.h> 42 #include <sys/malloc.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <arm/ixp12x0/ixp12x0reg.h> 47 #include <arm/ixp12x0/ixp12x0var.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pciconf.h> 52 53 #include "opt_pci.h" 54 #include "pci.h" 55 56 void ixp12x0_pci_attach_hook(device_t, device_t, 57 struct pcibus_attach_args *); 58 int ixp12x0_pci_bus_maxdevs(void *, int); 59 pcitag_t ixp12x0_pci_make_tag(void *, int, int, int); 60 void ixp12x0_pci_decompose_tag(void *, pcitag_t, int *, int *, int *); 61 pcireg_t ixp12x0_pci_conf_read(void *, pcitag_t, int); 62 void ixp12x0_pci_conf_write(void *, pcitag_t, int, pcireg_t); 63 void ixp12x0_pci_conf_interrupt(void *, int, int, int, int, int *); 64 65 static vaddr_t ixp12x0_pci_conf_setup(void *, struct ixp12x0_softc *, pcitag_t, int); 66 67 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 68 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 69 70 #define MAX_PCI_DEVICES 4 71 72 /* 73 * IXM1200 PCI configuration Cycles 74 * Device Address 75 * ------------------------------------- 76 * 0 IXP1200 0x0800 - 0x08FF 77 * 1 i21555 0x1000 - 0x10FF 78 * 2 i82559 0x2000 - 0x20FF 79 * 3 PMC expansion 0x4000 - 0x40FF 80 */ 81 82 void 83 ixp12x0_pci_init(pci_chipset_tag_t pc, void *cookie) 84 { 85 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 86 struct ixp12x0_softc *sc = cookie; 87 struct extent *ioext, *memext; 88 #endif 89 pc->pc_conf_v = cookie; 90 pc->pc_attach_hook = ixp12x0_pci_attach_hook; 91 pc->pc_bus_maxdevs = ixp12x0_pci_bus_maxdevs; 92 pc->pc_make_tag = ixp12x0_pci_make_tag; 93 pc->pc_decompose_tag = ixp12x0_pci_decompose_tag; 94 pc->pc_conf_read = ixp12x0_pci_conf_read; 95 pc->pc_conf_write = ixp12x0_pci_conf_write; 96 pc->pc_conf_interrupt = ixp12x0_pci_conf_interrupt; 97 98 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 99 ioext = extent_create("pciio", 0, IXP12X0_PCI_IO_SIZE - 1, 100 NULL, 0, EX_NOWAIT); 101 /* PCI MEM space is mapped same address as real memory */ 102 memext = extent_create("pcimem", IXP12X0_PCI_MEM_HWBASE, 103 IXP12X0_PCI_MEM_HWBASE + 104 IXP12X0_PCI_MEM_SIZE - 1, 105 NULL, 0, EX_NOWAIT); 106 aprint_normal_dev(sc->sc_dev, "configuring PCI bus\n"); 107 pci_configure_bus(pc, ioext, memext, NULL, 0 /* XXX bus = 0 */, 108 arm_dcache_align); 109 110 extent_destroy(ioext); 111 extent_destroy(memext); 112 #endif 113 } 114 115 void 116 ixp12x0_pci_conf_interrupt(void *v, int a, int b, int c, int d, int *p) 117 { 118 /* Nothing */ 119 } 120 121 void 122 ixp12x0_pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 123 { 124 /* Nothing to do. */ 125 } 126 127 int 128 ixp12x0_pci_bus_maxdevs(void *v, int busno) 129 { 130 return(MAX_PCI_DEVICES); 131 } 132 133 pcitag_t 134 ixp12x0_pci_make_tag(void *v, int bus, int device, int function) 135 { 136 #ifdef PCI_DEBUG 137 printf("ixp12x0_pci_make_tag(v=%p, bus=%d, device=%d, function=%d)\n", 138 v, bus, device, function); 139 #endif 140 return ((bus << 16) | (device << 11) | (function << 8)); 141 } 142 143 void 144 ixp12x0_pci_decompose_tag(void *v, pcitag_t tag, int *busp, int *devicep, int *functionp) 145 { 146 #ifdef PCI_DEBUG 147 printf("ixp12x0_pci_decompose_tag(v=%p, tag=0x%08lx, bp=%x, dp=%x, fp=%x)\n", 148 v, tag, (int)busp, (int)devicep, (int)functionp); 149 #endif 150 151 if (busp != NULL) 152 *busp = (tag >> 16) & 0xff; 153 if (devicep != NULL) 154 *devicep = (tag >> 11) & 0x1f; 155 if (functionp != NULL) 156 *functionp = (tag >> 8) & 0x7; 157 } 158 159 static vaddr_t 160 ixp12x0_pci_conf_setup(void *v, struct ixp12x0_softc *sc, pcitag_t tag, int offset) 161 { 162 int bus, device, function; 163 vaddr_t addr; 164 165 ixp12x0_pci_decompose_tag(v, tag, &bus, &device, &function); 166 167 if (bus == 0) { 168 /* configuration type 0 */ 169 addr = (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_conf0_ioh) + 170 ((1 << (device + 10)) | (offset & ~3)); 171 } else { 172 /* configuration type 1 */ 173 addr = (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_conf1_ioh) + 174 ((bus << 16) | (device << 11) | 175 (function << 8) | (offset & ~3) | 1); 176 } 177 return addr; 178 } 179 180 pcireg_t 181 ixp12x0_pci_conf_read(void *v, pcitag_t tag, int offset) 182 { 183 struct ixp12x0_softc *sc = v; 184 vaddr_t va = ixp12x0_pci_conf_setup(v, sc, tag, offset); 185 pcireg_t rv; 186 int s; 187 188 #ifdef PCI_DEBUG 189 printf("ixp12x0_pci_conf_read: base=%lx,va=%lx,tag=%lx,offset=%x\n", 190 sc->sc_conf0_ioh, va, tag, offset); 191 #endif 192 if (va == 0) 193 return -1; 194 195 PCI_CONF_LOCK(s); 196 197 if (badaddr_read((void *) va, sizeof(rv), &rv)) { 198 #ifdef PCI_DEBUG 199 printf("conf_read: %lx bad address\n", va); 200 #endif 201 rv = (pcireg_t) - 1; 202 } 203 204 PCI_CONF_UNLOCK(s); 205 206 return rv; 207 } 208 209 void 210 ixp12x0_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 211 { 212 struct ixp12x0_softc *sc = v; 213 vaddr_t va = ixp12x0_pci_conf_setup(v, sc, tag, offset); 214 int s; 215 216 #ifdef PCI_DEBUG 217 printf("ixp12x0_pci_conf_write: tag=%lx offset=%x -> va=%lx (base=%lx)\n", 218 tag, offset, va, sc->sc_conf0_ioh); 219 #endif 220 221 PCI_CONF_LOCK(s); 222 223 *(pcireg_t *) va = val; 224 225 PCI_CONF_UNLOCK(s); 226 } 227
Indexes created Mon Sep 29 21:09:56 GMT 2025