ixp12x0_pci.c revision 1.14
1 /* $NetBSD: ixp12x0_pci.c,v 1.14 2013/08/18 15:58:19 matt Exp $ */ 2 /* 3 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Ichiro FUKUHARA and Naoto Shimazaki. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: ixp12x0_pci.c,v 1.14 2013/08/18 15:58:19 matt Exp $"); 33 34 /* 35 * PCI configuration support for IXP12x0 Network Processor chip. 36 */ 37 38 #include "opt_pci.h" 39 #include "pci.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/extent.h> 45 #include <sys/malloc.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <arm/ixp12x0/ixp12x0reg.h> 50 #include <arm/ixp12x0/ixp12x0var.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pciconf.h> 55 56 #include <arm/locore.h> 57 58 void ixp12x0_pci_attach_hook(device_t, device_t, 59 struct pcibus_attach_args *); 60 int ixp12x0_pci_bus_maxdevs(void *, int); 61 pcitag_t ixp12x0_pci_make_tag(void *, int, int, int); 62 void ixp12x0_pci_decompose_tag(void *, pcitag_t, int *, int *, int *); 63 pcireg_t ixp12x0_pci_conf_read(void *, pcitag_t, int); 64 void ixp12x0_pci_conf_write(void *, pcitag_t, int, pcireg_t); 65 void ixp12x0_pci_conf_interrupt(void *, int, int, int, int, int *); 66 67 static vaddr_t ixp12x0_pci_conf_setup(void *, struct ixp12x0_softc *, pcitag_t, int); 68 69 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 70 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 71 72 #define MAX_PCI_DEVICES 4 73 74 /* 75 * IXM1200 PCI configuration Cycles 76 * Device Address 77 * ------------------------------------- 78 * 0 IXP1200 0x0800 - 0x08FF 79 * 1 i21555 0x1000 - 0x10FF 80 * 2 i82559 0x2000 - 0x20FF 81 * 3 PMC expansion 0x4000 - 0x40FF 82 */ 83 84 void 85 ixp12x0_pci_init(pci_chipset_tag_t pc, void *cookie) 86 { 87 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 88 struct ixp12x0_softc *sc = cookie; 89 struct extent *ioext, *memext; 90 #endif 91 pc->pc_conf_v = cookie; 92 pc->pc_attach_hook = ixp12x0_pci_attach_hook; 93 pc->pc_bus_maxdevs = ixp12x0_pci_bus_maxdevs; 94 pc->pc_make_tag = ixp12x0_pci_make_tag; 95 pc->pc_decompose_tag = ixp12x0_pci_decompose_tag; 96 pc->pc_conf_read = ixp12x0_pci_conf_read; 97 pc->pc_conf_write = ixp12x0_pci_conf_write; 98 pc->pc_conf_interrupt = ixp12x0_pci_conf_interrupt; 99 100 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 101 ioext = extent_create("pciio", 0, IXP12X0_PCI_IO_SIZE - 1, 102 NULL, 0, EX_NOWAIT); 103 /* PCI MEM space is mapped same address as real memory */ 104 memext = extent_create("pcimem", IXP12X0_PCI_MEM_HWBASE, 105 IXP12X0_PCI_MEM_HWBASE + 106 IXP12X0_PCI_MEM_SIZE - 1, 107 NULL, 0, EX_NOWAIT); 108 aprint_normal_dev(sc->sc_dev, "configuring PCI bus\n"); 109 pci_configure_bus(pc, ioext, memext, NULL, 0 /* XXX bus = 0 */, 110 arm_dcache_align); 111 112 extent_destroy(ioext); 113 extent_destroy(memext); 114 #endif 115 } 116 117 void 118 ixp12x0_pci_conf_interrupt(void *v, int a, int b, int c, int d, int *p) 119 { 120 /* Nothing */ 121 } 122 123 void 124 ixp12x0_pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 125 { 126 /* Nothing to do. */ 127 } 128 129 int 130 ixp12x0_pci_bus_maxdevs(void *v, int busno) 131 { 132 return(MAX_PCI_DEVICES); 133 } 134 135 pcitag_t 136 ixp12x0_pci_make_tag(void *v, int bus, int device, int function) 137 { 138 #ifdef PCI_DEBUG 139 printf("ixp12x0_pci_make_tag(v=%p, bus=%d, device=%d, function=%d)\n", 140 v, bus, device, function); 141 #endif 142 return ((bus << 16) | (device << 11) | (function << 8)); 143 } 144 145 void 146 ixp12x0_pci_decompose_tag(void *v, pcitag_t tag, int *busp, int *devicep, int *functionp) 147 { 148 #ifdef PCI_DEBUG 149 printf("ixp12x0_pci_decompose_tag(v=%p, tag=0x%08lx, bp=%x, dp=%x, fp=%x)\n", 150 v, tag, (int)busp, (int)devicep, (int)functionp); 151 #endif 152 153 if (busp != NULL) 154 *busp = (tag >> 16) & 0xff; 155 if (devicep != NULL) 156 *devicep = (tag >> 11) & 0x1f; 157 if (functionp != NULL) 158 *functionp = (tag >> 8) & 0x7; 159 } 160 161 static vaddr_t 162 ixp12x0_pci_conf_setup(void *v, struct ixp12x0_softc *sc, pcitag_t tag, int offset) 163 { 164 int bus, device, function; 165 vaddr_t addr; 166 167 ixp12x0_pci_decompose_tag(v, tag, &bus, &device, &function); 168 169 if (bus == 0) { 170 /* configuration type 0 */ 171 addr = (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_conf0_ioh) + 172 ((1 << (device + 10)) | (offset & ~3)); 173 } else { 174 /* configuration type 1 */ 175 addr = (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_conf1_ioh) + 176 ((bus << 16) | (device << 11) | 177 (function << 8) | (offset & ~3) | 1); 178 } 179 return addr; 180 } 181 182 pcireg_t 183 ixp12x0_pci_conf_read(void *v, pcitag_t tag, int offset) 184 { 185 struct ixp12x0_softc *sc = v; 186 vaddr_t va = ixp12x0_pci_conf_setup(v, sc, tag, offset); 187 pcireg_t rv; 188 int s; 189 190 #ifdef PCI_DEBUG 191 printf("ixp12x0_pci_conf_read: base=%lx,va=%lx,tag=%lx,offset=%x\n", 192 sc->sc_conf0_ioh, va, tag, offset); 193 #endif 194 if (va == 0) 195 return -1; 196 197 PCI_CONF_LOCK(s); 198 199 if (badaddr_read((void *) va, sizeof(rv), &rv)) { 200 #ifdef PCI_DEBUG 201 printf("conf_read: %lx bad address\n", va); 202 #endif 203 rv = (pcireg_t) - 1; 204 } 205 206 PCI_CONF_UNLOCK(s); 207 208 return rv; 209 } 210 211 void 212 ixp12x0_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 213 { 214 struct ixp12x0_softc *sc = v; 215 vaddr_t va = ixp12x0_pci_conf_setup(v, sc, tag, offset); 216 int s; 217 218 #ifdef PCI_DEBUG 219 printf("ixp12x0_pci_conf_write: tag=%lx offset=%x -> va=%lx (base=%lx)\n", 220 tag, offset, va, sc->sc_conf0_ioh); 221 #endif 222 223 PCI_CONF_LOCK(s); 224 225 *(pcireg_t *) va = val; 226 227 PCI_CONF_UNLOCK(s); 228 } 229
Indexes created Tue Sep 30 10:09:55 GMT 2025