ixp12x0_pci.c revision 1.4
1 /* $NetBSD: ixp12x0_pci.c,v 1.4 2003/02/17 20:51:52 ichiro Exp $ */ 2 /* 3 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Ichiro FUKUHARA and Naoto Shimazaki. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of The NetBSD Foundation nor the names of its 22 * contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for IXP12x0 Network Processor chip. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/extent.h> 46 #include <sys/malloc.h> 47 48 #include <uvm/uvm_extern.h> 49 50 #include <arm/ixp12x0/ixp12x0reg.h> 51 #include <arm/ixp12x0/ixp12x0var.h> 52 53 #include <dev/pci/pcireg.h> 54 #include <dev/pci/pcivar.h> 55 #include <dev/pci/pciconf.h> 56 57 #include "opt_pci.h" 58 #include "pci.h" 59 60 void ixp12x0_pci_attach_hook(struct device *, struct device *, 61 struct pcibus_attach_args *); 62 int ixp12x0_pci_bus_maxdevs(void *, int); 63 pcitag_t ixp12x0_pci_make_tag(void *, int, int, int); 64 void ixp12x0_pci_decompose_tag(void *, pcitag_t, int *, int *, int *); 65 pcireg_t ixp12x0_pci_conf_read(void *, pcitag_t, int); 66 void ixp12x0_pci_conf_write(void *, pcitag_t, int, pcireg_t); 67 68 static vaddr_t ixp12x0_pci_conf_setup(void *, struct ixp12x0_softc *, pcitag_t, int); 69 70 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 71 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 72 73 #define MAX_PCI_DEVICES 4 74 75 /* 76 * IXM1200 PCI configuration Cycles 77 * Device Address 78 * ------------------------------------- 79 * 0 IXP1200 0x0800 - 0x08FF 80 * 1 i21555 0x1000 - 0x10FF 81 * 2 i82559 0x2000 - 0x20FF 82 * 3 PMC expansion 0x4000 - 0x40FF 83 */ 84 85 void 86 ixp12x0_pci_init(pc, cookie) 87 pci_chipset_tag_t pc; 88 void *cookie; 89 { 90 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 91 struct ixp12x0_softc *sc = cookie; 92 struct extent *ioext, *memext; 93 #endif 94 pc->pc_conf_v = cookie; 95 pc->pc_attach_hook = ixp12x0_pci_attach_hook; 96 pc->pc_bus_maxdevs = ixp12x0_pci_bus_maxdevs; 97 pc->pc_make_tag = ixp12x0_pci_make_tag; 98 pc->pc_decompose_tag = ixp12x0_pci_decompose_tag; 99 pc->pc_conf_read = ixp12x0_pci_conf_read; 100 pc->pc_conf_write = ixp12x0_pci_conf_write; 101 102 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 103 ioext = extent_create("pciio", 0, IXP12X0_PCI_IO_SIZE - 1, 104 M_DEVBUF, NULL, 0, EX_NOWAIT); 105 /* PCI MEM space is mapped same address as real memory */ 106 memext = extent_create("pcimem", IXP12X0_PCI_MEM_HWBASE, 107 IXP12X0_PCI_MEM_HWBASE + 108 IXP12X0_PCI_MEM_SIZE - 1, 109 M_DEVBUF, NULL, 0, EX_NOWAIT); 110 printf("%s: configuring PCI bus\n", sc->sc_dev.dv_xname); 111 pci_configure_bus(pc, ioext, memext, NULL, 0 /* XXX bus = 0 */, 112 arm_dcache_align); 113 114 extent_destroy(ioext); 115 extent_destroy(memext); 116 #endif 117 } 118 119 void 120 pci_conf_interrupt(pc, a, b, c, d, p) 121 pci_chipset_tag_t pc; 122 int a, b, c, d, *p; 123 { 124 /* Nothing */ 125 } 126 127 void 128 ixp12x0_pci_attach_hook(parent, self, pba) 129 struct device *parent; 130 struct device *self; 131 struct pcibus_attach_args *pba; 132 { 133 /* Nothing to do. */ 134 } 135 136 int 137 ixp12x0_pci_bus_maxdevs(v, busno) 138 void *v; 139 int busno; 140 { 141 return(MAX_PCI_DEVICES); 142 } 143 144 pcitag_t 145 ixp12x0_pci_make_tag(v, bus, device, function) 146 void *v; 147 int bus, device, function; 148 { 149 #ifdef PCI_DEBUG 150 printf("ixp12x0_pci_make_tag(v=%p, bus=%d, device=%d, function=%d)\n", 151 v, bus, device, function); 152 #endif 153 return ((bus << 16) | (device << 11) | (function << 8)); 154 } 155 156 void 157 ixp12x0_pci_decompose_tag(v, tag, busp, devicep, functionp) 158 void *v; 159 pcitag_t tag; 160 int *busp, *devicep, *functionp; 161 { 162 #ifdef PCI_DEBUG 163 printf("ixp12x0_pci_decompose_tag(v=%p, tag=0x%08lx, bp=%x, dp=%x, fp=%x)\n", 164 v, tag, (int)busp, (int)devicep, (int)functionp); 165 #endif 166 167 if (busp != NULL) 168 *busp = (tag >> 16) & 0xff; 169 if (devicep != NULL) 170 *devicep = (tag >> 11) & 0x1f; 171 if (functionp != NULL) 172 *functionp = (tag >> 8) & 0x7; 173 } 174 175 static vaddr_t 176 ixp12x0_pci_conf_setup(v, sc, tag, offset) 177 void *v; 178 struct ixp12x0_softc *sc; 179 pcitag_t tag; 180 int offset; 181 { 182 int bus, device, function; 183 vaddr_t addr; 184 185 ixp12x0_pci_decompose_tag(v, tag, &bus, &device, &function); 186 187 if (bus == 0) { 188 /* configuration type 0 */ 189 #if 1 190 addr = (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_conf0_ioh) + 191 ((1 << (device + 10)) | (offset & 0xff)); 192 #else 193 addr = (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_conf0_ioh) + 194 (0xc00000 | (1 << (device)) << 11 | (offset & 0xff)); 195 #endif 196 return addr; 197 } else { 198 return (vaddr_t) - 1; 199 } 200 } 201 202 pcireg_t 203 ixp12x0_pci_conf_read(v, tag, offset) 204 void *v; 205 pcitag_t tag; 206 int offset; 207 { 208 struct ixp12x0_softc *sc = v; 209 vaddr_t va = ixp12x0_pci_conf_setup(v, sc, tag, offset); 210 pcireg_t rv; 211 int s; 212 213 #ifdef PCI_DEBUG 214 printf("ixp12x0_pci_conf_read: base=%lx,va=%lx,tag=%lx,offset=%x\n", 215 sc->sc_conf0_ioh, va, tag, offset); 216 #endif 217 if (va == 0) 218 return -1; 219 220 PCI_CONF_LOCK(s); 221 222 if (badaddr_read((void *) va, sizeof(rv), &rv)) { 223 #ifdef PCI_DEBUG 224 printf("conf_read: %lx bad address\n", va); 225 #endif 226 rv = (pcireg_t) - 1; 227 } 228 229 PCI_CONF_UNLOCK(s); 230 231 return rv; 232 } 233 234 void 235 ixp12x0_pci_conf_write(v, tag, offset, val) 236 void *v; 237 pcitag_t tag; 238 int offset; 239 pcireg_t val; 240 { 241 struct ixp12x0_softc *sc = v; 242 vaddr_t va = ixp12x0_pci_conf_setup(v, sc, tag, offset); 243 int s; 244 245 #ifdef PCI_DEBUG 246 printf("ixp12x0_pci_conf_write: tag=%lx offset=%x -> va=%lx (base=%lx)\n", 247 tag, offset, va, sc->sc_conf0_ioh); 248 #endif 249 250 PCI_CONF_LOCK(s); 251 252 *(pcireg_t *) va = val; 253 254 PCI_CONF_UNLOCK(s); 255 } 256
Indexes created Tue Sep 30 10:09:55 GMT 2025