ixp12x0_pci.c revision 1.7.76.1
1 /* $NetBSD: ixp12x0_pci.c,v 1.7.76.1 2008/06/02 13:21:54 mjf Exp $ */ 2 /* 3 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Ichiro FUKUHARA and Naoto Shimazaki. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: ixp12x0_pci.c,v 1.7.76.1 2008/06/02 13:21:54 mjf Exp $"); 33 34 /* 35 * PCI configuration support for IXP12x0 Network Processor chip. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/extent.h> 42 #include <sys/malloc.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <arm/ixp12x0/ixp12x0reg.h> 47 #include <arm/ixp12x0/ixp12x0var.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pciconf.h> 52 53 #include "opt_pci.h" 54 #include "pci.h" 55 56 void ixp12x0_pci_attach_hook(struct device *, struct device *, 57 struct pcibus_attach_args *); 58 int ixp12x0_pci_bus_maxdevs(void *, int); 59 pcitag_t ixp12x0_pci_make_tag(void *, int, int, int); 60 void ixp12x0_pci_decompose_tag(void *, pcitag_t, int *, int *, int *); 61 pcireg_t ixp12x0_pci_conf_read(void *, pcitag_t, int); 62 void ixp12x0_pci_conf_write(void *, pcitag_t, int, pcireg_t); 63 64 static vaddr_t ixp12x0_pci_conf_setup(void *, struct ixp12x0_softc *, pcitag_t, int); 65 66 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 67 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 68 69 #define MAX_PCI_DEVICES 4 70 71 /* 72 * IXM1200 PCI configuration Cycles 73 * Device Address 74 * ------------------------------------- 75 * 0 IXP1200 0x0800 - 0x08FF 76 * 1 i21555 0x1000 - 0x10FF 77 * 2 i82559 0x2000 - 0x20FF 78 * 3 PMC expansion 0x4000 - 0x40FF 79 */ 80 81 void 82 ixp12x0_pci_init(pc, cookie) 83 pci_chipset_tag_t pc; 84 void *cookie; 85 { 86 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 87 struct ixp12x0_softc *sc = cookie; 88 struct extent *ioext, *memext; 89 #endif 90 pc->pc_conf_v = cookie; 91 pc->pc_attach_hook = ixp12x0_pci_attach_hook; 92 pc->pc_bus_maxdevs = ixp12x0_pci_bus_maxdevs; 93 pc->pc_make_tag = ixp12x0_pci_make_tag; 94 pc->pc_decompose_tag = ixp12x0_pci_decompose_tag; 95 pc->pc_conf_read = ixp12x0_pci_conf_read; 96 pc->pc_conf_write = ixp12x0_pci_conf_write; 97 98 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 99 ioext = extent_create("pciio", 0, IXP12X0_PCI_IO_SIZE - 1, 100 M_DEVBUF, NULL, 0, EX_NOWAIT); 101 /* PCI MEM space is mapped same address as real memory */ 102 memext = extent_create("pcimem", IXP12X0_PCI_MEM_HWBASE, 103 IXP12X0_PCI_MEM_HWBASE + 104 IXP12X0_PCI_MEM_SIZE - 1, 105 M_DEVBUF, NULL, 0, EX_NOWAIT); 106 printf("%s: configuring PCI bus\n", sc->sc_dev.dv_xname); 107 pci_configure_bus(pc, ioext, memext, NULL, 0 /* XXX bus = 0 */, 108 arm_dcache_align); 109 110 extent_destroy(ioext); 111 extent_destroy(memext); 112 #endif 113 } 114 115 void 116 pci_conf_interrupt(pc, a, b, c, d, p) 117 pci_chipset_tag_t pc; 118 int a, b, c, d, *p; 119 { 120 /* Nothing */ 121 } 122 123 void 124 ixp12x0_pci_attach_hook(parent, self, pba) 125 struct device *parent; 126 struct device *self; 127 struct pcibus_attach_args *pba; 128 { 129 /* Nothing to do. */ 130 } 131 132 int 133 ixp12x0_pci_bus_maxdevs(v, busno) 134 void *v; 135 int busno; 136 { 137 return(MAX_PCI_DEVICES); 138 } 139 140 pcitag_t 141 ixp12x0_pci_make_tag(v, bus, device, function) 142 void *v; 143 int bus, device, function; 144 { 145 #ifdef PCI_DEBUG 146 printf("ixp12x0_pci_make_tag(v=%p, bus=%d, device=%d, function=%d)\n", 147 v, bus, device, function); 148 #endif 149 return ((bus << 16) | (device << 11) | (function << 8)); 150 } 151 152 void 153 ixp12x0_pci_decompose_tag(v, tag, busp, devicep, functionp) 154 void *v; 155 pcitag_t tag; 156 int *busp, *devicep, *functionp; 157 { 158 #ifdef PCI_DEBUG 159 printf("ixp12x0_pci_decompose_tag(v=%p, tag=0x%08lx, bp=%x, dp=%x, fp=%x)\n", 160 v, tag, (int)busp, (int)devicep, (int)functionp); 161 #endif 162 163 if (busp != NULL) 164 *busp = (tag >> 16) & 0xff; 165 if (devicep != NULL) 166 *devicep = (tag >> 11) & 0x1f; 167 if (functionp != NULL) 168 *functionp = (tag >> 8) & 0x7; 169 } 170 171 static vaddr_t 172 ixp12x0_pci_conf_setup(v, sc, tag, offset) 173 void *v; 174 struct ixp12x0_softc *sc; 175 pcitag_t tag; 176 int offset; 177 { 178 int bus, device, function; 179 vaddr_t addr; 180 181 ixp12x0_pci_decompose_tag(v, tag, &bus, &device, &function); 182 183 if (bus == 0) { 184 /* configuration type 0 */ 185 addr = (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_conf0_ioh) + 186 ((1 << (device + 10)) | (offset & ~3)); 187 } else { 188 /* configuration type 1 */ 189 addr = (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_conf1_ioh) + 190 ((bus << 16) | (device << 11) | 191 (function << 8) | (offset & ~3) | 1); 192 } 193 return addr; 194 } 195 196 pcireg_t 197 ixp12x0_pci_conf_read(v, tag, offset) 198 void *v; 199 pcitag_t tag; 200 int offset; 201 { 202 struct ixp12x0_softc *sc = v; 203 vaddr_t va = ixp12x0_pci_conf_setup(v, sc, tag, offset); 204 pcireg_t rv; 205 int s; 206 207 #ifdef PCI_DEBUG 208 printf("ixp12x0_pci_conf_read: base=%lx,va=%lx,tag=%lx,offset=%x\n", 209 sc->sc_conf0_ioh, va, tag, offset); 210 #endif 211 if (va == 0) 212 return -1; 213 214 PCI_CONF_LOCK(s); 215 216 if (badaddr_read((void *) va, sizeof(rv), &rv)) { 217 #ifdef PCI_DEBUG 218 printf("conf_read: %lx bad address\n", va); 219 #endif 220 rv = (pcireg_t) - 1; 221 } 222 223 PCI_CONF_UNLOCK(s); 224 225 return rv; 226 } 227 228 void 229 ixp12x0_pci_conf_write(v, tag, offset, val) 230 void *v; 231 pcitag_t tag; 232 int offset; 233 pcireg_t val; 234 { 235 struct ixp12x0_softc *sc = v; 236 vaddr_t va = ixp12x0_pci_conf_setup(v, sc, tag, offset); 237 int s; 238 239 #ifdef PCI_DEBUG 240 printf("ixp12x0_pci_conf_write: tag=%lx offset=%x -> va=%lx (base=%lx)\n", 241 tag, offset, va, sc->sc_conf0_ioh); 242 #endif 243 244 PCI_CONF_LOCK(s); 245 246 *(pcireg_t *) va = val; 247 248 PCI_CONF_UNLOCK(s); 249 } 250
Indexes created Thu Oct 23 22:10:10 GMT 2025