ixp12x0_pcireg.h revision 1.2
1 /* $NetBSD: ixp12x0_pcireg.h,v 1.2 2003/02/17 20:51:52 ichiro Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 5 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Ichiro FUKUHARA. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA AND CONTRIBUTORS ``AS IS'' 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS 26 * HEAD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 27 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef _IXP12X0_PCIREG_H_ 36 #define _IXP12X0_PCIREG_H_ 37 38 #include <arm/ixp12x0/ixp12x0reg.h> 39 40 /* PCI Configuration Space Registers */ 41 42 /* base address */ 43 #define IXP_PCI_MEM_BAR 0x10 44 # define IXP1200_PCI_MEM_BAR 0x40000000UL 45 # define IXP_PCI_MEM_BAR_MASK 0xffffff80 46 47 #define IXP_PCI_IO_BAR 0x14 48 # define IXP1200_PCI_IO_BAR 0x0000f000UL 49 # define IXP_PCI_IO_BAR_MASK 0xffffff80 50 51 #define IXP_PCI_DRAM_BAR 0x18 52 # define IXP1200_PCI_DRAM_BAR 0x00000000UL 53 # define IXP_PCI_DRAM_BAR_MASK 0xfffc0000 54 55 #define PCI_CAP_PTR 0x34 56 #define PCI_INT_LINE 0x3C 57 #define MAILBOX_0 0x50 58 #define MAILBOX_1 0x54 59 #define MAILBOX_2 0x58 60 #define MAILBOX_3 0x5C 61 #define DOORBELL 0x60 62 #define DOORBELL_SETUP 0x64 63 #define ROM_BYTE_WRITE 0x68 64 #define CAP_PTR_EXT 0x70 65 #define PWR_MGMT 0x74 66 67 /* Reset Registers*/ 68 #define IXPPCI_IXP1200_RESET 0x7C 69 # define RESET_UE0 (1U << 0) 70 # define RESET_UE1 (1U << 1) 71 # define RESET_UE2 (1U << 2) 72 # define RESET_UE3 (1U << 3) 73 # define RESET_UE4 (1U << 4) 74 # define RESET_UE5 (1U << 5) 75 # define RESET_PCIRST (1U << 14) 76 # define RESET_EXRST (1U << 15) 77 # define RESET_FBI (1U << 16) 78 # define RESET_CMDARB (1U << 17) 79 # define RESET_SDRAM (1U << 18) 80 # define RESET_SRAM (1U << 29) 81 # define RESET_PCI (1U << 30) 82 # define RESET_SACORE (1U << 31) 83 84 # define RESET_FULL (RESET_UE0 | RESET_UE1 | RESET_UE2 | \ 85 RESET_UE3 | RESET_UE4 | RESET_UE5 | \ 86 RESET_EXRST | RESET_FBI | \ 87 RESET_CMDARB | RESET_SDRAM | RESET_SRAM | \ 88 RESET_PCI | RESET_SACORE) 89 90 #define CHAN_1_BYTE_COUNT 0x80 91 #define CHAN_1_PCI_ADDR 0x84 92 #define CHAN_1_DRAM_ADDR 0x88 93 #define CHAN_1_DESC_PTR 0x8C 94 #define CHAN_1_CONTROL 0x90 95 #define DMA_INF_MODE 0x9C 96 #define CHAN_2_BYTE_COUNT 0xA0 97 #define CHAN_2_PCI_ADDR 0xA4 98 #define CHAN_2_DRAM_ADDR 0xA8 99 #define CHAN_2_DESC_PTR 0xAC 100 #define CHAN_2_CONTROL 0xB0 101 102 #define CSR_BASE_ADDR_MASK 0x0F8 103 #define CSR_BASE_ADDR_OFF 0xFC 104 # define CSR_BASE_ADDR_MASK_1M 0x000c0000UL 105 106 #define DRAM_BASE_ADDR_MASK 0x100 107 #define DRAM_BASE_ADDR_OFF 0x104 108 # define DRAM_BASE_ADDR_MASK_256MB 0x0ffc0000UL 109 110 #define ROM_BASE_ADDR_MASK 0x108 111 #define DRAM_TIMING 0x10C 112 #define DRAM_ADDR_SIZE_0 0x110 113 #define DRAM_ADDR_SIZE_1 0x114 114 #define DRAM_ADDR_SIZE_2 0x118 115 #define DRAM_ADDR_SIZE_3 0x11C 116 #define I2O_IFH 0x120 117 #define I2O_IPT 0x124 118 #define I2O_OPH 0x128 119 #define I2O_OFT 0x12C 120 #define I2O_IFC 0x130 121 #define I2O_OPC 0x134 122 #define I2O_IPC 0x138 123 #define SA_CONTROL 0x13C 124 # define SA_CONTROL_PNR (1 << 9) 125 # define SA_CONTROL_COMPLETE (1 << 0) 126 #define PCI_ADDR_EXT 0x140 127 # define PCI_ADDR_EXT_PIOADD(x) ((x) & 0xffff0000) 128 # define PCI_ADDR_EXT_PMSA(x) (((x) & 0xe0000000) >> 16) 129 #define PREFETCH_RANGE 0x144 130 #define PCI_ABITOR_STATUS 0x148 131 #define DBELL_PCI_MASK 0x150 132 #define DBELL_SA_MASK 0x154 133 134 /* 135 * Interrupt index assignment 136 * 137 * FIQ/IRQ bitmap in "PCI Registers Accessible Through StrongARM Core" 138 * 139 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 140 * bit 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 141 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------------+-+-+-+-+---+-+-+ 142 * |D|R|R|D|D|P|I|S|R|S|D|D| |P|D|D|D| |T|T|T|T| |S| | 143 * |P|T|M|P|T|W|I|D|S|B|M|M|R|I|M|M|F| |4|3|2|1| |I| | 144 * |E|A|A|E|E|R|P|P|E| |A|A|E|L|A|A|H| RES | | | | |RES| | | 145 * | | | |D| |M| |A|R| |2|1|S| |2|1| | | | | | | | | | 146 * | | | | | | | |R|R| |N|N| | | | | | | | | | | | | | 147 * | | | | | | | | | | |B|B| | | | | | | | | | | | | | 148 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------------+-+-+-+-+---+-+-+ 149 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 150 * index 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 7 6 5 4 1 0 151 * 152 */ 153 154 /* PCI_IRQ_STATUS */ 155 #define IXPPCI_IRQ_STATUS (IXP12X0_PCI_VBASE + 0x180) 156 #define IXPPCI_FIQ_STATUS (IXP12X0_PCI_VBASE + 0x280) 157 #define IXPPCI_IRQ_RAW_STATUS (IXP12X0_PCI_VBASE + 0x184) 158 #define IXPPCI_FIQ_RAW_STATUS (IXP12X0_PCI_VBASE + 0x284) 159 #define IXPPCI_IRQ_ENABLE (IXP12X0_PCI_VBASE + 0x188) 160 #define IXPPCI_FIQ_ENABLE (IXP12X0_PCI_VBASE + 0x288) 161 #define IXPPCI_IRQ_ENABLE_SET (IXP12X0_PCI_VBASE + 0x188) 162 #define IXPPCI_FIQ_ENABLE_SET (IXP12X0_PCI_VBASE + 0x288) 163 #define IXPPCI_IRQ_ENABLE_CLEAR (IXP12X0_PCI_VBASE + 0x18c) 164 #define IXPPCI_FIQ_ENABLE_CLEAR (IXP12X0_PCI_VBASE + 0x28c) 165 #define IXPPCI_IRQ_SOFT (IXP12X0_PCI_VBASE + 0x190) 166 #define IXPPCI_FIQ_SOFT (IXP12X0_PCI_VBASE + 0x290) 167 #define IXPPCI_IRQST_TIMER (IXP12X0_PCI_VBASE + 0x010) 168 169 #define IXPPCI_INTR_DPE 63 170 #define IXPPCI_INTR_RTA 62 171 #define IXPPCI_INTR_RMA 61 172 #define IXPPCI_INTR_DPED 60 173 #define IXPPCI_INTR_DTE 59 174 #define IXPPCI_INTR_PWRM 58 175 #define IXPPCI_INTR_IIP 57 176 #define IXPPCI_INTR_SDPAR 56 177 #define IXPPCI_INTR_RSERR 55 178 #define IXPPCI_INTR_SB 54 179 #define IXPPCI_INTR_DMA2NB 53 180 #define IXPPCI_INTR_DMA1NB 52 181 #define IXPPCI_INTR_bit19 51 182 #define IXPPCI_INTR_PIL 50 183 #define IXPPCI_INTR_DMA2 49 184 #define IXPPCI_INTR_DMA1 48 185 #define IXPPCI_INTR_DFH 47 186 #define IXPPCI_INTR_bit14 46 187 #define IXPPCI_INTR_bit13 45 188 #define IXPPCI_INTR_bit12 44 189 #define IXPPCI_INTR_bit11 43 190 #define IXPPCI_INTR_bit10 42 191 #define IXPPCI_INTR_bit9 41 192 #define IXPPCI_INTR_bit8 40 193 #define IXPPCI_INTR_T4 39 194 #define IXPPCI_INTR_T3 38 195 #define IXPPCI_INTR_T2 37 196 #define IXPPCI_INTR_T1 36 197 #define IXPPCI_INTR_bit3 35 198 #define IXPPCI_INTR_bit2 34 199 #define IXPPCI_INTR_SI 33 200 #define IXPPCI_INTR_bit0 32 201 202 #endif /* _IXP12X0_PCIREG_H_ */ 203
Indexes created Thu Oct 02 14:10:14 GMT 2025