ixp12x0reg.h revision 1.1.2.2
1 1.1.2.2 gehenna /* $NetBSD: ixp12x0reg.h,v 1.1.2.2 2002/07/21 13:00:31 gehenna Exp $ */ 2 1.1.2.2 gehenna 3 1.1.2.2 gehenna /* 4 1.1.2.2 gehenna * Copyright (c) 2002 5 1.1.2.2 gehenna * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 6 1.1.2.2 gehenna * All rights reserved. 7 1.1.2.2 gehenna * 8 1.1.2.2 gehenna * Redistribution and use in source and binary forms, with or without 9 1.1.2.2 gehenna * modification, are permitted provided that the following conditions 10 1.1.2.2 gehenna * are met: 11 1.1.2.2 gehenna * 1. Redistributions of source code must retain the above copyright 12 1.1.2.2 gehenna * notice, this list of conditions and the following disclaimer. 13 1.1.2.2 gehenna * 2. Redistributions in binary form must reproduce the above copyright 14 1.1.2.2 gehenna * notice, this list of conditions and the following disclaimer in the 15 1.1.2.2 gehenna * documentation and/or other materials provided with the distribution. 16 1.1.2.2 gehenna * 3. All advertising materials mentioning features or use of this software 17 1.1.2.2 gehenna * must display the following acknowledgement: 18 1.1.2.2 gehenna * This product includes software developed by Ichiro FUKUHARA. 19 1.1.2.2 gehenna * 4. The name of the company nor the name of the author may be used to 20 1.1.2.2 gehenna * endorse or promote products derived from this software without specific 21 1.1.2.2 gehenna * prior written permission. 22 1.1.2.2 gehenna * 23 1.1.2.2 gehenna * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 1.1.2.2 gehenna * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 1.1.2.2 gehenna * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 1.1.2.2 gehenna * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 1.1.2.2 gehenna * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 1.1.2.2 gehenna * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 1.1.2.2 gehenna * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 1.1.2.2 gehenna * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 1.1.2.2 gehenna * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 1.1.2.2 gehenna * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 1.1.2.2 gehenna * SUCH DAMAGE. 34 1.1.2.2 gehenna */ 35 1.1.2.2 gehenna 36 1.1.2.2 gehenna #ifndef _IXP12X0REG_H_ 37 1.1.2.2 gehenna #define _IXP12X0REG_H_ 38 1.1.2.2 gehenna 39 1.1.2.2 gehenna /* 40 1.1.2.2 gehenna * Physical memory map for the Intel IXP12X0 41 1.1.2.2 gehenna */ 42 1.1.2.2 gehenna 43 1.1.2.2 gehenna /* 44 1.1.2.2 gehenna * FFFF FFFF --------------------------- 45 1.1.2.2 gehenna * Device 6 46 1.1.2.2 gehenna * SDRAM 47 1.1.2.2 gehenna * FF00 0000 - FF00 0014 48 1.1.2.2 gehenna * SDRAM Control Register 49 1.1.2.2 gehenna * D000 0000 - DFFF FFFF 50 1.1.2.2 gehenna * Prefetch 256MB 51 1.1.2.2 gehenna * C000 0000 - CFFF FFFF 52 1.1.2.2 gehenna * non-Prefetch 256MB 53 1.1.2.2 gehenna * C000 0000 --------------------------- 54 1.1.2.2 gehenna * Device 5 55 1.1.2.2 gehenna * AMBA Translation (ATU) 56 1.1.2.2 gehenna * B000 0000 --------------------------- 57 1.1.2.2 gehenna * Device 4 58 1.1.2.2 gehenna * Reserved 59 1.1.2.2 gehenna * A000 0000 --------------------------- 60 1.1.2.2 gehenna * Device 3 61 1.1.2.2 gehenna * StrongARM Core System 62 1.1.2.2 gehenna * 9000 0000 --------------------------- 63 1.1.2.2 gehenna * Device 2 64 1.1.2.2 gehenna * Reserved 65 1.1.2.2 gehenna * 8000 0000 --------------------------- 66 1.1.2.2 gehenna * Device 1 67 1.1.2.2 gehenna * PCI UNIT 68 1.1.2.2 gehenna * 6000 0000 - 7FFF FFFF 69 1.1.2.2 gehenna * PCI Memory Cycle Access 70 1.1.2.2 gehenna * 5400 0000 - 5400 FFFF 71 1.1.2.2 gehenna * PCI I/O Cycle Access 72 1.1.2.2 gehenna * 5300 0000 - 53FF FFFF 73 1.1.2.2 gehenna * PCI Type0 Configuration Cycle Access 74 1.1.2.2 gehenna * 5200 0000 - 52FF FFFF 75 1.1.2.2 gehenna * PCI Type1 Configuration Cycle Access 76 1.1.2.2 gehenna * 4200 0000 - 4200 03FF 77 1.1.2.2 gehenna * Local PCI Configuration Space 78 1.1.2.2 gehenna * 4000 0000 --------------------------- 79 1.1.2.2 gehenna * Device 0 80 1.1.2.2 gehenna * SRAM UNIT 81 1.1.2.2 gehenna * 0000 0000 --------------------------- 82 1.1.2.2 gehenna */ 83 1.1.2.2 gehenna 84 1.1.2.2 gehenna 85 1.1.2.2 gehenna /* 86 1.1.2.2 gehenna * Virtual memory map for the Intel IXP12X0 integrated devices 87 1.1.2.2 gehenna */ 88 1.1.2.2 gehenna 89 1.1.2.2 gehenna /* 90 1.1.2.2 gehenna * FFFF FFFF --------------------------- 91 1.1.2.2 gehenna * 92 1.1.2.2 gehenna * F002 1000 --------------------------- 93 1.1.2.2 gehenna * PCI Registers Accessible Through I/O 94 1.1.2.2 gehenna * VA F001 1000 == PA 5400 0000 (64kbyte) 95 1.1.2.2 gehenna * F001 1000 --------------------------- 96 1.1.2.2 gehenna * PCI Registers Accessible Through StrongARM Core 97 1.1.2.2 gehenna * VA F001 0000 == PA 4200 0000 (4kbyte) 98 1.1.2.2 gehenna * F001 0300 - F001 036F TIMER 99 1.1.2.2 gehenna * F001 0000 --------------------------- 100 1.1.2.2 gehenna * StrongARM System and Peripheral Registers 101 1.1.2.2 gehenna * VA F001 0000 == PA 9000 0000 (64kbyte) 102 1.1.2.2 gehenna * F000 3400 - F000 3C03 UART 103 1.1.2.2 gehenna * F000 3400 - F000 3C03 UART 104 1.1.2.2 gehenna * F000 2000 - F000 3003 RTC 105 1.1.2.2 gehenna * F000 1C00 - F000 1C03 GPIO_DATA 106 1.1.2.2 gehenna * F000 1800 - F000 1C03 GPIO 107 1.1.2.2 gehenna * F000 1400 - F000 1403 IRQ 108 1.1.2.2 gehenna * F000 1000 - F000 1003 FIQ 109 1.1.2.2 gehenna * F000 0C00 - F000 0C03 PLL_CFG 110 1.1.2.2 gehenna * F000 0000 --------------------------- 111 1.1.2.2 gehenna * Kernel text and data 112 1.1.2.2 gehenna * C000 0000 --------------------------- 113 1.1.2.2 gehenna * L2 tables for user process (XXX should be fixed) 114 1.1.2.2 gehenna * 6000 0000 --------------------------- 115 1.1.2.2 gehenna * PCI Registers Accessible Through Memory 116 1.1.2.2 gehenna * 5400 0000 --------------------------- 117 1.1.2.2 gehenna * PCI Type 0 Configuration Cycle Access 118 1.1.2.2 gehenna * VA 5400 0000 == PA 5400 0000 119 1.1.2.2 gehenna * 5300 0000 --------------------------- 120 1.1.2.2 gehenna * PCI Type 1 Configuration Cycle Access 121 1.1.2.2 gehenna * VA 5300 0000 == PA 5300 0000 122 1.1.2.2 gehenna * 5200 0000 --------------------------- 123 1.1.2.2 gehenna * 124 1.1.2.2 gehenna * 0000 0000 --------------------------- 125 1.1.2.2 gehenna * 126 1.1.2.2 gehenna */ 127 1.1.2.2 gehenna 128 1.1.2.2 gehenna 129 1.1.2.2 gehenna /* Virtual address for I/O space */ 130 1.1.2.2 gehenna #define IXP12X0_IO_VBASE 0xf0000000 131 1.1.2.2 gehenna 132 1.1.2.2 gehenna /* StrongARM System and Peripheral Registers */ 133 1.1.2.2 gehenna #define IXP12X0_SYS_VBASE IXP12X0_IO_VBASE 134 1.1.2.2 gehenna /* va=0xf0000000 */ 135 1.1.2.2 gehenna #define IXP12X0_SYS_HWBASE 0x90000000 136 1.1.2.2 gehenna #define IXP12X0_SYS_SIZE 0x00010000 /* 64Kbyte */ 137 1.1.2.2 gehenna 138 1.1.2.2 gehenna #define IXP12X0_PLL_CFG (IXP12X0_IO_VBASE + 0x0c00) 139 1.1.2.2 gehenna #define IXP12X0_PLL_CFG_CCF 0x1f 140 1.1.2.2 gehenna 141 1.1.2.2 gehenna /* PCI Registers Accessible Through StrongARM Core */ 142 1.1.2.2 gehenna #define IXP12X0_PCI_VBASE (IXP12X0_IO_VBASE + IXP12X0_SYS_SIZE) 143 1.1.2.2 gehenna /* va=0xf0010000 */ 144 1.1.2.2 gehenna #define IXP12X0_PCI_HWBASE 0x42000000 145 1.1.2.2 gehenna #define IXP12X0_PCI_SIZE 0x00001000 /* 4Kbyte */ 146 1.1.2.2 gehenna 147 1.1.2.2 gehenna /* PCI I/O Memory Space */ 148 1.1.2.2 gehenna #define IXP12X0_PCI_IO_VBASE (IXP12X0_PCI_VBASE + IXP12X0_PCI_SIZE) 149 1.1.2.2 gehenna /* va=0xf0011000 */ 150 1.1.2.2 gehenna #define IXP12X0_PCI_IO_HWBASE 0x54000000 151 1.1.2.2 gehenna #define IXP12X0_PCI_IO_SIZE 0x00010000 /* 64Kbyte */ 152 1.1.2.2 gehenna 153 1.1.2.2 gehenna #define IXP12X0_PCI_MEM_VBASE 0x60000000 /* VA == PA */ 154 1.1.2.2 gehenna #define IXP12X0_PCI_MEM_SIZE 0x20000000 155 1.1.2.2 gehenna 156 1.1.2.2 gehenna /* PCI Type0/1 Configuration address */ 157 1.1.2.2 gehenna #define IXP12X0_PCI_TYPEX_SIZE 0x01000000 158 1.1.2.2 gehenna 159 1.1.2.2 gehenna #define IXP12X0_PCI_TYPE0_VBASE 0x53000000 /* VA == PA */ 160 1.1.2.2 gehenna #define IXP12X0_PCI_TYPE1_VBASE 0x52000000 161 1.1.2.2 gehenna 162 1.1.2.2 gehenna /* 163 1.1.2.2 gehenna * SlowPort I/O Register 164 1.1.2.2 gehenna */ 165 1.1.2.2 gehenna /* see. arch/evbarm/ixm1200/ixm1200reg.h */ 166 1.1.2.2 gehenna 167 1.1.2.2 gehenna /* Physical register base addresses */ 168 1.1.2.2 gehenna /* #define IXP12X0_GPIO_VBASE */ 169 1.1.2.2 gehenna #define IXP12X0_GPIO_HWBASE 0x90001800 170 1.1.2.2 gehenna #define IXP12X0_GPIO_SIZE 0x00000800 171 1.1.2.2 gehenna 172 1.1.2.2 gehenna /* Interrupts */ 173 1.1.2.2 gehenna #define IXP12X0_FIQ_VBASE (IXP12X0_IO_VBASE + 0x1000) 174 1.1.2.2 gehenna #define IXP12X0_FIQ_HWBASE 0x90001000 175 1.1.2.2 gehenna #define IXP12X0_FIQ_SIZE 0x00000004 176 1.1.2.2 gehenna #define IXP12X0_IRQ_VBASE (IXP12X0_IO_VBASE + 0x1400) 177 1.1.2.2 gehenna #define IXP12X0_IRQ_HWBASE 0x90001400 178 1.1.2.2 gehenna #define IXP12X0_IRQ_SIZE 0x00000004 179 1.1.2.2 gehenna 180 1.1.2.2 gehenna /* 181 1.1.2.2 gehenna * Interrupt index assignment 182 1.1.2.2 gehenna * 183 1.1.2.2 gehenna * 184 1.1.2.2 gehenna * FIQ/IRQ bitmap in "StrongARM System and Peripheral Registers" 185 1.1.2.2 gehenna * 186 1.1.2.2 gehenna * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 187 1.1.2.2 gehenna * bit 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 188 1.1.2.2 gehenna * +-+-------------------------------------------+-+-+-+-+-+-+-+---+ 189 1.1.2.2 gehenna * |M| |U|S|R|S|U|C|P| | 190 1.1.2.2 gehenna * |B| |A|D|T|R|E|I|C| | 191 1.1.2.2 gehenna * |Z| RES |R|R|C|A|N|N|I|RES| 192 1.1.2.2 gehenna * | | |T|A| |M|G|T| | | 193 1.1.2.2 gehenna * | | | |M| | | | | | | 194 1.1.2.2 gehenna * +-+-------------------------------------------+-+-+-+-+-+-+-+---+ 195 1.1.2.2 gehenna * 3 196 1.1.2.2 gehenna * index 1 8 7 6 5 4 3 2 197 1.1.2.2 gehenna * 198 1.1.2.2 gehenna * 199 1.1.2.2 gehenna * We Map a software interrupt queue index to the unused bits in the 200 1.1.2.2 gehenna * IRQ/FIQ registers. (in "StrongARM System and Peripheral Registers") 201 1.1.2.2 gehenna * 202 1.1.2.2 gehenna * XXX will need to revisit this if those bits are ever used in future 203 1.1.2.2 gehenna * steppings). 204 1.1.2.2 gehenna * 205 1.1.2.2 gehenna * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 206 1.1.2.2 gehenna * bit 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 207 1.1.2.2 gehenna * +-+-+-+-+-+-----------------------------------+-+-+-+-+-+-+-+---+ 208 1.1.2.2 gehenna * |M|S|C|N|S| |U|S|R|S|U|C|P| | 209 1.1.2.2 gehenna * |B|O|L|E|E| |A|D|T|R|E|I|C| | 210 1.1.2.2 gehenna * |Z|F|O|T|R| RES |R|R|C|A|N|N|I|RES| 211 1.1.2.2 gehenna * | |T|C| |I| |T|A| |M|G|T| | | 212 1.1.2.2 gehenna * | | |K| |A| | |M| | | | | | | 213 1.1.2.2 gehenna * | | | | |L| | | | | | | | | | 214 1.1.2.2 gehenna * +-+-+-+-+-+-----------------------------------+-+-+-+-+-+-+-+---+ 215 1.1.2.2 gehenna * 3 3 2 2 2 216 1.1.2.2 gehenna * index 1 0 9 8 7 8 7 6 5 4 3 2 217 1.1.2.2 gehenna * 218 1.1.2.2 gehenna */ 219 1.1.2.2 gehenna 220 1.1.2.2 gehenna #define NIRQ 64 221 1.1.2.2 gehenna #define SYS_NIRQ 32 222 1.1.2.2 gehenna 223 1.1.2.2 gehenna #define IXP12X0_INTR_MBZ 31 224 1.1.2.2 gehenna #define IXP12X0_INTR_bit30 30 225 1.1.2.2 gehenna #define IXP12X0_INTR_bit29 29 226 1.1.2.2 gehenna #define IXP12X0_INTR_bit28 28 227 1.1.2.2 gehenna #define IXP12X0_INTR_bit27 27 228 1.1.2.2 gehenna #define IXP12X0_INTR_bit26 26 229 1.1.2.2 gehenna #define IXP12X0_INTR_bit25 25 230 1.1.2.2 gehenna #define IXP12X0_INTR_bit24 24 231 1.1.2.2 gehenna #define IXP12X0_INTR_bit23 23 232 1.1.2.2 gehenna #define IXP12X0_INTR_bit22 22 233 1.1.2.2 gehenna #define IXP12X0_INTR_bit21 21 234 1.1.2.2 gehenna #define IXP12X0_INTR_bit20 20 235 1.1.2.2 gehenna #define IXP12X0_INTR_bit19 19 236 1.1.2.2 gehenna #define IXP12X0_INTR_bit18 18 237 1.1.2.2 gehenna #define IXP12X0_INTR_bit17 17 238 1.1.2.2 gehenna #define IXP12X0_INTR_bit16 16 239 1.1.2.2 gehenna #define IXP12X0_INTR_bit15 15 240 1.1.2.2 gehenna #define IXP12X0_INTR_bit14 14 241 1.1.2.2 gehenna #define IXP12X0_INTR_bit13 13 242 1.1.2.2 gehenna #define IXP12X0_INTR_bit12 12 243 1.1.2.2 gehenna #define IXP12X0_INTR_bit11 11 244 1.1.2.2 gehenna #define IXP12X0_INTR_bit10 10 245 1.1.2.2 gehenna #define IXP12X0_INTR_bit9 9 246 1.1.2.2 gehenna #define IXP12X0_INTR_UART 8 247 1.1.2.2 gehenna #define IXP12X0_INTR_SDRAM 7 248 1.1.2.2 gehenna #define IXP12X0_INTR_RTC 6 249 1.1.2.2 gehenna #define IXP12X0_INTR_SRAM 5 250 1.1.2.2 gehenna #define IXP12X0_INTR_UENG 4 251 1.1.2.2 gehenna #define IXP12X0_INTR_CINT 3 252 1.1.2.2 gehenna #define IXP12X0_INTR_PCI 2 253 1.1.2.2 gehenna #define IXP12X0_INTR_bit1 1 254 1.1.2.2 gehenna #define IXP12X0_INTR_bit0 0 255 1.1.2.2 gehenna 256 1.1.2.2 gehenna #define IXP12X0_INTR_MASK \ 257 1.1.2.2 gehenna ((1U << IXP12X0_INTR_MBZ) \ 258 1.1.2.2 gehenna | (1U << IXP12X0_INTR_UART) \ 259 1.1.2.2 gehenna | (1U << IXP12X0_INTR_SDRAM) \ 260 1.1.2.2 gehenna | (1U << IXP12X0_INTR_RTC) \ 261 1.1.2.2 gehenna | (1U << IXP12X0_INTR_SRAM) \ 262 1.1.2.2 gehenna | (1U << IXP12X0_INTR_UENG) \ 263 1.1.2.2 gehenna | (1U << IXP12X0_INTR_CINT)) 264 1.1.2.2 gehenna 265 1.1.2.2 gehenna #endif /* _IXP12X0REG_H_ */ 266
Indexes created Fri Oct 31 11:10:07 GMT 2025