ixp12x0reg.h revision 1.5
1 /* $NetBSD: ixp12x0reg.h,v 1.5 2003/11/10 08:51:51 wiz Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 5 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #ifndef _IXP12X0REG_H_ 37 #define _IXP12X0REG_H_ 38 39 /* 40 * Physical memory map for the Intel IXP12X0 41 */ 42 43 /* 44 * FFFF FFFF --------------------------- 45 * Device 6 46 * SDRAM 47 * FF00 0000 - FF00 0014 48 * SDRAM Control Register 49 * D000 0000 - DFFF FFFF 50 * Prefetch 256MB 51 * C000 0000 - CFFF FFFF 52 * non-Prefetch 256MB 53 * C000 0000 --------------------------- 54 * Device 5 55 * AMBA Translation (ATU) 56 * B000 0000 --------------------------- 57 * Device 4 58 * Reserved 59 * A000 0000 --------------------------- 60 * Device 3 61 * StrongARM Core System 62 * 9000 0000 --------------------------- 63 * Device 2 64 * Reserved 65 * 8000 0000 --------------------------- 66 * Device 1 67 * PCI UNIT 68 * 6000 0000 - 7FFF FFFF 69 * PCI Memory Cycle Access 70 * 5400 0000 - 5400 FFFF 71 * PCI I/O Cycle Access 72 * 5300 0000 - 53BF FFFF 73 * PCI Type0 Configuration Cycle Access 74 * 5200 0000 - 52FF FFFF 75 * PCI Type1 Configuration Cycle Access 76 * 4200 0000 - 4200 03FF 77 * Local PCI Configuration Space 78 * 4000 0000 --------------------------- 79 * Device 0 80 * SRAM UNIT 81 * 0000 0000 --------------------------- 82 */ 83 84 85 /* 86 * Virtual memory map for the Intel IXP12X0 integrated devices 87 * 88 * IXP12x0 processors have many device registers at very lower addresses. 89 * To make user process space wider, we map the registers at lower address 90 * to upper address using address translation of virtual memory system. 91 * 92 * Some device registers are staticaly mapped on upper address region. 93 * because we have to access them before bus_space is initialized. 94 * Most device is dinamicaly mapped by bus_space_map(). In this case, 95 * the actual mapped (virtual) address are not cared by device drivers. 96 */ 97 98 /* 99 * FFFF FFFF --------------------------- 100 * 101 * F400 0000 --------------------------- 102 * PCI Type 0 Configuration Cycle Access 103 * VA F300 0000 == PA 5300 0000 (16Mbyte) 104 * F300 0000 --------------------------- 105 * PCI Type 1 Configuration Cycle Access 106 * VA F200 0000 == PA 5200 0000 (16Mbyte) 107 * F200 0000 --------------------------- 108 * not used 109 * F020 0000 --------------------------- 110 * PCI Registers Accessible Through I/O 111 * VA F010 0000 == PA 5400 0000 (1Mbyte) 112 * F010 0000 --------------------------- 113 * not used 114 * F001 1000 --------------------------- 115 * PCI Registers Accessible Through StrongARM Core 116 * VA F001 0000 == PA 4200 0000 (4kbyte) 117 * F001 0300 - F001 036F TIMER 118 * F001 0200 - F001 0293 PCI_FIQ 119 * F001 0180 - F001 0193 PCI_IRQ 120 * F001 0000 --------------------------- 121 * StrongARM System and Peripheral Registers 122 * VA F000 0000 == PA 9000 0000 (64kbyte) 123 * F000 3400 - F000 3C03 UART 124 * F000 3400 - F000 3C03 UART 125 * F000 2000 - F000 3003 RTC 126 * F000 1C00 - F000 1C03 GPIO_DATA 127 * F000 1800 - F000 1C03 GPIO 128 * F000 1400 - F000 1403 IRQ 129 * F000 1000 - F000 1003 FIQ 130 * F000 0C00 - F000 0C03 PLL_CFG (not used at this addres) 131 * F000 0000 --------------------------- 132 * Kernel text and data 133 * C000 0000 --------------------------- 134 * L2 tables for user process (XXX should be fixed) 135 * 8000 0000 --------------------------- 136 * PCI Registers Accessible Through Memory 137 * VA 6000 0000 == PA 6000 0000 (512Mbyte) 138 * 6000 0000 --------------------------- 139 * 5400 0000 --------------------------- 140 * 0000 0000 --------------------------- 141 * 142 */ 143 144 /* Virtual address for I/O space */ 145 #define IXP12X0_IO_VBASE 0xf0000000UL 146 147 /* StrongARM System and Peripheral Registers */ 148 #define IXP12X0_SYS_VBASE 0xf0000000UL 149 #define IXP12X0_SYS_HWBASE 0x90000000UL 150 #define IXP12X0_SYS_SIZE 0x00010000UL /* 64Kbyte */ 151 152 #define IXP12X0_PLL_CFG (IXP12X0_IO_VBASE + 0x0c00) 153 #define IXP12X0_PLL_CFG_CCF 0x1f 154 155 /* PCI Registers Accessible Through StrongARM Core */ 156 #define IXP12X0_PCI_VBASE 0xf0010000UL 157 #define IXP12X0_PCI_HWBASE 0x42000000UL 158 #define IXP12X0_PCI_SIZE 0x00001000UL /* 4Kbyte */ 159 160 /* PCI I/O Space */ 161 #define IXP12X0_PCI_IO_VBASE 0xf0100000UL 162 #define IXP12X0_PCI_IO_HWBASE 0x54000000UL 163 #define IXP12X0_PCI_IO_SIZE 0x00100000UL /* 1Mbyte */ 164 165 /* PCI Memory Space */ 166 #define IXP12X0_PCI_MEM_HWBASE 0x60000000UL /* VA == PA */ 167 #define IXP12X0_PCI_MEM_VBASE IXP12X0_PCI_MEM_HWBASE 168 #define IXP12X0_PCI_MEM_SIZE 0x20000000UL 169 170 /* PCI Type0/1 Configuration address */ 171 #define IXP12X0_PCI_TYPE0_HWBASE 0x53000000UL 172 #define IXP12X0_PCI_TYPE0_VBASE 0xf3000000UL 173 #define IXP12X0_PCI_TYPE0_SIZE 0x01000000UL /* 16MB */ 174 175 #define IXP12X0_PCI_TYPE1_HWBASE 0x52000000UL 176 #define IXP12X0_PCI_TYPE1_VBASE 0xf2000000UL 177 #define IXP12X0_PCI_TYPE1_SIZE 0x01000000UL /* 16MB */ 178 179 /* 180 * SlowPort I/O Register 181 */ 182 /* see. arch/evbarm/ixm1200/ixm1200reg.h */ 183 184 /* Physical register base addresses */ 185 /* #define IXP12X0_GPIO_VBASE */ 186 #define IXP12X0_GPIO_HWBASE 0x90001800UL 187 #define IXP12X0_GPIO_SIZE 0x00000800UL 188 189 /* Interrupts */ 190 #define IXP12X0_FIQ_VBASE (IXP12X0_IO_VBASE + 0x1000) 191 #define IXP12X0_FIQ_HWBASE 0x90001000UL 192 #define IXP12X0_FIQ_SIZE 0x00000004UL 193 #define IXP12X0_IRQ_VBASE (IXP12X0_IO_VBASE + 0x1400) 194 #define IXP12X0_IRQ_HWBASE 0x90001400UL 195 #define IXP12X0_IRQ_SIZE 0x00000004UL 196 197 /* 198 * Interrupt index assignment 199 * 200 * 201 * FIQ/IRQ bitmap in "StrongARM System and Peripheral Registers" 202 * 203 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 204 * bit 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 205 * +-+-------------------------------------------+-+-+-+-+-+-+-+---+ 206 * |M| |U|S|R|S|U|C|P| | 207 * |B| |A|D|T|R|E|I|C| | 208 * |Z| RES |R|R|C|A|N|N|I|RES| 209 * | | |T|A| |M|G|T| | | 210 * | | | |M| | | | | | | 211 * +-+-------------------------------------------+-+-+-+-+-+-+-+---+ 212 * 3 213 * index 1 8 7 6 5 4 3 2 214 * 215 * 216 * We Map a software interrupt queue index to the unused bits in the 217 * IRQ/FIQ registers. (in "StrongARM System and Peripheral Registers") 218 * 219 * XXX will need to revisit this if those bits are ever used in future 220 * steppings). 221 * 222 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 223 * bit 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 224 * +-+-+-+-+-+-----------------------------------+-+-+-+-+-+-+-+---+ 225 * |M|S|C|N|S| |U|S|R|S|U|C|P| | 226 * |B|O|L|E|E| |A|D|T|R|E|I|C| | 227 * |Z|F|O|T|R| RES |R|R|C|A|N|N|I|RES| 228 * | |T|C| |I| |T|A| |M|G|T| | | 229 * | | |K| |A| | |M| | | | | | | 230 * | | | | |L| | | | | | | | | | 231 * +-+-+-+-+-+-----------------------------------+-+-+-+-+-+-+-+---+ 232 * 3 3 2 2 2 233 * index 1 0 9 8 7 8 7 6 5 4 3 2 234 * 235 */ 236 237 #define NIRQ 64 238 #define SYS_NIRQ 32 239 240 #define IXP12X0_INTR_MBZ 31 241 #define IXP12X0_INTR_bit30 30 242 #define IXP12X0_INTR_bit29 29 243 #define IXP12X0_INTR_bit28 28 244 #define IXP12X0_INTR_bit27 27 245 #define IXP12X0_INTR_bit26 26 246 #define IXP12X0_INTR_bit25 25 247 #define IXP12X0_INTR_bit24 24 248 #define IXP12X0_INTR_bit23 23 249 #define IXP12X0_INTR_bit22 22 250 #define IXP12X0_INTR_bit21 21 251 #define IXP12X0_INTR_bit20 20 252 #define IXP12X0_INTR_bit19 19 253 #define IXP12X0_INTR_bit18 18 254 #define IXP12X0_INTR_bit17 17 255 #define IXP12X0_INTR_bit16 16 256 #define IXP12X0_INTR_bit15 15 257 #define IXP12X0_INTR_bit14 14 258 #define IXP12X0_INTR_bit13 13 259 #define IXP12X0_INTR_bit12 12 260 #define IXP12X0_INTR_bit11 11 261 #define IXP12X0_INTR_bit10 10 262 #define IXP12X0_INTR_bit9 9 263 #define IXP12X0_INTR_UART 8 264 #define IXP12X0_INTR_SDRAM 7 265 #define IXP12X0_INTR_RTC 6 266 #define IXP12X0_INTR_SRAM 5 267 #define IXP12X0_INTR_UENG 4 268 #define IXP12X0_INTR_CINT 3 269 #define IXP12X0_INTR_PCI 2 270 #define IXP12X0_INTR_bit1 1 271 #define IXP12X0_INTR_bit0 0 272 273 #define IXP12X0_INTR_MASK \ 274 ((1U << IXP12X0_INTR_MBZ) \ 275 | (1U << IXP12X0_INTR_UART) \ 276 | (1U << IXP12X0_INTR_SDRAM) \ 277 | (1U << IXP12X0_INTR_RTC) \ 278 | (1U << IXP12X0_INTR_SRAM) \ 279 | (1U << IXP12X0_INTR_UENG) \ 280 | (1U << IXP12X0_INTR_CINT)) 281 282 #endif /* _IXP12X0REG_H_ */ 283
Indexes created Fri Oct 03 02:09:57 GMT 2025