ixp12x0var.h revision 1.1.4.2
1 1.1.4.2 nathanw /* $NetBSD: ixp12x0var.h,v 1.1.4.2 2002/10/18 02:35:37 nathanw Exp $ */ 2 1.1.4.2 nathanw /* 3 1.1.4.2 nathanw * Copyright (c) 2002 4 1.1.4.2 nathanw * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 5 1.1.4.2 nathanw * All rights reserved. 6 1.1.4.2 nathanw * 7 1.1.4.2 nathanw * Redistribution and use in source and binary forms, with or without 8 1.1.4.2 nathanw * modification, are permitted provided that the following conditions 9 1.1.4.2 nathanw * are met: 10 1.1.4.2 nathanw * 1. Redistributions of source code must retain the above copyright 11 1.1.4.2 nathanw * notice, this list of conditions and the following disclaimer. 12 1.1.4.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.4.2 nathanw * notice, this list of conditions and the following disclaimer in the 14 1.1.4.2 nathanw * documentation and/or other materials provided with the distribution. 15 1.1.4.2 nathanw * 3. All advertising materials mentioning features or use of this software 16 1.1.4.2 nathanw * must display the following acknowledgement: 17 1.1.4.2 nathanw * This product includes software developed by Ichiro FUKUHARA. 18 1.1.4.2 nathanw * 4. The name of the company nor the name of the author may be used to 19 1.1.4.2 nathanw * endorse or promote products derived from this software without specific 20 1.1.4.2 nathanw * prior written permission. 21 1.1.4.2 nathanw * 22 1.1.4.2 nathanw * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 23 1.1.4.2 nathanw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 1.1.4.2 nathanw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 1.1.4.2 nathanw * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 26 1.1.4.2 nathanw * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 1.1.4.2 nathanw * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 1.1.4.2 nathanw * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 1.1.4.2 nathanw * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 1.1.4.2 nathanw * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 1.1.4.2 nathanw * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 1.1.4.2 nathanw * SUCH DAMAGE. 33 1.1.4.2 nathanw */ 34 1.1.4.2 nathanw 35 1.1.4.2 nathanw #ifndef _IXP12X0VAR_H_ 36 1.1.4.2 nathanw #define _IXP12X0VAR_H_ 37 1.1.4.2 nathanw 38 1.1.4.2 nathanw #include <sys/conf.h> 39 1.1.4.2 nathanw #include <sys/device.h> 40 1.1.4.2 nathanw #include <sys/queue.h> 41 1.1.4.2 nathanw 42 1.1.4.2 nathanw #include <machine/bus.h> 43 1.1.4.2 nathanw 44 1.1.4.2 nathanw #include <dev/pci/pcivar.h> 45 1.1.4.2 nathanw 46 1.1.4.2 nathanw #define IXPREG(reg) *((volatile u_int32_t*) (reg)) 47 1.1.4.2 nathanw 48 1.1.4.2 nathanw struct ixp12x0_softc { 49 1.1.4.2 nathanw struct device sc_dev; 50 1.1.4.2 nathanw bus_space_tag_t sc_iot; 51 1.1.4.2 nathanw bus_space_handle_t sc_ioh; /* IRQ handle */ 52 1.1.4.2 nathanw 53 1.1.4.2 nathanw u_int32_t sc_intrmask; 54 1.1.4.2 nathanw 55 1.1.4.2 nathanw /* Handles for the various subregions. */ 56 1.1.4.2 nathanw bus_space_handle_t sc_pci_ioh; 57 1.1.4.2 nathanw 58 1.1.4.2 nathanw /* I/O window vaddr */ 59 1.1.4.2 nathanw 60 1.1.4.2 nathanw /* PCI address */ 61 1.1.4.2 nathanw 62 1.1.4.2 nathanw /* Bus space, DMA, and PCI tags for the PCI bus */ 63 1.1.4.2 nathanw struct bus_space ia_pci_iot; 64 1.1.4.2 nathanw struct bus_space ia_pci_memt; 65 1.1.4.2 nathanw struct arm32_bus_dma_tag ia_pci_dmat; 66 1.1.4.2 nathanw struct arm32_pci_chipset ia_pci_chipset; 67 1.1.4.2 nathanw 68 1.1.4.2 nathanw /* GPIO */ 69 1.1.4.2 nathanw }; 70 1.1.4.2 nathanw 71 1.1.4.2 nathanw struct intrhand { 72 1.1.4.2 nathanw TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */ 73 1.1.4.2 nathanw int (*ih_func)(void *); /* interrupt handler */ 74 1.1.4.2 nathanw void *ih_arg; /* arg for handler */ 75 1.1.4.2 nathanw int ih_ipl; /* IPL_* */ 76 1.1.4.2 nathanw int ih_irq; /* IRQ number */ 77 1.1.4.2 nathanw }; 78 1.1.4.2 nathanw 79 1.1.4.2 nathanw #define IRQNAMESIZE sizeof("ixpintr ipl xxx") 80 1.1.4.2 nathanw 81 1.1.4.2 nathanw struct intrq { 82 1.1.4.2 nathanw TAILQ_HEAD(, intrhand) iq_list; /* handler list */ 83 1.1.4.2 nathanw struct evcnt iq_ev; /* event counter */ 84 1.1.4.2 nathanw u_int32_t iq_mask; /* IRQs to mask while handling */ 85 1.1.4.2 nathanw u_int32_t iq_pci_mask; /* PCI IRQs to mask while handling */ 86 1.1.4.2 nathanw u_int32_t iq_levels; /* IPL_*'s this IRQ has */ 87 1.1.4.2 nathanw char iq_name[IRQNAMESIZE]; /* interrupt name */ 88 1.1.4.2 nathanw }; 89 1.1.4.2 nathanw 90 1.1.4.2 nathanw struct pmap_ent { 91 1.1.4.2 nathanw const char* msg; 92 1.1.4.2 nathanw vaddr_t va; 93 1.1.4.2 nathanw paddr_t pa; 94 1.1.4.2 nathanw vsize_t sz; 95 1.1.4.2 nathanw int prot; 96 1.1.4.2 nathanw int cache; 97 1.1.4.2 nathanw }; 98 1.1.4.2 nathanw 99 1.1.4.2 nathanw void ixp12x0_bs_init(bus_space_tag_t, void *); 100 1.1.4.2 nathanw void ixp12x0_io_bs_init(bus_space_tag_t, void *); 101 1.1.4.2 nathanw void ixp12x0_mem_bs_init(bus_space_tag_t, void *); 102 1.1.4.2 nathanw void ixp12x0_pci_init(pci_chipset_tag_t, void *); 103 1.1.4.2 nathanw void ixp12x0_pci_dma_init(bus_dma_tag_t, void *); 104 1.1.4.2 nathanw void ixp12x0_attach(struct ixp12x0_softc *); 105 1.1.4.2 nathanw void ixp12x0_intr_init(void); 106 1.1.4.2 nathanw void *ixp12x0_intr_establish(int irq, int ipl, int (*)(void *), void *); 107 1.1.4.2 nathanw void ixp12x0_intr_disestablish(void *); 108 1.1.4.2 nathanw void ixp12x0_pmap_chunk_table(vaddr_t l1pt, struct pmap_ent* m); 109 1.1.4.2 nathanw void ixp12x0_pmap_io_reg(vaddr_t l1pt); 110 1.1.4.2 nathanw void ixp12x0_reset(void); 111 1.1.4.2 nathanw 112 1.1.4.2 nathanw #endif /* _IXP12X0VAR_H_ */ 113
Indexes created Sat Nov 01 05:10:12 GMT 2025