mainbus_io.c revision 1.5.4.6
1 1.5.4.6 nathanw /* $NetBSD: mainbus_io.c,v 1.5.4.6 2002/10/18 02:35:38 nathanw Exp $ */ 2 1.5.4.2 nathanw 3 1.5.4.2 nathanw /* 4 1.5.4.2 nathanw * Copyright (c) 1997 Mark Brinicombe. 5 1.5.4.2 nathanw * All rights reserved. 6 1.5.4.2 nathanw * 7 1.5.4.2 nathanw * Redistribution and use in source and binary forms, with or without 8 1.5.4.2 nathanw * modification, are permitted provided that the following conditions 9 1.5.4.2 nathanw * are met: 10 1.5.4.2 nathanw * 1. Redistributions of source code must retain the above copyright 11 1.5.4.2 nathanw * notice, this list of conditions and the following disclaimer. 12 1.5.4.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 13 1.5.4.2 nathanw * notice, this list of conditions and the following disclaimer in the 14 1.5.4.2 nathanw * documentation and/or other materials provided with the distribution. 15 1.5.4.2 nathanw * 3. All advertising materials mentioning features or use of this software 16 1.5.4.2 nathanw * must display the following acknowledgement: 17 1.5.4.2 nathanw * This product includes software developed by Mark Brinicombe. 18 1.5.4.2 nathanw * 4. The name of the company nor the name of the author may be used to 19 1.5.4.2 nathanw * endorse or promote products derived from this software without specific 20 1.5.4.2 nathanw * prior written permission. 21 1.5.4.2 nathanw * 22 1.5.4.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 23 1.5.4.2 nathanw * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 1.5.4.2 nathanw * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 1.5.4.2 nathanw * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 26 1.5.4.2 nathanw * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 1.5.4.2 nathanw * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 1.5.4.2 nathanw * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 1.5.4.2 nathanw * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 1.5.4.2 nathanw * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 1.5.4.2 nathanw * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 1.5.4.2 nathanw * SUCH DAMAGE. 33 1.5.4.2 nathanw */ 34 1.5.4.2 nathanw 35 1.5.4.2 nathanw /* 36 1.5.4.2 nathanw * bus_space I/O functions for mainbus 37 1.5.4.2 nathanw */ 38 1.5.4.2 nathanw 39 1.5.4.2 nathanw #include <sys/param.h> 40 1.5.4.2 nathanw #include <sys/systm.h> 41 1.5.4.2 nathanw #include <sys/queue.h> 42 1.5.4.2 nathanw 43 1.5.4.2 nathanw #include <uvm/uvm.h> 44 1.5.4.2 nathanw 45 1.5.4.2 nathanw #include <machine/bus.h> 46 1.5.4.2 nathanw #include <machine/pmap.h> 47 1.5.4.2 nathanw 48 1.5.4.2 nathanw /* Proto types for all the bus_space structure functions */ 49 1.5.4.2 nathanw 50 1.5.4.2 nathanw bs_protos(mainbus); 51 1.5.4.2 nathanw bs_protos(bs_notimpl); 52 1.5.4.2 nathanw 53 1.5.4.2 nathanw /* Declare the mainbus bus space tag */ 54 1.5.4.2 nathanw 55 1.5.4.2 nathanw struct bus_space mainbus_bs_tag = { 56 1.5.4.2 nathanw /* cookie */ 57 1.5.4.2 nathanw NULL, 58 1.5.4.2 nathanw 59 1.5.4.2 nathanw /* mapping/unmapping */ 60 1.5.4.2 nathanw mainbus_bs_map, 61 1.5.4.2 nathanw mainbus_bs_unmap, 62 1.5.4.2 nathanw mainbus_bs_subregion, 63 1.5.4.2 nathanw 64 1.5.4.2 nathanw /* allocation/deallocation */ 65 1.5.4.2 nathanw mainbus_bs_alloc, 66 1.5.4.2 nathanw mainbus_bs_free, 67 1.5.4.2 nathanw 68 1.5.4.2 nathanw /* get kernel virtual address */ 69 1.5.4.2 nathanw 0, /* there is no linear mapping */ 70 1.5.4.2 nathanw 71 1.5.4.2 nathanw /* Mmap bus space for user */ 72 1.5.4.2 nathanw mainbus_bs_mmap, 73 1.5.4.2 nathanw 74 1.5.4.2 nathanw /* barrier */ 75 1.5.4.2 nathanw mainbus_bs_barrier, 76 1.5.4.2 nathanw 77 1.5.4.2 nathanw /* read (single) */ 78 1.5.4.2 nathanw mainbus_bs_r_1, 79 1.5.4.2 nathanw mainbus_bs_r_2, 80 1.5.4.2 nathanw mainbus_bs_r_4, 81 1.5.4.2 nathanw bs_notimpl_bs_r_8, 82 1.5.4.2 nathanw 83 1.5.4.2 nathanw /* read multiple */ 84 1.5.4.2 nathanw bs_notimpl_bs_rm_1, 85 1.5.4.2 nathanw mainbus_bs_rm_2, 86 1.5.4.2 nathanw bs_notimpl_bs_rm_4, 87 1.5.4.2 nathanw bs_notimpl_bs_rm_8, 88 1.5.4.2 nathanw 89 1.5.4.2 nathanw /* read region */ 90 1.5.4.2 nathanw bs_notimpl_bs_rr_1, 91 1.5.4.2 nathanw bs_notimpl_bs_rr_2, 92 1.5.4.2 nathanw bs_notimpl_bs_rr_4, 93 1.5.4.2 nathanw bs_notimpl_bs_rr_8, 94 1.5.4.2 nathanw 95 1.5.4.2 nathanw /* write (single) */ 96 1.5.4.2 nathanw mainbus_bs_w_1, 97 1.5.4.2 nathanw mainbus_bs_w_2, 98 1.5.4.2 nathanw mainbus_bs_w_4, 99 1.5.4.2 nathanw bs_notimpl_bs_w_8, 100 1.5.4.2 nathanw 101 1.5.4.2 nathanw /* write multiple */ 102 1.5.4.2 nathanw mainbus_bs_wm_1, 103 1.5.4.2 nathanw mainbus_bs_wm_2, 104 1.5.4.2 nathanw bs_notimpl_bs_wm_4, 105 1.5.4.2 nathanw bs_notimpl_bs_wm_8, 106 1.5.4.2 nathanw 107 1.5.4.2 nathanw /* write region */ 108 1.5.4.2 nathanw bs_notimpl_bs_wr_1, 109 1.5.4.2 nathanw bs_notimpl_bs_wr_2, 110 1.5.4.2 nathanw bs_notimpl_bs_wr_4, 111 1.5.4.2 nathanw bs_notimpl_bs_wr_8, 112 1.5.4.2 nathanw 113 1.5.4.2 nathanw bs_notimpl_bs_sm_1, 114 1.5.4.2 nathanw bs_notimpl_bs_sm_2, 115 1.5.4.2 nathanw bs_notimpl_bs_sm_4, 116 1.5.4.2 nathanw bs_notimpl_bs_sm_8, 117 1.5.4.2 nathanw 118 1.5.4.2 nathanw /* set region */ 119 1.5.4.2 nathanw bs_notimpl_bs_sr_1, 120 1.5.4.2 nathanw bs_notimpl_bs_sr_2, 121 1.5.4.2 nathanw bs_notimpl_bs_sr_4, 122 1.5.4.2 nathanw bs_notimpl_bs_sr_8, 123 1.5.4.2 nathanw 124 1.5.4.2 nathanw /* copy */ 125 1.5.4.2 nathanw bs_notimpl_bs_c_1, 126 1.5.4.2 nathanw bs_notimpl_bs_c_2, 127 1.5.4.2 nathanw bs_notimpl_bs_c_4, 128 1.5.4.2 nathanw bs_notimpl_bs_c_8, 129 1.5.4.2 nathanw }; 130 1.5.4.2 nathanw 131 1.5.4.2 nathanw /* bus space functions */ 132 1.5.4.2 nathanw 133 1.5.4.2 nathanw int 134 1.5.4.2 nathanw mainbus_bs_map(t, bpa, size, cacheable, bshp) 135 1.5.4.2 nathanw void *t; 136 1.5.4.2 nathanw bus_addr_t bpa; 137 1.5.4.2 nathanw bus_size_t size; 138 1.5.4.2 nathanw int cacheable; 139 1.5.4.2 nathanw bus_space_handle_t *bshp; 140 1.5.4.2 nathanw { 141 1.5.4.2 nathanw u_long startpa, endpa, pa; 142 1.5.4.2 nathanw vaddr_t va; 143 1.5.4.2 nathanw pt_entry_t *pte; 144 1.5.4.2 nathanw 145 1.5.4.3 nathanw if ((u_long)bpa > (u_long)KERNEL_BASE) { 146 1.5.4.2 nathanw /* XXX This is a temporary hack to aid transition. */ 147 1.5.4.2 nathanw *bshp = bpa; 148 1.5.4.2 nathanw return(0); 149 1.5.4.2 nathanw } 150 1.5.4.2 nathanw 151 1.5.4.2 nathanw startpa = trunc_page(bpa); 152 1.5.4.2 nathanw endpa = round_page(bpa + size); 153 1.5.4.2 nathanw 154 1.5.4.2 nathanw /* XXX use extent manager to check duplicate mapping */ 155 1.5.4.2 nathanw 156 1.5.4.2 nathanw va = uvm_km_valloc(kernel_map, endpa - startpa); 157 1.5.4.2 nathanw if (! va) 158 1.5.4.2 nathanw return(ENOMEM); 159 1.5.4.2 nathanw 160 1.5.4.2 nathanw *bshp = (bus_space_handle_t)(va + (bpa - startpa)); 161 1.5.4.2 nathanw 162 1.5.4.2 nathanw for(pa = startpa; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) { 163 1.5.4.2 nathanw pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE); 164 1.5.4.3 nathanw pte = vtopte(va); 165 1.5.4.5 thorpej if (cacheable == 0) { 166 1.5.4.4 nathanw *pte &= ~L2_S_CACHE_MASK; 167 1.5.4.5 thorpej PTE_SYNC(pte); 168 1.5.4.5 thorpej } 169 1.5.4.2 nathanw } 170 1.5.4.2 nathanw pmap_update(pmap_kernel()); 171 1.5.4.2 nathanw 172 1.5.4.2 nathanw return(0); 173 1.5.4.2 nathanw } 174 1.5.4.2 nathanw 175 1.5.4.2 nathanw int 176 1.5.4.2 nathanw mainbus_bs_alloc(t, rstart, rend, size, alignment, boundary, cacheable, 177 1.5.4.2 nathanw bpap, bshp) 178 1.5.4.2 nathanw void *t; 179 1.5.4.2 nathanw bus_addr_t rstart, rend; 180 1.5.4.2 nathanw bus_size_t size, alignment, boundary; 181 1.5.4.2 nathanw int cacheable; 182 1.5.4.2 nathanw bus_addr_t *bpap; 183 1.5.4.2 nathanw bus_space_handle_t *bshp; 184 1.5.4.2 nathanw { 185 1.5.4.6 nathanw panic("mainbus_bs_alloc(): Help!"); 186 1.5.4.2 nathanw } 187 1.5.4.2 nathanw 188 1.5.4.2 nathanw 189 1.5.4.2 nathanw void 190 1.5.4.2 nathanw mainbus_bs_unmap(t, bsh, size) 191 1.5.4.2 nathanw void *t; 192 1.5.4.2 nathanw bus_space_handle_t bsh; 193 1.5.4.2 nathanw bus_size_t size; 194 1.5.4.2 nathanw { 195 1.5.4.2 nathanw /* 196 1.5.4.2 nathanw * Temporary implementation 197 1.5.4.2 nathanw */ 198 1.5.4.2 nathanw } 199 1.5.4.2 nathanw 200 1.5.4.2 nathanw void 201 1.5.4.2 nathanw mainbus_bs_free(t, bsh, size) 202 1.5.4.2 nathanw void *t; 203 1.5.4.2 nathanw bus_space_handle_t bsh; 204 1.5.4.2 nathanw bus_size_t size; 205 1.5.4.2 nathanw { 206 1.5.4.2 nathanw 207 1.5.4.6 nathanw panic("mainbus_bs_free(): Help!"); 208 1.5.4.2 nathanw /* mainbus_bs_unmap() does all that we need to do. */ 209 1.5.4.2 nathanw /* mainbus_bs_unmap(t, bsh, size);*/ 210 1.5.4.2 nathanw } 211 1.5.4.2 nathanw 212 1.5.4.2 nathanw int 213 1.5.4.2 nathanw mainbus_bs_subregion(t, bsh, offset, size, nbshp) 214 1.5.4.2 nathanw void *t; 215 1.5.4.2 nathanw bus_space_handle_t bsh; 216 1.5.4.2 nathanw bus_size_t offset, size; 217 1.5.4.2 nathanw bus_space_handle_t *nbshp; 218 1.5.4.2 nathanw { 219 1.5.4.2 nathanw 220 1.5.4.2 nathanw *nbshp = bsh + offset; 221 1.5.4.2 nathanw return (0); 222 1.5.4.2 nathanw } 223 1.5.4.2 nathanw 224 1.5.4.2 nathanw paddr_t 225 1.5.4.2 nathanw mainbus_bs_mmap(t, paddr, offset, prot, flags) 226 1.5.4.2 nathanw void *t; 227 1.5.4.2 nathanw bus_addr_t paddr; 228 1.5.4.2 nathanw off_t offset; 229 1.5.4.2 nathanw int prot; 230 1.5.4.2 nathanw int flags; 231 1.5.4.2 nathanw { 232 1.5.4.2 nathanw /* 233 1.5.4.2 nathanw * mmap from address `paddr+offset' for one page 234 1.5.4.2 nathanw */ 235 1.5.4.3 nathanw return (arm_btop((paddr + offset))); 236 1.5.4.2 nathanw } 237 1.5.4.2 nathanw 238 1.5.4.2 nathanw void 239 1.5.4.2 nathanw mainbus_bs_barrier(t, bsh, offset, len, flags) 240 1.5.4.2 nathanw void *t; 241 1.5.4.2 nathanw bus_space_handle_t bsh; 242 1.5.4.2 nathanw bus_size_t offset, len; 243 1.5.4.2 nathanw int flags; 244 1.5.4.2 nathanw { 245 1.5.4.2 nathanw } 246 1.5.4.2 nathanw 247 1.5.4.2 nathanw /* End of mainbus_io.c */ 248
Indexes created Wed Oct 22 06:10:02 GMT 2025