mv78xx0reg.h revision 1.1
1 /* $NetBSD: mv78xx0reg.h,v 1.1 2010/10/03 05:49:24 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2010 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef _MV78XX0REG_H_ 29 #define _MV78XX0REG_H_ 30 31 #include <arm/marvell/mvsocreg.h> 32 33 /* 34 * MHz PCIe GbE SATA TDMI COM 35 * MV76100: 800, 2 x2, x1, -, x3 36 * MV78100: 1.2, 2 x4, x2, x2, x2, x4 37 * MV78200: 1.0 x2, 2 x4, x4, x2, x2, x4 38 */ 39 40 #define MV78XX0_UNITID_DDR MVSOC_UNITID_DDR 41 #define MV78XX0_UNITID_DEVBUS MVSOC_UNITID_DEVBUS 42 #define MV78XX0_UNITID_LMB MVSOC_UNITID_LMB 43 #define MV78XX0_UNITID_GBE23 0x3 /* Gigabit Ethernet registers */ 44 #define MV78XX0_UNITID_PEX MVSOC_UNITID_PEX 45 #define MV78XX0_UNITID_USB 0x5 /* USB registers */ 46 #define MV78XX0_UNITID_IDMA 0x6 /* IDMA registers */ 47 #define MV78XX0_UNITID_XOR 0x6 /* XOR registers */ 48 #define MV78XX0_UNITID_GBE01 0x7 /* Gigabit Ethernet registers */ 49 #define MV78XX0_UNITID_CRYPT 0x9 /* Cryptographic Engine reg */ 50 #define MV78XX0_UNITID_SA 0x9 /* Security Accelelerator reg */ 51 #define MV78XX0_UNITID_SATA 0xa /* SATA registers */ 52 #define MV78XX0_UNITID_TDM 0xb /* TDM registers */ 53 54 #define MV78XX0_ATTR_DEVICE_CS0 0x3e 55 #define MV78XX0_ATTR_DEVICE_CS1 0x3d 56 #define MV78XX0_ATTR_DEVICE_CS2 0x3b 57 #define MV78XX0_ATTR_DEVICE_CS2 0x37 58 #define MV78XX0_ATTR_BOOT_CS 0x2f 59 #define MV78XX0_ATTR_SPI 0x1f 60 #define MV78XX0_ATTR_PEX_IO 0xe0 /* PCIe x4 Port 0.0 */ 61 #define MV78XX0_ATTR_PEX_MEM 0xe8 62 #define MV78XX0_ATTR_PEX1_IO 0xe0 /* PCIe x1 Port 1 */ 63 #define MV78XX0_ATTR_PEX1_MEM 0xe8 64 #define MV78XX0_ATTR_PEX_0_IO 0xe0 /* PCIe x1 Port 0.0 */ 65 #define MV78XX0_ATTR_PEX_0_MEM 0xe8 66 #define MV78XX0_ATTR_PEX_1_IO 0xd0 /* PCIe x1 Port 0.1 */ 67 #define MV78XX0_ATTR_PEX_1_MEM 0xd8 68 #define MV78XX0_ATTR_PEX_2_IO 0xb0 /* PCIe x1 Port 0.2 */ 69 #define MV78XX0_ATTR_PEX_2_MEM 0xb8 70 #define MV78XX0_ATTR_PEX_3_IO 0x70 /* PCIe x1 Port 0.3 */ 71 #define MV78XX0_ATTR_PEX_3_MEM 0x78 72 73 #define MV78XX0_IRQ_ERRSUM 0 /* Sum of Main Intr Err Cause */ 74 #define MV78XX0_IRQ_SPI 1 /* SPI */ 75 #define MV78XX0_IRQ_TWSI0 2 /* TWSI0 */ 76 #define MV78XX0_IRQ_TWSI1 3 /* TWSI1 */ 77 #define MV78XX0_IRQ_IDMA0 4 /* IDMA Channel0 completion */ 78 #define MV78XX0_IRQ_IDMA1 5 /* IDMA Channel1 completion */ 79 #define MV78XX0_IRQ_IDMA2 6 /* IDMA Channel2 completion */ 80 #define MV78XX0_IRQ_IDMA3 7 /* IDMA Channel3 completion */ 81 #define MV78XX0_IRQ_TIMER0 8 /* Timer0 */ 82 #define MV78XX0_IRQ_TIMER1 9 /* Timer1 */ 83 #define MV78XX0_IRQ_TIMER2 10 /* Timer2 */ 84 #define MV78XX0_IRQ_TIMER3 11 /* Timer3 */ 85 #define MV78XX0_IRQ_UART0 12 /* UART0 */ 86 #define MV78XX0_IRQ_UART1 13 /* UART1 */ 87 #define MV78XX0_IRQ_UART2 14 /* UART2 */ 88 #define MV78XX0_IRQ_UART3 15 /* UART3 */ 89 #define MV78XX0_IRQ_USB0 16 /* USB0 */ 90 #define MV78XX0_IRQ_USB1 17 /* USB1 */ 91 #define MV78XX0_IRQ_USB2 18 /* USB2 */ 92 #define MV78XX0_IRQ_CRYPTO 19 /* Crypto engine completion */ 93 #define MV78XX0_IRQ_XOR0 22 /* XOR engine 0 completion */ 94 #define MV78XX0_IRQ_XOR1 23 /* XOR engine 1 completion */ 95 #define MV78XX0_IRQ_SATA 26 /* SATA ports */ 96 #define MV78XX0_IRQ_TDMI_INT 27 /* TDM */ 97 #define MV78XX0_IRQ_PEX00INTA 32 /* PCIe Port0.0 INTA/B/C/D */ 98 #define MV78XX0_IRQ_PEX01INTA 33 /* PCIe Port0.1 INTA/B/C/D */ 99 #define MV78XX0_IRQ_PEX02INTA 34 /* PCIe Port0.2 INTA/B/C/D */ 100 #define MV78XX0_IRQ_PEX03INTA 35 /* PCIe Port0.3 INTA/B/C/D */ 101 #define MV78XX0_IRQ_PEX10INTA 36 /* PCIe Port1.0 INTA/B/C/D */ 102 #define MV78XX0_IRQ_PEX11INTA 37 /* PCIe Port1.1 INTA/B/C/D */ 103 #define MV78XX0_IRQ_PEX12INTA 38 /* PCIe Port1.2 INTA/B/C/D */ 104 #define MV78XX0_IRQ_PEX13INTA 39 /* PCIe Port1.3 INTA/B/C/D */ 105 #define MV78XX0_IRQ_GE00SUM 40 /* Gigabit Ethernet Port0 sum */ 106 #define MV78XX0_IRQ_GE00RX 41 /* Gigabit Ethernet Port0 Rx */ 107 #define MV78XX0_IRQ_GE00TX 42 /* Gigabit Ethernet Port0 Tx */ 108 #define MV78XX0_IRQ_GE00MISC 43 /* Gigabit Ethernet Port0 misc*/ 109 #define MV78XX0_IRQ_GE01SUM 44 /* Gigabit Ethernet Port1 sum */ 110 #define MV78XX0_IRQ_GE01RX 45 /* Gigabit Ethernet Port1 Rx */ 111 #define MV78XX0_IRQ_GE01TX 46 /* Gigabit Ethernet Port1 Tx */ 112 #define MV78XX0_IRQ_GE01MISC 47 /* Gigabit Ethernet Port1 misc*/ 113 #define MV78XX0_IRQ_GE10SUM 48 /* Gigabit Ethernet Port2 sum */ 114 #define MV78XX0_IRQ_GE10RX 49 /* Gigabit Ethernet Port2 Rx */ 115 #define MV78XX0_IRQ_GE10TX 50 /* Gigabit Ethernet Port2 Tx */ 116 #define MV78XX0_IRQ_GE10MISC 51 /* Gigabit Ethernet Port2 misc*/ 117 #define MV78XX0_IRQ_GE11SUM 52 /* Gigabit Ethernet Port3 sum */ 118 #define MV78XX0_IRQ_GE11RX 53 /* Gigabit Ethernet Port3 Rx */ 119 #define MV78XX0_IRQ_GE11TX 54 /* Gigabit Ethernet Port3 Tx */ 120 #define MV78XX0_IRQ_GE11MISC 55 /* Gigabit Ethernet Port3 misc*/ 121 #define MV78XX0_IRQ_GPIO0_7 56 /* GPIO[7:0] */ 122 #define MV78XX0_IRQ_GPIO8_15 57 /* GPIO[15:8] */ 123 #define MV78XX0_IRQ_GPIO16_23 58 /* GPIO[23:16] */ 124 #define MV78XX0_IRQ_GPIO24_31 59 /* GPIO[31:24] */ 125 #define MV78XX0_IRQ_DB_IN 60 /*Summary of Inbound Doorbell Cause*/ 126 #define MV78XX0_IRQ_DB_OUT 61/*Summary of Outbound Doorbell Cause*/ 127 128 129 /* 130 * Physical address of integrated peripherals 131 */ 132 133 #undef UNITID2PHYS 134 #define UNITID2PHYS(uid) ((MV78XX0_UNITID_ ## uid) << 16) 135 136 /* 137 * General Purpose Port Registers 138 */ 139 #define MV78XX0_GPP_BASE (MVSOC_DEVBUS_BASE + 0x0100) 140 #define MV78XX0_GPP_SIZE 0x100 141 142 /* 143 * UART Interface Registers 144 */ 145 /* NS16550 compatible */ 146 #define MV78XX0_COM2_BASE (MVSOC_DEVBUS_BASE + 0x2200) 147 #define MV78XX0_COM3_BASE (MVSOC_DEVBUS_BASE + 0x2300) 148 149 /* 150 * Mbus-L to Mbus Bridge Registers 151 */ 152 /* CPU Address Map Registers */ 153 #define MV78XX0_MLMB_NWINDOW 14 154 #define MV78XX0_MLMB_NREMAP 8 155 156 /* Main Interrupt Controller Registers */ 157 #define MV78XX0_MLMB_MICLR 0x200 /*Main Interrupt Cause Low reg*/ 158 #define MV78XX0_MLMB_MIRQIMLR 0x204 /* Main IRQ Interrupt Mask */ 159 #define MV78XX0_MLMB_MFIQIMLR 0x208 /* Main FIQ Interrupt Mask */ 160 #define MV78XX0_MLMB_EIMLR 0x20c /* Endpoint Interrupt Mask */ 161 #define MV78XX0_MLMB_MICHR 0x210 /* Main Intr Cause High reg */ 162 #define MV78XX0_MLMB_MIRQIMHR 0x214 /*Main IRQ Interrupt High Mask*/ 163 #define MV78XX0_MLMB_MFIQIMHR 0x218 /*Main FIQ Interrupt High Mask*/ 164 #define MV78XX0_MLMB_EIMHR 0x21c /*Endpoint Interrupt High Mask*/ 165 166 /* CPU Timers Registers */ 167 /* see oriontmrreg.h */ 168 169 170 /* 171 * PCI Express Interface Registers 172 */ 173 #define MV78XX0_PEX_BASE (UNITID2PHYS(PEX)) /* 0x40000 */ 174 175 /* 176 * USB 2.0 Interface Registers 177 */ 178 #define MV78XX0_USB_BASE (UNITID2PHYS(USB)) /* 0x50000 */ 179 180 /* 181 * IDMA Controller and XOR Engine Registers 182 */ 183 #define MV78XX0_IDMAC_BASE (UNITID2PHYS(IDMA)) /* 0x60000 */ 184 185 /* 186 * Gigabit Ethernet Registers 187 */ 188 #define MV78XX0_GBE01_BASE (UNITID2PHYS(GBE01)) /* 0x70000 */ 189 #define MV78XX0_GBE23_BASE (UNITID2PHYS(GBE23)) /* 0x30000 */ 190 191 /* 192 * Cryptographic Engine and Security Accelerator Registers 193 */ 194 #define MV78XX0_CESA_BASE (UNITID2PHYS(CRYPT)) /* 0x90000 */ 195 196 /* 197 * Serial-ATA Host Controller (SATAHC) Registers 198 */ 199 #define MV78XX0_SATAHC_BASE (UNITID2PHYS(SATA)) /* 0xa0000 */ 200 201 /* 202 * Time Division Multiplexing (TDM) Unit Registers 203 */ 204 #define MV78XX0_TDM_BASE (UNITID2PHYS(TDM)) /* 0xb0000 */ 205 206 #endif /* _MV78XX0REG_H_ */ 207
Indexes created Fri Oct 03 02:09:57 GMT 2025