mvsoc.c revision 1.11
1 /* $NetBSD: mvsoc.c,v 1.11 2013/05/29 20:47:14 rkujawa Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.11 2013/05/29 20:47:14 rkujawa Exp $"); 30 31 #include "opt_cputypes.h" 32 #include "opt_mvsoc.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pcireg.h> 41 #include <dev/marvell/marvellreg.h> 42 #include <dev/marvell/marvellvar.h> 43 44 #include <arm/marvell/mvsocreg.h> 45 #include <arm/marvell/mvsocvar.h> 46 #include <arm/marvell/orionreg.h> 47 #include <arm/marvell/kirkwoodreg.h> 48 49 #if defined(ARMADAXP) 50 #include <evbarm/armadaxp/armadaxpreg.h> 51 #include <evbarm/marvell/marvellreg.h> 52 #endif 53 54 #include "locators.h" 55 56 #ifdef MVSOC_CONSOLE_EARLY 57 #include <dev/ic/ns16550reg.h> 58 #include <dev/ic/comreg.h> 59 #include <dev/cons.h> 60 #endif 61 62 static int mvsoc_match(device_t, struct cfdata *, void *); 63 static void mvsoc_attach(device_t, device_t, void *); 64 65 static int mvsoc_print(void *, const char *); 66 static int mvsoc_search(device_t, cfdata_t, const int *, void *); 67 68 uint32_t mvPclk, mvSysclk, mvTclk = 0; 69 int nwindow = 0, nremap = 0; 70 static vaddr_t regbase = 0xffffffff, dsc_base, pex_base; 71 vaddr_t mlmb_base; 72 #if defined(ARMADAXP) 73 vaddr_t misc_base; 74 #endif 75 76 void (*mvsoc_intr_init)(void); 77 78 79 #ifdef MVSOC_CONSOLE_EARLY 80 static vaddr_t com_base; 81 82 static inline uint32_t 83 uart_read(bus_size_t o) 84 { 85 return *(volatile uint32_t *)(com_base + (o << 2)); 86 } 87 88 static inline void 89 uart_write(bus_size_t o, uint32_t v) 90 { 91 *(volatile uint32_t *)(com_base + (o << 2)) = v; 92 } 93 94 static int 95 mvsoc_cngetc(dev_t dv) 96 { 97 if ((uart_read(com_lsr) & LSR_RXRDY) == 0) 98 return -1; 99 100 return uart_read(com_data) & 0xff; 101 } 102 103 static void 104 mvsoc_cnputc(dev_t dv, int c) 105 { 106 int timo = 150000; 107 108 while ((uart_read(com_lsr) & LSR_TXRDY) == 0 && --timo > 0) 109 ; 110 111 uart_write(com_data, c); 112 113 timo = 150000; 114 while ((uart_read(com_lsr) & LSR_TSRE) == 0 && --timo > 0) 115 ; 116 } 117 118 static struct consdev mvsoc_earlycons = { 119 .cn_putc = mvsoc_cnputc, 120 .cn_getc = mvsoc_cngetc, 121 .cn_pollc = nullcnpollc, 122 }; 123 #endif 124 125 126 /* attributes */ 127 static struct { 128 int tag; 129 uint32_t attr; 130 uint32_t target; 131 } mvsoc_tags[] = { 132 { MARVELL_TAG_SDRAM_CS0, 133 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 134 { MARVELL_TAG_SDRAM_CS1, 135 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 136 { MARVELL_TAG_SDRAM_CS2, 137 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 138 { MARVELL_TAG_SDRAM_CS3, 139 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 140 141 #if defined(ORION) 142 { ORION_TAG_DEVICE_CS0, 143 ORION_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 144 { ORION_TAG_DEVICE_CS1, 145 ORION_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 146 { ORION_TAG_DEVICE_CS2, 147 ORION_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 148 { ORION_TAG_DEVICE_BOOTCS, 149 ORION_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 150 { ORION_TAG_FLASH_CS, 151 ORION_ATTR_FLASH_CS, MVSOC_UNITID_DEVBUS }, 152 { ORION_TAG_PEX0_MEM, 153 ORION_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 154 { ORION_TAG_PEX0_IO, 155 ORION_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 156 { ORION_TAG_PEX1_MEM, 157 ORION_ATTR_PEX_MEM, ORION_UNITID_PEX1 }, 158 { ORION_TAG_PEX1_IO, 159 ORION_ATTR_PEX_IO, ORION_UNITID_PEX1 }, 160 { ORION_TAG_PCI_MEM, 161 ORION_ATTR_PCI_MEM, ORION_UNITID_PCI }, 162 { ORION_TAG_PCI_IO, 163 ORION_ATTR_PCI_IO, ORION_UNITID_PCI }, 164 { ORION_TAG_CRYPT, 165 ORION_ATTR_CRYPT, ORION_UNITID_CRYPT }, 166 #endif 167 168 #if defined(KIRKWOOD) 169 { KIRKWOOD_TAG_NAND, 170 KIRKWOOD_ATTR_NAND, MVSOC_UNITID_DEVBUS }, 171 { KIRKWOOD_TAG_SPI, 172 KIRKWOOD_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 173 { KIRKWOOD_TAG_BOOTROM, 174 KIRKWOOD_ATTR_BOOTROM, MVSOC_UNITID_DEVBUS }, 175 { KIRKWOOD_TAG_PEX_MEM, 176 KIRKWOOD_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 177 { KIRKWOOD_TAG_PEX_IO, 178 KIRKWOOD_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 179 { KIRKWOOD_TAG_PEX1_MEM, 180 KIRKWOOD_ATTR_PEX1_MEM, MVSOC_UNITID_PEX }, 181 { KIRKWOOD_TAG_PEX1_IO, 182 KIRKWOOD_ATTR_PEX1_IO, MVSOC_UNITID_PEX }, 183 { KIRKWOOD_TAG_CRYPT, 184 KIRKWOOD_ATTR_CRYPT, KIRKWOOD_UNITID_CRYPT }, 185 #endif 186 #if defined(ARMADAXP) 187 { ARMADAXP_TAG_PEX00_MEM, 188 ARMADAXP_ATTR_PEXx0_MEM, ARMADAXP_UNITID_PEX0 }, 189 { ARMADAXP_TAG_PEX00_IO, 190 ARMADAXP_ATTR_PEXx0_IO, ARMADAXP_UNITID_PEX0 }, 191 { ARMADAXP_TAG_PEX01_MEM, 192 ARMADAXP_ATTR_PEXx1_MEM, ARMADAXP_UNITID_PEX0 }, 193 { ARMADAXP_TAG_PEX01_IO, 194 ARMADAXP_ATTR_PEXx1_IO, ARMADAXP_UNITID_PEX0 }, 195 { ARMADAXP_TAG_PEX02_MEM, 196 ARMADAXP_ATTR_PEXx2_MEM, ARMADAXP_UNITID_PEX0 }, 197 { ARMADAXP_TAG_PEX02_IO, 198 ARMADAXP_ATTR_PEXx2_IO, ARMADAXP_UNITID_PEX0 }, 199 { ARMADAXP_TAG_PEX03_MEM, 200 ARMADAXP_ATTR_PEXx3_MEM, ARMADAXP_UNITID_PEX0 }, 201 { ARMADAXP_TAG_PEX03_IO, 202 ARMADAXP_ATTR_PEXx3_IO, ARMADAXP_UNITID_PEX0 }, 203 { ARMADAXP_TAG_PEX2_MEM, 204 ARMADAXP_ATTR_PEX2_MEM, ARMADAXP_UNITID_PEX2 }, 205 { ARMADAXP_TAG_PEX2_IO, 206 ARMADAXP_ATTR_PEX2_IO, ARMADAXP_UNITID_PEX2 }, 207 { ARMADAXP_TAG_PEX3_MEM, 208 ARMADAXP_ATTR_PEX3_MEM, ARMADAXP_UNITID_PEX3 }, 209 { ARMADAXP_TAG_PEX3_IO, 210 ARMADAXP_ATTR_PEX3_IO, ARMADAXP_UNITID_PEX3 }, 211 #endif 212 }; 213 214 #if defined(ARMADAXP) 215 #undef ARMADAXP 216 #define ARMADAXP(m) MARVELL_ARMADAXP_ ## m 217 #endif 218 #if defined(ORION) 219 #define ORION_1(m) MARVELL_ORION_1_ ## m 220 #define ORION_2(m) MARVELL_ORION_2_ ## m 221 #endif 222 #if defined(KIRKWOOD) 223 #undef KIRKWOOD 224 #define KIRKWOOD(m) MARVELL_KIRKWOOD_ ## m 225 #endif 226 #if defined(MV78XX0) 227 #undef MV78XX0 228 #define MV78XX0(m) MARVELL_MV78XX0_ ## m 229 #endif 230 static struct { 231 uint16_t model; 232 uint8_t rev; 233 const char *modelstr; 234 const char *revstr; 235 const char *typestr; 236 } nametbl[] = { 237 #if defined(ORION) 238 { ORION_1(88F1181), 0, "MV88F1181", NULL, "Orion1" }, 239 { ORION_1(88F5082), 2, "MV88F5082", "A2", "Orion1" }, 240 { ORION_1(88F5180N), 3, "MV88F5180N","B1", "Orion1" }, 241 { ORION_1(88F5181), 0, "MV88F5181", "A0", "Orion1" }, 242 { ORION_1(88F5181), 1, "MV88F5181", "A1", "Orion1" }, 243 { ORION_1(88F5181), 2, "MV88F5181", "B0", "Orion1" }, 244 { ORION_1(88F5181), 3, "MV88F5181", "B1", "Orion1" }, 245 { ORION_1(88F5181), 8, "MV88F5181L","A0", "Orion1" }, 246 { ORION_1(88F5181), 9, "MV88F5181L","A1", "Orion1" }, 247 { ORION_1(88F5182), 0, "MV88F5182", "A0", "Orion1" }, 248 { ORION_1(88F5182), 1, "MV88F5182", "A1", "Orion1" }, 249 { ORION_1(88F5182), 2, "MV88F5182", "A2", "Orion1" }, 250 { ORION_1(88F6082), 0, "MV88F6082", "A0", "Orion1" }, 251 { ORION_1(88F6082), 1, "MV88F6082", "A1", "Orion1" }, 252 { ORION_1(88F6183), 0, "MV88F6183", "A0", "Orion1" }, 253 { ORION_1(88F6183), 1, "MV88F6183", "Z0", "Orion1" }, 254 { ORION_1(88W8660), 0, "MV88W8660", "A0", "Orion1" }, 255 { ORION_1(88W8660), 1, "MV88W8660", "A1", "Orion1" }, 256 257 { ORION_2(88F1281), 0, "MV88F1281", "A0", "Orion2" }, 258 { ORION_2(88F5281), 0, "MV88F5281", "A0", "Orion2" }, 259 { ORION_2(88F5281), 1, "MV88F5281", "B0", "Orion2" }, 260 { ORION_2(88F5281), 2, "MV88F5281", "C0", "Orion2" }, 261 { ORION_2(88F5281), 3, "MV88F5281", "C1", "Orion2" }, 262 { ORION_2(88F5281), 4, "MV88F5281", "D0", "Orion2" }, 263 #endif 264 265 #if defined(KIRKWOOD) 266 { KIRKWOOD(88F6180), 2, "88F6180", "A0", "Kirkwood" }, 267 { KIRKWOOD(88F6180), 3, "88F6180", "A1", "Kirkwood" }, 268 { KIRKWOOD(88F6192), 0, "88F619x", "Z0", "Kirkwood" }, 269 { KIRKWOOD(88F6192), 2, "88F619x", "A0", "Kirkwood" }, 270 { KIRKWOOD(88F6192), 3, "88F619x", "A1", "Kirkwood" }, 271 { KIRKWOOD(88F6281), 0, "88F6281", "Z0", "Kirkwood" }, 272 { KIRKWOOD(88F6281), 2, "88F6281", "A0", "Kirkwood" }, 273 { KIRKWOOD(88F6281), 3, "88F6281", "A1", "Kirkwood" }, 274 { KIRKWOOD(88F6282), 0, "88F6282", "A0", "Kirkwood" }, 275 { KIRKWOOD(88F6282), 1, "88F6282", "A1", "Kirkwood" }, 276 #endif 277 278 #if defined(MV78XX0) 279 { MV78XX0(MV78100), 1, "MV78100", "A0", "Discovery Innovation" }, 280 { MV78XX0(MV78100), 2, "MV78100", "A1", "Discovery Innovation" }, 281 { MV78XX0(MV78200), 1, "MV78200", "A0", "Discovery Innovation" }, 282 #endif 283 284 #if defined(ARMADAXP) 285 { ARMADAXP(MV78130), 1, "MV78130", "A0", "Armada XP" }, 286 { ARMADAXP(MV78160), 1, "MV78160", "A0", "Armada XP" }, 287 { ARMADAXP(MV78230), 1, "MV78260", "A0", "Armada XP" }, 288 { ARMADAXP(MV78260), 1, "MV78260", "A0", "Armada XP" }, 289 { ARMADAXP(MV78460), 1, "MV78460", "A0", "Armada XP" }, 290 { ARMADAXP(MV78460), 2, "MV78460", "B0", "Armada XP" }, 291 #endif 292 }; 293 294 #define OFFSET_DEFAULT MVA_OFFSET_DEFAULT 295 #define IRQ_DEFAULT MVA_IRQ_DEFAULT 296 static const struct mvsoc_periph { 297 int model; 298 const char *name; 299 int unit; 300 bus_size_t offset; 301 int irq; 302 uint32_t clkpwr_bit; 303 } mvsoc_periphs[] = { 304 #if defined(ORION) 305 { ORION_1(88F1181), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 306 { ORION_1(88F1181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 307 { ORION_1(88F1181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 308 { ORION_1(88F1181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 309 { ORION_1(88F1181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 310 { ORION_1(88F1181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 311 { ORION_1(88F1181), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 312 313 { ORION_1(88F5082), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 314 { ORION_1(88F5082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 315 { ORION_1(88F5082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 316 { ORION_1(88F5082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 317 { ORION_1(88F5082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 318 { ORION_1(88F5082), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 319 { ORION_1(88F5082), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 320 { ORION_1(88F5082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 321 { ORION_1(88F5082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 322 { ORION_1(88F5082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 323 { ORION_1(88F5082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 324 { ORION_1(88F5082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 325 326 { ORION_1(88F5180N),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 327 { ORION_1(88F5180N),"mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 328 { ORION_1(88F5180N),"com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 329 { ORION_1(88F5180N),"com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 330 { ORION_1(88F5180N),"ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 331 { ORION_1(88F5180N),"gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 332 { ORION_1(88F5180N),"gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 333 { ORION_1(88F5180N),"gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 334 { ORION_1(88F5180N),"mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 335 { ORION_1(88F5180N),"mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 336 337 { ORION_1(88F5181), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 338 { ORION_1(88F5181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 339 { ORION_1(88F5181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 340 { ORION_1(88F5181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 341 { ORION_1(88F5181), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 342 { ORION_1(88F5181), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 343 { ORION_1(88F5181), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 344 { ORION_1(88F5181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 345 { ORION_1(88F5181), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 346 { ORION_1(88F5181), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 347 { ORION_1(88F5181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 348 349 { ORION_1(88F5182), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 350 { ORION_1(88F5182), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 351 { ORION_1(88F5182), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 352 { ORION_1(88F5182), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 353 { ORION_1(88F5182), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 354 { ORION_1(88F5182), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 355 { ORION_1(88F5182), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 356 { ORION_1(88F5182), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 357 { ORION_1(88F5182), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 358 { ORION_1(88F5182), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 359 { ORION_1(88F5182), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 360 { ORION_1(88F5182), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 361 362 { ORION_1(88F6082), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 363 { ORION_1(88F6082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 364 { ORION_1(88F6082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 365 { ORION_1(88F6082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 366 { ORION_1(88F6082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 367 { ORION_1(88F6082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 368 { ORION_1(88F6082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 369 { ORION_1(88F6082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 370 { ORION_1(88F6082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 371 { ORION_1(88F6082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 372 373 { ORION_1(88F6183), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 374 { ORION_1(88F6183), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 375 { ORION_1(88F6183), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 376 { ORION_1(88F6183), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 377 378 { ORION_1(88W8660), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 379 { ORION_1(88W8660), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 380 { ORION_1(88W8660), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 381 { ORION_1(88W8660), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 382 { ORION_1(88W8660), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 383 { ORION_1(88W8660), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 384 { ORION_1(88W8660), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 385 { ORION_1(88W8660), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 386 { ORION_1(88W8660), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 387 { ORION_1(88W8660), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 388 389 { ORION_2(88F1281), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 390 { ORION_2(88F1281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 391 { ORION_2(88F1281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 392 { ORION_2(88F1281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 393 { ORION_2(88F1281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 394 { ORION_2(88F1281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 395 { ORION_2(88F1281), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 396 397 { ORION_2(88F5281), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 398 { ORION_2(88F5281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 399 { ORION_2(88F5281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 400 { ORION_2(88F5281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 401 { ORION_2(88F5281), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 402 { ORION_2(88F5281), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 403 { ORION_2(88F5281), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 404 { ORION_2(88F5281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 405 { ORION_2(88F5281), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 406 { ORION_2(88F5281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 407 #endif 408 409 #if defined(KIRKWOOD) 410 { KIRKWOOD(88F6180),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 411 { KIRKWOOD(88F6180),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 412 { KIRKWOOD(88F6180),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 413 { KIRKWOOD(88F6180),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 414 { KIRKWOOD(88F6180),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 415 { KIRKWOOD(88F6180),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 416 { KIRKWOOD(88F6180),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 417 { KIRKWOOD(88F6180),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 418 { KIRKWOOD(88F6180),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 419 { KIRKWOOD(88F6180),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 420 { KIRKWOOD(88F6180),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 421 { KIRKWOOD(88F6180),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 422 423 { KIRKWOOD(88F6192),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 424 { KIRKWOOD(88F6192),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 425 { KIRKWOOD(88F6192),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 426 { KIRKWOOD(88F6192),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 427 { KIRKWOOD(88F6192),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 428 { KIRKWOOD(88F6192),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 429 { KIRKWOOD(88F6192),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 430 { KIRKWOOD(88F6192),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 431 { KIRKWOOD(88F6192),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 432 { KIRKWOOD(88F6192),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 433 { KIRKWOOD(88F6192),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 434 { KIRKWOOD(88F6192),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 435 { KIRKWOOD(88F6192),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 436 { KIRKWOOD(88F6192),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 437 438 { KIRKWOOD(88F6281),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 439 { KIRKWOOD(88F6281),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 440 { KIRKWOOD(88F6281),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 441 { KIRKWOOD(88F6281),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 442 { KIRKWOOD(88F6281),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 443 { KIRKWOOD(88F6281),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT, 444 MVSOC_MLMB_CLKGATING_BIT(3) }, 445 { KIRKWOOD(88F6281),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 446 { KIRKWOOD(88F6281),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 447 { KIRKWOOD(88F6281),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT, 448 MVSOC_MLMB_CLKGATING_BIT(17) }, 449 { KIRKWOOD(88F6281),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT, 450 MVSOC_MLMB_CLKGATING_BIT(0) }, 451 { KIRKWOOD(88F6281),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT, 452 MVSOC_MLMB_CLKGATING_BIT(19) }, 453 { KIRKWOOD(88F6281),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT, 454 MVSOC_MLMB_CLKGATING_BIT(2) }, 455 { KIRKWOOD(88F6281),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA, 456 MVSOC_MLMB_CLKGATING_BIT(14) | 457 MVSOC_MLMB_CLKGATING_BIT(15) }, 458 { KIRKWOOD(88F6281),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT, 459 MVSOC_MLMB_CLKGATING_BIT(4) }, 460 461 { KIRKWOOD(88F6282),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 462 { KIRKWOOD(88F6282),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 463 { KIRKWOOD(88F6282),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 464 { KIRKWOOD(88F6282),"mvsocts", 0, KIRKWOOD_TS_BASE, IRQ_DEFAULT }, 465 { KIRKWOOD(88F6282),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 466 { KIRKWOOD(88F6282),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 467 { KIRKWOOD(88F6282),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 468 { KIRKWOOD(88F6282),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 469 { KIRKWOOD(88F6282),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 470 { KIRKWOOD(88F6282),"gttwsi", 1, KIRKWOOD_TWSI1_BASE,KIRKWOOD_IRQ_TWSI1 }, 471 { KIRKWOOD(88F6282),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 472 { KIRKWOOD(88F6282),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 473 { KIRKWOOD(88F6282),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 474 { KIRKWOOD(88F6282),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 475 { KIRKWOOD(88F6282),"mvpex", 1, KIRKWOOD_PEX1_BASE,KIRKWOOD_IRQ_PEX1INT }, 476 { KIRKWOOD(88F6282),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 477 { KIRKWOOD(88F6282),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 478 #endif 479 480 #if defined(MV78XX0) 481 { MV78XX0(MV78100), "mvsoctmr",0,MVSOC_TMR_BASE, IRQ_DEFAULT }, 482 { MV78XX0(MV78100), "mvsocgpp",0,MVSOC_GPP_BASE, MV78XX0_IRQ_GPIOLO7_0 }, 483 { MV78XX0(MV78100), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0INT }, 484 { MV78XX0(MV78100), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1INT }, 485 { MV78XX0(MV78100), "gttwsi",0,MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI }, 486 : 487 488 { MV78XX0(MV78200), "mvsoctmr",0,MVSOC_TMR_BASE, IRQ_DEFAULT }, 489 { MV78XX0(MV78200), "mvsocgpp",0,MVSOC_GPP_BASE, MV78XX0_IRQ_GPIOLO7_0 }, 490 { MV78XX0(MV78200), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0INT }, 491 { MV78XX0(MV78200), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1INT }, 492 { MV78XX0(MV78200), "gttwsi",0,MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI }, 493 : 494 #endif 495 496 #if defined(ARMADAXP) 497 { ARMADAXP(MV78130), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 498 { ARMADAXP(MV78130), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0INT }, 499 { ARMADAXP(MV78130), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1INT }, 500 { ARMADAXP(MV78130), "com", 2, ARMADAXP_COM2_BASE, ARMADAXP_IRQ_UART2INT }, 501 { ARMADAXP(MV78130), "com", 3, ARMADAXP_COM3_BASE, ARMADAXP_IRQ_UART3INT }, 502 { ARMADAXP(MV78130), "mvsocrtc",0, ARMADAXP_RTC_BASE, ARMADAXP_IRQ_RTCINT }, 503 { ARMADAXP(MV78130), "ehci", 0, ARMADAXP_USB0_BASE, ARMADAXP_IRQ_USB0INT }, 504 { ARMADAXP(MV78130), "ehci", 1, ARMADAXP_USB1_BASE, ARMADAXP_IRQ_USB1INT }, 505 { ARMADAXP(MV78130), "mvpex", 0, ARMADAXP_PEX00_BASE, ARMADAXP_IRQ_PEX00}, 506 { ARMADAXP(MV78130), "mvpex", 1, ARMADAXP_PEX01_BASE, ARMADAXP_IRQ_PEX01}, 507 { ARMADAXP(MV78130), "mvpex", 2, ARMADAXP_PEX02_BASE, ARMADAXP_IRQ_PEX02}, 508 { ARMADAXP(MV78130), "mvpex", 3, ARMADAXP_PEX03_BASE, ARMADAXP_IRQ_PEX03}, 509 510 { ARMADAXP(MV78160), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 511 { ARMADAXP(MV78160), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0INT }, 512 { ARMADAXP(MV78160), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1INT }, 513 { ARMADAXP(MV78160), "com", 2, ARMADAXP_COM2_BASE, ARMADAXP_IRQ_UART2INT }, 514 { ARMADAXP(MV78160), "com", 3, ARMADAXP_COM3_BASE, ARMADAXP_IRQ_UART3INT }, 515 { ARMADAXP(MV78160), "mvsocrtc",0, ARMADAXP_RTC_BASE, ARMADAXP_IRQ_RTCINT }, 516 { ARMADAXP(MV78160), "ehci", 0, ARMADAXP_USB0_BASE, ARMADAXP_IRQ_USB0INT }, 517 { ARMADAXP(MV78160), "ehci", 1, ARMADAXP_USB1_BASE, ARMADAXP_IRQ_USB1INT }, 518 { ARMADAXP(MV78160), "mvpex", 0, ARMADAXP_PEX00_BASE, ARMADAXP_IRQ_PEX00}, 519 { ARMADAXP(MV78160), "mvpex", 1, ARMADAXP_PEX01_BASE, ARMADAXP_IRQ_PEX01}, 520 { ARMADAXP(MV78160), "mvpex", 2, ARMADAXP_PEX02_BASE, ARMADAXP_IRQ_PEX02}, 521 { ARMADAXP(MV78160), "mvpex", 3, ARMADAXP_PEX03_BASE, ARMADAXP_IRQ_PEX03}, 522 { ARMADAXP(MV78160), "mvpex", 4, ARMADAXP_PEX2_BASE, ARMADAXP_IRQ_PEX2}, 523 524 { ARMADAXP(MV78230), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 525 { ARMADAXP(MV78230), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0INT }, 526 { ARMADAXP(MV78230), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1INT }, 527 { ARMADAXP(MV78230), "com", 2, ARMADAXP_COM2_BASE, ARMADAXP_IRQ_UART2INT }, 528 { ARMADAXP(MV78230), "com", 3, ARMADAXP_COM3_BASE, ARMADAXP_IRQ_UART3INT }, 529 { ARMADAXP(MV78230), "mvsocrtc",0, ARMADAXP_RTC_BASE, ARMADAXP_IRQ_RTCINT }, 530 { ARMADAXP(MV78230), "ehci", 0, ARMADAXP_USB0_BASE, ARMADAXP_IRQ_USB0INT }, 531 { ARMADAXP(MV78230), "ehci", 1, ARMADAXP_USB1_BASE, ARMADAXP_IRQ_USB1INT }, 532 { ARMADAXP(MV78230), "mvpex", 0, ARMADAXP_PEX00_BASE, ARMADAXP_IRQ_PEX00}, 533 { ARMADAXP(MV78230), "mvpex", 1, ARMADAXP_PEX01_BASE, ARMADAXP_IRQ_PEX01}, 534 { ARMADAXP(MV78230), "mvpex", 2, ARMADAXP_PEX02_BASE, ARMADAXP_IRQ_PEX02}, 535 { ARMADAXP(MV78230), "mvpex", 3, ARMADAXP_PEX03_BASE, ARMADAXP_IRQ_PEX03}, 536 { ARMADAXP(MV78230), "mvpex", 4, ARMADAXP_PEX2_BASE, ARMADAXP_IRQ_PEX2}, 537 538 { ARMADAXP(MV78260), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 539 { ARMADAXP(MV78260), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0INT }, 540 { ARMADAXP(MV78260), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1INT }, 541 { ARMADAXP(MV78260), "com", 2, ARMADAXP_COM2_BASE, ARMADAXP_IRQ_UART2INT }, 542 { ARMADAXP(MV78260), "com", 3, ARMADAXP_COM3_BASE, ARMADAXP_IRQ_UART3INT }, 543 { ARMADAXP(MV78260), "mvsocrtc",0, ARMADAXP_RTC_BASE, ARMADAXP_IRQ_RTCINT }, 544 { ARMADAXP(MV78260), "ehci", 0, ARMADAXP_USB0_BASE, ARMADAXP_IRQ_USB0INT }, 545 { ARMADAXP(MV78260), "ehci", 1, ARMADAXP_USB1_BASE, ARMADAXP_IRQ_USB1INT }, 546 { ARMADAXP(MV78260), "mvpex", 0, ARMADAXP_PEX00_BASE, ARMADAXP_IRQ_PEX00}, 547 { ARMADAXP(MV78260), "mvpex", 1, ARMADAXP_PEX01_BASE, ARMADAXP_IRQ_PEX01}, 548 { ARMADAXP(MV78260), "mvpex", 2, ARMADAXP_PEX02_BASE, ARMADAXP_IRQ_PEX02}, 549 { ARMADAXP(MV78260), "mvpex", 3, ARMADAXP_PEX03_BASE, ARMADAXP_IRQ_PEX03}, 550 { ARMADAXP(MV78260), "mvpex", 4, ARMADAXP_PEX2_BASE, ARMADAXP_IRQ_PEX2}, 551 552 { ARMADAXP(MV78460), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 553 { ARMADAXP(MV78460), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0INT }, 554 { ARMADAXP(MV78460), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1INT }, 555 { ARMADAXP(MV78460), "com", 2, ARMADAXP_COM2_BASE, ARMADAXP_IRQ_UART2INT }, 556 { ARMADAXP(MV78460), "com", 3, ARMADAXP_COM3_BASE, ARMADAXP_IRQ_UART3INT }, 557 { ARMADAXP(MV78460), "mvsocrtc",0, ARMADAXP_RTC_BASE, ARMADAXP_IRQ_RTCINT }, 558 { ARMADAXP(MV78460), "ehci", 0, ARMADAXP_USB0_BASE, ARMADAXP_IRQ_USB0INT }, 559 { ARMADAXP(MV78460), "ehci", 1, ARMADAXP_USB1_BASE, ARMADAXP_IRQ_USB1INT }, 560 { ARMADAXP(MV78460), "mvpex", 0, ARMADAXP_PEX00_BASE, ARMADAXP_IRQ_PEX00}, 561 { ARMADAXP(MV78460), "mvpex", 1, ARMADAXP_PEX01_BASE, ARMADAXP_IRQ_PEX01}, 562 { ARMADAXP(MV78460), "mvpex", 2, ARMADAXP_PEX02_BASE, ARMADAXP_IRQ_PEX02}, 563 { ARMADAXP(MV78460), "mvpex", 3, ARMADAXP_PEX03_BASE, ARMADAXP_IRQ_PEX03}, 564 { ARMADAXP(MV78460), "mvpex", 4, ARMADAXP_PEX2_BASE, ARMADAXP_IRQ_PEX2}, 565 { ARMADAXP(MV78460), "mvpex", 5, ARMADAXP_PEX3_BASE, ARMADAXP_IRQ_PEX3}, 566 { ARMADAXP(MV78460), "mvsata", 0, ARMADAXP_SATAHC_BASE, ARMADAXP_IRQ_SATA0 }, 567 { ARMADAXP(MV78460), "gttwsi", 0, ARMADAXP_TWSI0_BASE, ARMADAXP_IRQ_TWSI0}, 568 { ARMADAXP(MV78460), "gttwsi", 1, ARMADAXP_TWSI1_BASE, ARMADAXP_IRQ_TWSI1}, 569 { ARMADAXP(MV78460), "mvspi", 0, ARMADAXP_SPI0_BASE, ARMADAXP_IRQ_SPI0}, 570 { ARMADAXP(MV78460), "mvspi", 1, ARMADAXP_SPI1_BASE, ARMADAXP_IRQ_SPI0}, 571 #endif 572 }; 573 574 575 CFATTACH_DECL_NEW(mvsoc, sizeof(struct mvsoc_softc), 576 mvsoc_match, mvsoc_attach, NULL, NULL); 577 578 /* ARGSUSED */ 579 static int 580 mvsoc_match(device_t parent, struct cfdata *match, void *aux) 581 { 582 583 return 1; 584 } 585 586 /* ARGSUSED */ 587 static void 588 mvsoc_attach(device_t parent, device_t self, void *aux) 589 { 590 struct mvsoc_softc *sc = device_private(self); 591 struct marvell_attach_args mva; 592 uint16_t model; 593 uint8_t rev; 594 uint32_t clkpwr, clkpwrbit; 595 int i; 596 597 sc->sc_dev = self; 598 sc->sc_iot = &mvsoc_bs_tag; 599 sc->sc_addr = regbase; 600 sc->sc_dmat = &mvsoc_bus_dma_tag; 601 if (bus_space_map(sc->sc_iot, sc->sc_addr, 0x100000, 0, &sc->sc_ioh) != 602 0) { 603 aprint_error_dev(self, "can't map registers\n"); 604 return; 605 } 606 607 model = mvsoc_model(); 608 rev = mvsoc_rev(); 609 for (i = 0; i < __arraycount(nametbl); i++) 610 if (nametbl[i].model == model && nametbl[i].rev == rev) 611 break; 612 if (i >= __arraycount(nametbl)) 613 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 614 615 aprint_normal(": Marvell %s %s%s %s\n", 616 nametbl[i].modelstr, 617 nametbl[i].revstr != NULL ? "Rev. " : "", 618 nametbl[i].revstr != NULL ? nametbl[i].revstr : "", 619 nametbl[i].typestr); 620 aprint_normal("%s: CPU Clock %d.%03d MHz" 621 " SysClock %d.%03d MHz TClock %d.%03d MHz\n", 622 device_xname(self), 623 mvPclk / 1000000, (mvPclk / 1000) % 1000, 624 mvSysclk / 1000000, (mvSysclk / 1000) % 1000, 625 mvTclk / 1000000, (mvTclk / 1000) % 1000); 626 aprint_naive("\n"); 627 628 mvsoc_intr_init(); 629 630 for (i = 0; i < __arraycount(mvsoc_periphs); i++) { 631 if (mvsoc_periphs[i].model != model) 632 continue; 633 634 /* Skip clock disabled devices */ 635 clkpwrbit = mvsoc_periphs[i].clkpwr_bit; 636 if (clkpwrbit != 0) { 637 clkpwr = read_mlmbreg(MVSOC_MLMB_CLKGATING); 638 639 if ((clkpwr & clkpwrbit) == 0) { 640 aprint_normal("%s: %s%d clock disabled\n", 641 device_xname(self), 642 mvsoc_periphs[i].name, 643 mvsoc_periphs[i].unit); 644 continue; 645 } 646 } 647 648 mva.mva_name = mvsoc_periphs[i].name; 649 mva.mva_model = model; 650 mva.mva_revision = rev; 651 mva.mva_iot = sc->sc_iot; 652 mva.mva_ioh = sc->sc_ioh; 653 mva.mva_unit = mvsoc_periphs[i].unit; 654 mva.mva_addr = sc->sc_addr; 655 mva.mva_offset = mvsoc_periphs[i].offset; 656 mva.mva_size = 0; 657 mva.mva_dmat = sc->sc_dmat; 658 mva.mva_irq = mvsoc_periphs[i].irq; 659 660 config_found_sm_loc(sc->sc_dev, "mvsoc", NULL, &mva, 661 mvsoc_print, mvsoc_search); 662 } 663 } 664 665 static int 666 mvsoc_print(void *aux, const char *pnp) 667 { 668 struct marvell_attach_args *mva = aux; 669 670 if (pnp) 671 aprint_normal("%s at %s unit %d", 672 mva->mva_name, pnp, mva->mva_unit); 673 else { 674 if (mva->mva_unit != MVA_UNIT_DEFAULT) 675 aprint_normal(" unit %d", mva->mva_unit); 676 if (mva->mva_offset != MVA_OFFSET_DEFAULT) { 677 aprint_normal(" offset 0x%04lx", mva->mva_offset); 678 if (mva->mva_size > 0) 679 aprint_normal("-0x%04lx", 680 mva->mva_offset + mva->mva_size - 1); 681 } 682 if (mva->mva_irq != MVA_IRQ_DEFAULT) 683 aprint_normal(" irq %d", mva->mva_irq); 684 } 685 686 return UNCONF; 687 } 688 689 /* ARGSUSED */ 690 static int 691 mvsoc_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 692 { 693 694 return config_match(parent, cf, aux); 695 } 696 697 /* ARGSUSED */ 698 int 699 marvell_winparams_by_tag(device_t dev, int tag, int *target, int *attribute, 700 uint64_t *base, uint32_t *size) 701 { 702 uint32_t base32; 703 int rv; 704 705 rv = mvsoc_target(tag, target, attribute, &base32, size); 706 *base = base32; 707 if (rv == -1) 708 return -1; 709 return 0; 710 } 711 712 713 /* 714 * These functions is called before bus_space is initialized. 715 */ 716 717 void 718 mvsoc_bootstrap(bus_addr_t iobase) 719 { 720 721 #if defined(ARMADAXP) 722 regbase = MARVELL_INTERREGS_PBASE; 723 misc_base = iobase + MVSOC_MISC_BASE; 724 #else 725 regbase = iobase; 726 #endif 727 dsc_base = iobase + MVSOC_DSC_BASE; 728 mlmb_base = iobase + MVSOC_MLMB_BASE; 729 pex_base = iobase + MVSOC_PEX_BASE; 730 #ifdef MVSOC_CONSOLE_EARLY 731 com_base = iobase + MVSOC_COM0_BASE; 732 cn_tab = &mvsoc_earlycons; 733 printf("Hello\n"); 734 #endif 735 } 736 737 /* 738 * We can read register of PCI configurations from (MVSOC_PEX_BASE + 0). 739 */ 740 uint16_t 741 mvsoc_model(void) 742 { 743 /* 744 * We read product-id from vendor/device register of PCI-Express. 745 */ 746 uint32_t reg; 747 uint16_t model; 748 749 KASSERT(regbase != 0xffffffff); 750 751 reg = *(volatile uint32_t *)(pex_base + PCI_ID_REG); 752 model = PCI_PRODUCT(reg); 753 754 #if defined(ORION) 755 if (model == PCI_PRODUCT_MARVELL_88F5182) { 756 reg = *(volatile uint32_t *)(regbase + ORION_PMI_BASE + 757 ORION_PMI_SAMPLE_AT_RESET); 758 if ((reg & ORION_PMISMPL_TCLK_MASK) == 0) 759 model = PCI_PRODUCT_MARVELL_88F5082; 760 } 761 #endif 762 763 return model; 764 } 765 766 uint8_t 767 mvsoc_rev(void) 768 { 769 uint32_t reg; 770 uint8_t rev; 771 772 KASSERT(regbase != 0xffffffff); 773 774 reg = *(volatile uint32_t *)(pex_base + PCI_CLASS_REG); 775 rev = PCI_REVISION(reg); 776 777 return rev; 778 } 779 780 781 int 782 mvsoc_target(int tag, uint32_t *target, uint32_t *attr, uint32_t *base, 783 uint32_t *size) 784 { 785 int i; 786 787 KASSERT(regbase != 0xffffffff); 788 789 if (tag == MVSOC_TAG_INTERNALREG) { 790 if (target != NULL) 791 *target = 0; 792 if (attr != NULL) 793 *attr = 0; 794 if (base != NULL) 795 *base = read_mlmbreg(MVSOC_MLMB_IRBAR) & 796 MVSOC_MLMB_IRBAR_BASE_MASK; 797 if (size != NULL) 798 *size = 0; 799 800 return 0; 801 } 802 803 /* sanity check */ 804 for (i = 0; i < __arraycount(mvsoc_tags); i++) 805 if (mvsoc_tags[i].tag == tag) 806 break; 807 if (i >= __arraycount(mvsoc_tags)) 808 return -1; 809 810 if (target != NULL) 811 *target = mvsoc_tags[i].target; 812 if (attr != NULL) 813 *attr = mvsoc_tags[i].attr; 814 815 if (mvsoc_tags[i].target == MVSOC_UNITID_DDR) { 816 /* 817 * Read DDR SDRAM Controller Address Decode Registers 818 */ 819 uint32_t baseaddrreg, sizereg; 820 int cs = 0; 821 822 switch (mvsoc_tags[i].attr) { 823 case MARVELL_ATTR_SDRAM_CS0: 824 cs = 0; 825 break; 826 case MARVELL_ATTR_SDRAM_CS1: 827 cs = 1; 828 break; 829 case MARVELL_ATTR_SDRAM_CS2: 830 cs = 2; 831 break; 832 case MARVELL_ATTR_SDRAM_CS3: 833 cs = 3; 834 break; 835 } 836 sizereg = *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSSR(cs)); 837 if (sizereg & MVSOC_DSC_CSSR_WINEN) { 838 baseaddrreg = *(volatile uint32_t *)(dsc_base + 839 MVSOC_DSC_CSBAR(cs)); 840 841 if (base != NULL) 842 *base = baseaddrreg & MVSOC_DSC_CSBAR_BASE_MASK; 843 if (size != NULL) 844 *size = (sizereg & MVSOC_DSC_CSSR_SIZE_MASK) + 845 (~MVSOC_DSC_CSSR_SIZE_MASK + 1); 846 } else { 847 if (base != NULL) 848 *base = 0; 849 if (size != NULL) 850 *size = 0; 851 } 852 return 0; 853 } else { 854 /* 855 * Read CPU Address Map Registers 856 */ 857 uint32_t basereg, ctrlreg, ta, tamask; 858 859 ta = MVSOC_MLMB_WCR_TARGET(mvsoc_tags[i].target) | 860 MVSOC_MLMB_WCR_ATTR(mvsoc_tags[i].attr); 861 tamask = MVSOC_MLMB_WCR_TARGET(MVSOC_UNITID_MASK) | 862 MVSOC_MLMB_WCR_ATTR(MARVELL_ATTR_MASK); 863 864 if (base != NULL) 865 *base = 0; 866 if (size != NULL) 867 *size = 0; 868 869 for (i = 0; i < nwindow; i++) { 870 ctrlreg = read_mlmbreg(MVSOC_MLMB_WCR(i)); 871 if ((ctrlreg & tamask) != ta) 872 continue; 873 if (ctrlreg & MVSOC_MLMB_WCR_WINEN) { 874 basereg = read_mlmbreg(MVSOC_MLMB_WBR(i)); 875 876 if (base != NULL) 877 *base = 878 basereg & MVSOC_MLMB_WBR_BASE_MASK; 879 if (size != NULL) 880 *size = (ctrlreg & 881 MVSOC_MLMB_WCR_SIZE_MASK) + 882 (~MVSOC_MLMB_WCR_SIZE_MASK + 1); 883 } 884 break; 885 } 886 return i; 887 } 888 } 889
Indexes created Thu Oct 23 22:10:10 GMT 2025