mvsoc.c revision 1.16
1 /* $NetBSD: mvsoc.c,v 1.16 2013/12/23 04:12:09 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.16 2013/12/23 04:12:09 kiyohara Exp $"); 30 31 #include "opt_cputypes.h" 32 #include "opt_mvsoc.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pcireg.h> 41 #include <dev/marvell/marvellreg.h> 42 #include <dev/marvell/marvellvar.h> 43 44 #include <arm/marvell/mvsocreg.h> 45 #include <arm/marvell/mvsocvar.h> 46 #include <arm/marvell/orionreg.h> 47 #include <arm/marvell/kirkwoodreg.h> 48 #include <arm/marvell/mv78xx0reg.h> 49 #include <arm/marvell/armadaxpreg.h> 50 51 #include <uvm/uvm.h> 52 53 #include "locators.h" 54 55 #ifdef MVSOC_CONSOLE_EARLY 56 #include <dev/ic/ns16550reg.h> 57 #include <dev/ic/comreg.h> 58 #include <dev/cons.h> 59 #endif 60 61 static int mvsoc_match(device_t, struct cfdata *, void *); 62 static void mvsoc_attach(device_t, device_t, void *); 63 64 static int mvsoc_print(void *, const char *); 65 static int mvsoc_search(device_t, cfdata_t, const int *, void *); 66 67 uint32_t mvPclk, mvSysclk, mvTclk = 0; 68 int nwindow = 0, nremap = 0; 69 static vaddr_t regbase = 0xffffffff, dsc_base, pex_base; 70 vaddr_t mlmb_base; 71 72 void (*mvsoc_intr_init)(void); 73 int (*mvsoc_clkgating)(struct marvell_attach_args *); 74 75 76 #ifdef MVSOC_CONSOLE_EARLY 77 static vaddr_t com_base; 78 79 static inline uint32_t 80 uart_read(bus_size_t o) 81 { 82 return *(volatile uint32_t *)(com_base + (o << 2)); 83 } 84 85 static inline void 86 uart_write(bus_size_t o, uint32_t v) 87 { 88 *(volatile uint32_t *)(com_base + (o << 2)) = v; 89 } 90 91 static int 92 mvsoc_cngetc(dev_t dv) 93 { 94 if ((uart_read(com_lsr) & LSR_RXRDY) == 0) 95 return -1; 96 97 return uart_read(com_data) & 0xff; 98 } 99 100 static void 101 mvsoc_cnputc(dev_t dv, int c) 102 { 103 int timo = 150000; 104 105 while ((uart_read(com_lsr) & LSR_TXRDY) == 0 && --timo > 0) 106 ; 107 108 uart_write(com_data, c); 109 110 timo = 150000; 111 while ((uart_read(com_lsr) & LSR_TSRE) == 0 && --timo > 0) 112 ; 113 } 114 115 static struct consdev mvsoc_earlycons = { 116 .cn_putc = mvsoc_cnputc, 117 .cn_getc = mvsoc_cngetc, 118 .cn_pollc = nullcnpollc, 119 }; 120 #endif 121 122 123 /* attributes */ 124 static struct { 125 int tag; 126 uint32_t attr; 127 uint32_t target; 128 } mvsoc_tags[] = { 129 { MARVELL_TAG_SDRAM_CS0, 130 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 131 { MARVELL_TAG_SDRAM_CS1, 132 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 133 { MARVELL_TAG_SDRAM_CS2, 134 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 135 { MARVELL_TAG_SDRAM_CS3, 136 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 137 138 #if defined(ORION) 139 { ORION_TAG_DEVICE_CS0, 140 ORION_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 141 { ORION_TAG_DEVICE_CS1, 142 ORION_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 143 { ORION_TAG_DEVICE_CS2, 144 ORION_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 145 { ORION_TAG_DEVICE_BOOTCS, 146 ORION_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 147 { ORION_TAG_FLASH_CS, 148 ORION_ATTR_FLASH_CS, MVSOC_UNITID_DEVBUS }, 149 { ORION_TAG_PEX0_MEM, 150 ORION_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 151 { ORION_TAG_PEX0_IO, 152 ORION_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 153 { ORION_TAG_PEX1_MEM, 154 ORION_ATTR_PEX_MEM, ORION_UNITID_PEX1 }, 155 { ORION_TAG_PEX1_IO, 156 ORION_ATTR_PEX_IO, ORION_UNITID_PEX1 }, 157 { ORION_TAG_PCI_MEM, 158 ORION_ATTR_PCI_MEM, ORION_UNITID_PCI }, 159 { ORION_TAG_PCI_IO, 160 ORION_ATTR_PCI_IO, ORION_UNITID_PCI }, 161 { ORION_TAG_CRYPT, 162 ORION_ATTR_CRYPT, ORION_UNITID_CRYPT }, 163 #endif 164 165 #if defined(KIRKWOOD) 166 { KIRKWOOD_TAG_NAND, 167 KIRKWOOD_ATTR_NAND, MVSOC_UNITID_DEVBUS }, 168 { KIRKWOOD_TAG_SPI, 169 KIRKWOOD_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 170 { KIRKWOOD_TAG_BOOTROM, 171 KIRKWOOD_ATTR_BOOTROM, MVSOC_UNITID_DEVBUS }, 172 { KIRKWOOD_TAG_PEX_MEM, 173 KIRKWOOD_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 174 { KIRKWOOD_TAG_PEX_IO, 175 KIRKWOOD_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 176 { KIRKWOOD_TAG_PEX1_MEM, 177 KIRKWOOD_ATTR_PEX1_MEM, MVSOC_UNITID_PEX }, 178 { KIRKWOOD_TAG_PEX1_IO, 179 KIRKWOOD_ATTR_PEX1_IO, MVSOC_UNITID_PEX }, 180 { KIRKWOOD_TAG_CRYPT, 181 KIRKWOOD_ATTR_CRYPT, KIRKWOOD_UNITID_CRYPT }, 182 #endif 183 184 #if defined(MV78XX0) 185 { MV78XX0_TAG_DEVICE_CS0, 186 MV78XX0_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 187 { MV78XX0_TAG_DEVICE_CS1, 188 MV78XX0_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 189 { MV78XX0_TAG_DEVICE_CS2, 190 MV78XX0_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 191 { MV78XX0_TAG_DEVICE_CS3, 192 MV78XX0_ATTR_DEVICE_CS3, MVSOC_UNITID_DEVBUS }, 193 { MV78XX0_TAG_DEVICE_BOOTCS, 194 MV78XX0_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 195 { MV78XX0_TAG_SPI, 196 MV78XX0_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 197 { MV78XX0_TAG_PEX0_MEM, 198 MV78XX0_ATTR_PEX_0_MEM, MVSOC_UNITID_PEX }, 199 { MV78XX0_TAG_PEX01_MEM, 200 MV78XX0_ATTR_PEX_1_MEM, MVSOC_UNITID_PEX }, 201 { MV78XX0_TAG_PEX02_MEM, 202 MV78XX0_ATTR_PEX_2_MEM, MVSOC_UNITID_PEX }, 203 { MV78XX0_TAG_PEX03_MEM, 204 MV78XX0_ATTR_PEX_3_MEM, MVSOC_UNITID_PEX }, 205 { MV78XX0_TAG_PEX0_IO, 206 MV78XX0_ATTR_PEX_0_IO, MVSOC_UNITID_PEX }, 207 { MV78XX0_TAG_PEX01_IO, 208 MV78XX0_ATTR_PEX_1_IO, MVSOC_UNITID_PEX }, 209 { MV78XX0_TAG_PEX02_IO, 210 MV78XX0_ATTR_PEX_2_IO, MVSOC_UNITID_PEX }, 211 { MV78XX0_TAG_PEX03_IO, 212 MV78XX0_ATTR_PEX_3_IO, MVSOC_UNITID_PEX }, 213 { MV78XX0_TAG_PEX1_MEM, 214 MV78XX0_ATTR_PEX_0_MEM, MV78XX0_UNITID_PEX1 }, 215 { MV78XX0_TAG_PEX11_MEM, 216 MV78XX0_ATTR_PEX_1_MEM, MV78XX0_UNITID_PEX1 }, 217 { MV78XX0_TAG_PEX12_MEM, 218 MV78XX0_ATTR_PEX_2_MEM, MV78XX0_UNITID_PEX1 }, 219 { MV78XX0_TAG_PEX13_MEM, 220 MV78XX0_ATTR_PEX_3_MEM, MV78XX0_UNITID_PEX1 }, 221 { MV78XX0_TAG_PEX1_IO, 222 MV78XX0_ATTR_PEX_0_IO, MV78XX0_UNITID_PEX1 }, 223 { MV78XX0_TAG_PEX11_IO, 224 MV78XX0_ATTR_PEX_1_IO, MV78XX0_UNITID_PEX1 }, 225 { MV78XX0_TAG_PEX12_IO, 226 MV78XX0_ATTR_PEX_2_IO, MV78XX0_UNITID_PEX1 }, 227 { MV78XX0_TAG_PEX13_IO, 228 MV78XX0_ATTR_PEX_3_IO, MV78XX0_UNITID_PEX1 }, 229 { MV78XX0_TAG_CRYPT, 230 MV78XX0_ATTR_CRYPT, MV78XX0_UNITID_CRYPT }, 231 #endif 232 233 #if defined(ARMADAXP) 234 { ARMADAXP_TAG_PEX00_MEM, 235 ARMADAXP_ATTR_PEXx0_MEM, ARMADAXP_UNITID_PEX0 }, 236 { ARMADAXP_TAG_PEX00_IO, 237 ARMADAXP_ATTR_PEXx0_IO, ARMADAXP_UNITID_PEX0 }, 238 { ARMADAXP_TAG_PEX01_MEM, 239 ARMADAXP_ATTR_PEXx1_MEM, ARMADAXP_UNITID_PEX0 }, 240 { ARMADAXP_TAG_PEX01_IO, 241 ARMADAXP_ATTR_PEXx1_IO, ARMADAXP_UNITID_PEX0 }, 242 { ARMADAXP_TAG_PEX02_MEM, 243 ARMADAXP_ATTR_PEXx2_MEM, ARMADAXP_UNITID_PEX0 }, 244 { ARMADAXP_TAG_PEX02_IO, 245 ARMADAXP_ATTR_PEXx2_IO, ARMADAXP_UNITID_PEX0 }, 246 { ARMADAXP_TAG_PEX03_MEM, 247 ARMADAXP_ATTR_PEXx3_MEM, ARMADAXP_UNITID_PEX0 }, 248 { ARMADAXP_TAG_PEX03_IO, 249 ARMADAXP_ATTR_PEXx3_IO, ARMADAXP_UNITID_PEX0 }, 250 { ARMADAXP_TAG_PEX2_MEM, 251 ARMADAXP_ATTR_PEX2_MEM, ARMADAXP_UNITID_PEX2 }, 252 { ARMADAXP_TAG_PEX2_IO, 253 ARMADAXP_ATTR_PEX2_IO, ARMADAXP_UNITID_PEX2 }, 254 { ARMADAXP_TAG_PEX3_MEM, 255 ARMADAXP_ATTR_PEX3_MEM, ARMADAXP_UNITID_PEX3 }, 256 { ARMADAXP_TAG_PEX3_IO, 257 ARMADAXP_ATTR_PEX3_IO, ARMADAXP_UNITID_PEX3 }, 258 #endif 259 }; 260 261 #if defined(ARMADAXP) 262 #undef ARMADAXP 263 #define ARMADAXP(m) MARVELL_ARMADAXP_ ## m 264 #endif 265 #if defined(ORION) 266 #define ORION_1(m) MARVELL_ORION_1_ ## m 267 #define ORION_2(m) MARVELL_ORION_2_ ## m 268 #endif 269 #if defined(KIRKWOOD) 270 #undef KIRKWOOD 271 #define KIRKWOOD(m) MARVELL_KIRKWOOD_ ## m 272 #endif 273 #if defined(MV78XX0) 274 #undef MV78XX0 275 #define MV78XX0(m) MARVELL_MV78XX0_ ## m 276 #endif 277 static struct { 278 uint16_t model; 279 uint8_t rev; 280 const char *modelstr; 281 const char *revstr; 282 const char *typestr; 283 } nametbl[] = { 284 #if defined(ORION) 285 { ORION_1(88F1181), 0, "MV88F1181", NULL, "Orion1" }, 286 { ORION_1(88F5082), 2, "MV88F5082", "A2", "Orion1" }, 287 { ORION_1(88F5180N), 3, "MV88F5180N","B1", "Orion1" }, 288 { ORION_1(88F5181), 0, "MV88F5181", "A0", "Orion1" }, 289 { ORION_1(88F5181), 1, "MV88F5181", "A1", "Orion1" }, 290 { ORION_1(88F5181), 2, "MV88F5181", "B0", "Orion1" }, 291 { ORION_1(88F5181), 3, "MV88F5181", "B1", "Orion1" }, 292 { ORION_1(88F5181), 8, "MV88F5181L","A0", "Orion1" }, 293 { ORION_1(88F5181), 9, "MV88F5181L","A1", "Orion1" }, 294 { ORION_1(88F5182), 0, "MV88F5182", "A0", "Orion1" }, 295 { ORION_1(88F5182), 1, "MV88F5182", "A1", "Orion1" }, 296 { ORION_1(88F5182), 2, "MV88F5182", "A2", "Orion1" }, 297 { ORION_1(88F6082), 0, "MV88F6082", "A0", "Orion1" }, 298 { ORION_1(88F6082), 1, "MV88F6082", "A1", "Orion1" }, 299 { ORION_1(88F6183), 0, "MV88F6183", "A0", "Orion1" }, 300 { ORION_1(88F6183), 1, "MV88F6183", "Z0", "Orion1" }, 301 { ORION_1(88W8660), 0, "MV88W8660", "A0", "Orion1" }, 302 { ORION_1(88W8660), 1, "MV88W8660", "A1", "Orion1" }, 303 304 { ORION_2(88F1281), 0, "MV88F1281", "A0", "Orion2" }, 305 { ORION_2(88F5281), 0, "MV88F5281", "A0", "Orion2" }, 306 { ORION_2(88F5281), 1, "MV88F5281", "B0", "Orion2" }, 307 { ORION_2(88F5281), 2, "MV88F5281", "C0", "Orion2" }, 308 { ORION_2(88F5281), 3, "MV88F5281", "C1", "Orion2" }, 309 { ORION_2(88F5281), 4, "MV88F5281", "D0", "Orion2" }, 310 #endif 311 312 #if defined(KIRKWOOD) 313 { KIRKWOOD(88F6180), 2, "88F6180", "A0", "Kirkwood" }, 314 { KIRKWOOD(88F6180), 3, "88F6180", "A1", "Kirkwood" }, 315 { KIRKWOOD(88F6192), 0, "88F619x", "Z0", "Kirkwood" }, 316 { KIRKWOOD(88F6192), 2, "88F619x", "A0", "Kirkwood" }, 317 { KIRKWOOD(88F6192), 3, "88F619x", "A1", "Kirkwood" }, 318 { KIRKWOOD(88F6281), 0, "88F6281", "Z0", "Kirkwood" }, 319 { KIRKWOOD(88F6281), 2, "88F6281", "A0", "Kirkwood" }, 320 { KIRKWOOD(88F6281), 3, "88F6281", "A1", "Kirkwood" }, 321 { KIRKWOOD(88F6282), 0, "88F6282", "A0", "Kirkwood" }, 322 { KIRKWOOD(88F6282), 1, "88F6282", "A1", "Kirkwood" }, 323 #endif 324 325 #if defined(MV78XX0) 326 { MV78XX0(MV78100), 1, "MV78100", "A0", "Discovery Innovation" }, 327 { MV78XX0(MV78100), 2, "MV78100", "A1", "Discovery Innovation" }, 328 { MV78XX0(MV78200), 1, "MV78200", "A0", "Discovery Innovation" }, 329 #endif 330 331 #if defined(ARMADAXP) 332 { ARMADAXP(MV78130), 1, "MV78130", "A0", "Armada XP" }, 333 { ARMADAXP(MV78160), 1, "MV78160", "A0", "Armada XP" }, 334 { ARMADAXP(MV78230), 1, "MV78260", "A0", "Armada XP" }, 335 { ARMADAXP(MV78260), 1, "MV78260", "A0", "Armada XP" }, 336 { ARMADAXP(MV78460), 1, "MV78460", "A0", "Armada XP" }, 337 { ARMADAXP(MV78460), 2, "MV78460", "B0", "Armada XP" }, 338 #endif 339 }; 340 341 #define OFFSET_DEFAULT MVA_OFFSET_DEFAULT 342 #define IRQ_DEFAULT MVA_IRQ_DEFAULT 343 static const struct mvsoc_periph { 344 int model; 345 const char *name; 346 int unit; 347 bus_size_t offset; 348 int irq; 349 } mvsoc_periphs[] = { 350 #if defined(ORION) 351 #define ORION_IRQ_TMR (32 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 352 353 { ORION_1(88F1181), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 354 { ORION_1(88F1181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 355 { ORION_1(88F1181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 356 { ORION_1(88F1181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 357 { ORION_1(88F1181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 358 { ORION_1(88F1181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 359 { ORION_1(88F1181), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 360 361 { ORION_1(88F5082), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 362 { ORION_1(88F5082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 363 { ORION_1(88F5082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 364 { ORION_1(88F5082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 365 { ORION_1(88F5082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 366 { ORION_1(88F5082), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 367 { ORION_1(88F5082), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 368 { ORION_1(88F5082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 369 { ORION_1(88F5082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 370 { ORION_1(88F5082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 371 { ORION_1(88F5082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 372 { ORION_1(88F5082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 373 374 { ORION_1(88F5180N),"mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 375 { ORION_1(88F5180N),"mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 376 { ORION_1(88F5180N),"com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 377 { ORION_1(88F5180N),"com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 378 { ORION_1(88F5180N),"ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 379 { ORION_1(88F5180N),"gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 380 { ORION_1(88F5180N),"gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 381 { ORION_1(88F5180N),"gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 382 { ORION_1(88F5180N),"mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 383 { ORION_1(88F5180N),"mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 384 385 { ORION_1(88F5181), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 386 { ORION_1(88F5181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 387 { ORION_1(88F5181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 388 { ORION_1(88F5181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 389 { ORION_1(88F5181), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 390 { ORION_1(88F5181), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 391 { ORION_1(88F5181), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 392 { ORION_1(88F5181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 393 { ORION_1(88F5181), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 394 { ORION_1(88F5181), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 395 { ORION_1(88F5181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 396 397 { ORION_1(88F5182), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 398 { ORION_1(88F5182), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 399 { ORION_1(88F5182), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 400 { ORION_1(88F5182), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 401 { ORION_1(88F5182), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 402 { ORION_1(88F5182), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 403 { ORION_1(88F5182), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 404 { ORION_1(88F5182), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 405 { ORION_1(88F5182), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 406 { ORION_1(88F5182), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 407 { ORION_1(88F5182), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 408 { ORION_1(88F5182), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 409 410 { ORION_1(88F6082), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 411 { ORION_1(88F6082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 412 { ORION_1(88F6082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 413 { ORION_1(88F6082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 414 { ORION_1(88F6082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 415 { ORION_1(88F6082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 416 { ORION_1(88F6082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 417 { ORION_1(88F6082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 418 { ORION_1(88F6082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 419 { ORION_1(88F6082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 420 421 { ORION_1(88F6183), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 422 { ORION_1(88F6183), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 423 { ORION_1(88F6183), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 424 { ORION_1(88F6183), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 425 426 { ORION_1(88W8660), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 427 { ORION_1(88W8660), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 428 { ORION_1(88W8660), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 429 { ORION_1(88W8660), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 430 { ORION_1(88W8660), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 431 { ORION_1(88W8660), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 432 { ORION_1(88W8660), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 433 { ORION_1(88W8660), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 434 { ORION_1(88W8660), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 435 { ORION_1(88W8660), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 436 437 { ORION_2(88F1281), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 438 { ORION_2(88F1281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 439 { ORION_2(88F1281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 440 { ORION_2(88F1281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 441 { ORION_2(88F1281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 442 { ORION_2(88F1281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 443 { ORION_2(88F1281), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 444 445 { ORION_2(88F5281), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 446 { ORION_2(88F5281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 447 { ORION_2(88F5281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 448 { ORION_2(88F5281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 449 { ORION_2(88F5281), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 450 { ORION_2(88F5281), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 451 { ORION_2(88F5281), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 452 { ORION_2(88F5281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 453 { ORION_2(88F5281), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 454 { ORION_2(88F5281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 455 #endif 456 457 #if defined(KIRKWOOD) 458 #define KIRKWOOD_IRQ_TMR (64 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 459 460 { KIRKWOOD(88F6180),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 461 { KIRKWOOD(88F6180),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 462 { KIRKWOOD(88F6180),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 463 { KIRKWOOD(88F6180),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 464 { KIRKWOOD(88F6180),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 465 { KIRKWOOD(88F6180),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 466 { KIRKWOOD(88F6180),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 467 { KIRKWOOD(88F6180),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 468 { KIRKWOOD(88F6180),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 469 { KIRKWOOD(88F6180),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 470 { KIRKWOOD(88F6180),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 471 { KIRKWOOD(88F6180),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 472 473 { KIRKWOOD(88F6192),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 474 { KIRKWOOD(88F6192),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 475 { KIRKWOOD(88F6192),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 476 { KIRKWOOD(88F6192),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 477 { KIRKWOOD(88F6192),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 478 { KIRKWOOD(88F6192),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 479 { KIRKWOOD(88F6192),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 480 { KIRKWOOD(88F6192),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 481 { KIRKWOOD(88F6192),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 482 { KIRKWOOD(88F6192),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 483 { KIRKWOOD(88F6192),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 484 { KIRKWOOD(88F6192),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 485 { KIRKWOOD(88F6192),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 486 { KIRKWOOD(88F6192),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 487 488 { KIRKWOOD(88F6281),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 489 { KIRKWOOD(88F6281),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 490 { KIRKWOOD(88F6281),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 491 { KIRKWOOD(88F6281),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 492 { KIRKWOOD(88F6281),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 493 { KIRKWOOD(88F6281),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 494 { KIRKWOOD(88F6281),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 495 { KIRKWOOD(88F6281),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 496 { KIRKWOOD(88F6281),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT }, 497 { KIRKWOOD(88F6281),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 498 { KIRKWOOD(88F6281),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 499 { KIRKWOOD(88F6281),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 500 { KIRKWOOD(88F6281),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 501 { KIRKWOOD(88F6281),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 502 503 { KIRKWOOD(88F6282),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 504 { KIRKWOOD(88F6282),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 505 { KIRKWOOD(88F6282),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 506 { KIRKWOOD(88F6282),"mvsocts", 0, KIRKWOOD_TS_BASE, IRQ_DEFAULT }, 507 { KIRKWOOD(88F6282),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 508 { KIRKWOOD(88F6282),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 509 { KIRKWOOD(88F6282),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 510 { KIRKWOOD(88F6282),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 511 { KIRKWOOD(88F6282),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 512 { KIRKWOOD(88F6282),"gttwsi", 1, KIRKWOOD_TWSI1_BASE,KIRKWOOD_IRQ_TWSI1 }, 513 { KIRKWOOD(88F6282),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 514 { KIRKWOOD(88F6282),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 515 { KIRKWOOD(88F6282),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 516 { KIRKWOOD(88F6282),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 517 { KIRKWOOD(88F6282),"mvpex", 1, KIRKWOOD_PEX1_BASE,KIRKWOOD_IRQ_PEX1INT }, 518 { KIRKWOOD(88F6282),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 519 { KIRKWOOD(88F6282),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 520 #endif 521 522 #if defined(MV78XX0) 523 { MV78XX0(MV78100), "mvsoctmr",0, MVSOC_TMR_BASE, MV78XX0_IRQ_TIMER0 }, 524 { MV78XX0(MV78100), "mvsocgpp",0, MVSOC_GPP_BASE, MV78XX0_IRQ_GPIO0_7 }, 525 { MV78XX0(MV78100), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0 }, 526 { MV78XX0(MV78100), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1 }, 527 { MV78XX0(MV78100), "com", 2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 }, 528 { MV78XX0(MV78100), "com", 3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 }, 529 { MV78XX0(MV78100), "gttwsi", 0, MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI0 }, 530 { MV78XX0(MV78100), "gttwsi", 1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 }, 531 { MV78XX0(MV78100), "mvgbec", 0, MV78XX0_GBE0_BASE,IRQ_DEFAULT }, 532 { MV78XX0(MV78100), "mvgbec", 1, MV78XX0_GBE1_BASE,IRQ_DEFAULT }, 533 { MV78XX0(MV78100), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA }, 534 535 { MV78XX0(MV78200), "mvsoctmr",0, MVSOC_TMR_BASE, MV78XX0_IRQ_TIMER0 }, 536 { MV78XX0(MV78200), "mvsocgpp",0, MVSOC_GPP_BASE, MV78XX0_IRQ_GPIO0_7 }, 537 { MV78XX0(MV78200), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0 }, 538 { MV78XX0(MV78200), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1 }, 539 { MV78XX0(MV78200), "com", 2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 }, 540 { MV78XX0(MV78200), "com", 3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 }, 541 { MV78XX0(MV78200), "gttwsi", 0, MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI0 }, 542 { MV78XX0(MV78200), "gttwsi", 1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 }, 543 { MV78XX0(MV78200), "mvgbec", 0, MV78XX0_GBE0_BASE,IRQ_DEFAULT }, 544 { MV78XX0(MV78200), "mvgbec", 1, MV78XX0_GBE1_BASE,IRQ_DEFAULT }, 545 { MV78XX0(MV78200), "mvgbec", 2, MV78XX0_GBE2_BASE,IRQ_DEFAULT }, 546 { MV78XX0(MV78200), "mvgbec", 3, MV78XX0_GBE3_BASE,IRQ_DEFAULT }, 547 { MV78XX0(MV78200), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA }, 548 #endif 549 550 #if defined(ARMADAXP) 551 { ARMADAXP(MV78130), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 552 { ARMADAXP(MV78130), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 553 { ARMADAXP(MV78130), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 554 { ARMADAXP(MV78130), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 555 { ARMADAXP(MV78130), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 556 { ARMADAXP(MV78130), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 557 { ARMADAXP(MV78130), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 558 { ARMADAXP(MV78130), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 559 { ARMADAXP(MV78130), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 560 { ARMADAXP(MV78130), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 561 { ARMADAXP(MV78130), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 562 { ARMADAXP(MV78130), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 563 { ARMADAXP(MV78130), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 564 { ARMADAXP(MV78130), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 565 { ARMADAXP(MV78130), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 566 { ARMADAXP(MV78130), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 567 { ARMADAXP(MV78130), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 568 { ARMADAXP(MV78130), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 569 { ARMADAXP(MV78130), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 570 { ARMADAXP(MV78130), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 571 { ARMADAXP(MV78130), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 572 { ARMADAXP(MV78130), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 573 { ARMADAXP(MV78130), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 574 { ARMADAXP(MV78130), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 575 { ARMADAXP(MV78130), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 576 577 { ARMADAXP(MV78160), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 578 { ARMADAXP(MV78160), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 579 { ARMADAXP(MV78160), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 580 { ARMADAXP(MV78160), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 581 { ARMADAXP(MV78160), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 582 { ARMADAXP(MV78160), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 583 { ARMADAXP(MV78160), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 584 { ARMADAXP(MV78160), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 585 { ARMADAXP(MV78160), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 586 { ARMADAXP(MV78160), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 587 { ARMADAXP(MV78160), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 588 { ARMADAXP(MV78160), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 589 { ARMADAXP(MV78160), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 590 { ARMADAXP(MV78160), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 591 { ARMADAXP(MV78160), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 592 { ARMADAXP(MV78160), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 593 { ARMADAXP(MV78160), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 594 { ARMADAXP(MV78160), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 595 { ARMADAXP(MV78160), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 596 { ARMADAXP(MV78160), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 597 { ARMADAXP(MV78160), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 598 { ARMADAXP(MV78160), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 599 { ARMADAXP(MV78160), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 600 { ARMADAXP(MV78160), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 601 { ARMADAXP(MV78160), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 602 { ARMADAXP(MV78160), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 603 { ARMADAXP(MV78160), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 604 605 { ARMADAXP(MV78230), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 606 { ARMADAXP(MV78230), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 607 { ARMADAXP(MV78230), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 608 { ARMADAXP(MV78230), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 609 { ARMADAXP(MV78230), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 610 { ARMADAXP(MV78230), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 611 { ARMADAXP(MV78230), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 612 { ARMADAXP(MV78230), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 613 { ARMADAXP(MV78230), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 614 { ARMADAXP(MV78230), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 615 { ARMADAXP(MV78230), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 616 { ARMADAXP(MV78230), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 617 { ARMADAXP(MV78230), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 618 { ARMADAXP(MV78230), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 619 { ARMADAXP(MV78230), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 620 { ARMADAXP(MV78230), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 621 { ARMADAXP(MV78230), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 622 { ARMADAXP(MV78230), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 623 { ARMADAXP(MV78230), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 624 { ARMADAXP(MV78230), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 625 { ARMADAXP(MV78230), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 626 { ARMADAXP(MV78230), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 627 { ARMADAXP(MV78230), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 628 { ARMADAXP(MV78230), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 629 { ARMADAXP(MV78230), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 630 { ARMADAXP(MV78230), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 631 632 { ARMADAXP(MV78260), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 633 { ARMADAXP(MV78260), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 634 { ARMADAXP(MV78260), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 635 { ARMADAXP(MV78260), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 636 { ARMADAXP(MV78260), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 637 { ARMADAXP(MV78260), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 638 { ARMADAXP(MV78260), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 639 { ARMADAXP(MV78260), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 640 { ARMADAXP(MV78260), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 641 { ARMADAXP(MV78260), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 642 { ARMADAXP(MV78260), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 643 { ARMADAXP(MV78260), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 644 { ARMADAXP(MV78260), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 645 { ARMADAXP(MV78260), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 646 { ARMADAXP(MV78260), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 647 { ARMADAXP(MV78260), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 648 { ARMADAXP(MV78260), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 649 { ARMADAXP(MV78260), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 650 { ARMADAXP(MV78260), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 651 { ARMADAXP(MV78260), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 652 { ARMADAXP(MV78260), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 653 { ARMADAXP(MV78260), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 654 { ARMADAXP(MV78260), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 655 { ARMADAXP(MV78260), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 656 { ARMADAXP(MV78260), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 657 { ARMADAXP(MV78260), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 658 { ARMADAXP(MV78260), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 659 660 { ARMADAXP(MV78460), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 661 { ARMADAXP(MV78460), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 662 { ARMADAXP(MV78460), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 663 { ARMADAXP(MV78460), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 664 { ARMADAXP(MV78460), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 665 { ARMADAXP(MV78460), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 666 { ARMADAXP(MV78460), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 667 { ARMADAXP(MV78460), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 668 { ARMADAXP(MV78460), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 669 { ARMADAXP(MV78460), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 670 { ARMADAXP(MV78460), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 671 { ARMADAXP(MV78460), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 672 { ARMADAXP(MV78460), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 673 { ARMADAXP(MV78460), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 674 { ARMADAXP(MV78460), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 675 { ARMADAXP(MV78460), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 676 { ARMADAXP(MV78460), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 677 { ARMADAXP(MV78460), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 678 { ARMADAXP(MV78460), "mvpex", 5, ARMADAXP_PEX3_BASE,ARMADAXP_IRQ_PEX3 }, 679 { ARMADAXP(MV78460), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 680 { ARMADAXP(MV78460), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 681 { ARMADAXP(MV78460), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 682 { ARMADAXP(MV78460), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 683 { ARMADAXP(MV78460), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 684 { ARMADAXP(MV78460), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 685 { ARMADAXP(MV78460), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 686 { ARMADAXP(MV78460), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 687 { ARMADAXP(MV78460), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 688 #endif 689 }; 690 691 692 CFATTACH_DECL_NEW(mvsoc, sizeof(struct mvsoc_softc), 693 mvsoc_match, mvsoc_attach, NULL, NULL); 694 695 /* ARGSUSED */ 696 static int 697 mvsoc_match(device_t parent, struct cfdata *match, void *aux) 698 { 699 700 return 1; 701 } 702 703 /* ARGSUSED */ 704 static void 705 mvsoc_attach(device_t parent, device_t self, void *aux) 706 { 707 struct mvsoc_softc *sc = device_private(self); 708 struct marvell_attach_args mva; 709 uint16_t model; 710 uint8_t rev; 711 int i; 712 713 sc->sc_dev = self; 714 sc->sc_iot = &mvsoc_bs_tag; 715 sc->sc_addr = vtophys(regbase); 716 sc->sc_dmat = &mvsoc_bus_dma_tag; 717 if (bus_space_map(sc->sc_iot, sc->sc_addr, 0x100000, 0, &sc->sc_ioh) != 718 0) { 719 aprint_error_dev(self, "can't map registers\n"); 720 return; 721 } 722 723 model = mvsoc_model(); 724 rev = mvsoc_rev(); 725 for (i = 0; i < __arraycount(nametbl); i++) 726 if (nametbl[i].model == model && nametbl[i].rev == rev) 727 break; 728 if (i >= __arraycount(nametbl)) 729 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 730 731 aprint_normal(": Marvell %s %s%s %s\n", 732 nametbl[i].modelstr, 733 nametbl[i].revstr != NULL ? "Rev. " : "", 734 nametbl[i].revstr != NULL ? nametbl[i].revstr : "", 735 nametbl[i].typestr); 736 aprint_normal("%s: CPU Clock %d.%03d MHz" 737 " SysClock %d.%03d MHz TClock %d.%03d MHz\n", 738 device_xname(self), 739 mvPclk / 1000000, (mvPclk / 1000) % 1000, 740 mvSysclk / 1000000, (mvSysclk / 1000) % 1000, 741 mvTclk / 1000000, (mvTclk / 1000) % 1000); 742 aprint_naive("\n"); 743 744 mvsoc_intr_init(); 745 746 for (i = 0; i < __arraycount(mvsoc_periphs); i++) { 747 if (mvsoc_periphs[i].model != model) 748 continue; 749 750 mva.mva_name = mvsoc_periphs[i].name; 751 mva.mva_model = model; 752 mva.mva_revision = rev; 753 mva.mva_iot = sc->sc_iot; 754 mva.mva_ioh = sc->sc_ioh; 755 mva.mva_unit = mvsoc_periphs[i].unit; 756 mva.mva_addr = sc->sc_addr; 757 mva.mva_offset = mvsoc_periphs[i].offset; 758 mva.mva_size = 0; 759 mva.mva_dmat = sc->sc_dmat; 760 mva.mva_irq = mvsoc_periphs[i].irq; 761 762 /* Skip clock disabled devices */ 763 if (mvsoc_clkgating != NULL && mvsoc_clkgating(&mva)) { 764 aprint_normal_dev(self, "%s%d clock disabled\n", 765 mvsoc_periphs[i].name, mvsoc_periphs[i].unit); 766 continue; 767 } 768 769 config_found_sm_loc(sc->sc_dev, "mvsoc", NULL, &mva, 770 mvsoc_print, mvsoc_search); 771 } 772 } 773 774 static int 775 mvsoc_print(void *aux, const char *pnp) 776 { 777 struct marvell_attach_args *mva = aux; 778 779 if (pnp) 780 aprint_normal("%s at %s unit %d", 781 mva->mva_name, pnp, mva->mva_unit); 782 else { 783 if (mva->mva_unit != MVA_UNIT_DEFAULT) 784 aprint_normal(" unit %d", mva->mva_unit); 785 if (mva->mva_offset != MVA_OFFSET_DEFAULT) { 786 aprint_normal(" offset 0x%04lx", mva->mva_offset); 787 if (mva->mva_size > 0) 788 aprint_normal("-0x%04lx", 789 mva->mva_offset + mva->mva_size - 1); 790 } 791 if (mva->mva_irq != MVA_IRQ_DEFAULT) 792 aprint_normal(" irq %d", mva->mva_irq); 793 } 794 795 return UNCONF; 796 } 797 798 /* ARGSUSED */ 799 static int 800 mvsoc_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 801 { 802 803 return config_match(parent, cf, aux); 804 } 805 806 /* ARGSUSED */ 807 int 808 marvell_winparams_by_tag(device_t dev, int tag, int *target, int *attribute, 809 uint64_t *base, uint32_t *size) 810 { 811 uint32_t base32; 812 int rv; 813 814 rv = mvsoc_target(tag, target, attribute, &base32, size); 815 *base = base32; 816 if (rv == -1) 817 return -1; 818 return 0; 819 } 820 821 822 /* 823 * These functions is called before bus_space is initialized. 824 */ 825 826 void 827 mvsoc_bootstrap(bus_addr_t iobase) 828 { 829 830 regbase = iobase; 831 dsc_base = iobase + MVSOC_DSC_BASE; 832 mlmb_base = iobase + MVSOC_MLMB_BASE; 833 pex_base = iobase + MVSOC_PEX_BASE; 834 #ifdef MVSOC_CONSOLE_EARLY 835 com_base = iobase + MVSOC_COM0_BASE; 836 cn_tab = &mvsoc_earlycons; 837 printf("Hello\n"); 838 #endif 839 } 840 841 /* 842 * We can read register of PCI configurations from (MVSOC_PEX_BASE + 0). 843 */ 844 uint16_t 845 mvsoc_model(void) 846 { 847 /* 848 * We read product-id from vendor/device register of PCI-Express. 849 */ 850 uint32_t reg; 851 uint16_t model; 852 853 KASSERT(regbase != 0xffffffff); 854 855 reg = *(volatile uint32_t *)(pex_base + PCI_ID_REG); 856 model = PCI_PRODUCT(reg); 857 858 #if defined(ORION) 859 if (model == PCI_PRODUCT_MARVELL_88F5182) { 860 reg = *(volatile uint32_t *)(regbase + ORION_PMI_BASE + 861 ORION_PMI_SAMPLE_AT_RESET); 862 if ((reg & ORION_PMISMPL_TCLK_MASK) == 0) 863 model = PCI_PRODUCT_MARVELL_88F5082; 864 } 865 #endif 866 #if defined(KIRKWOOD) 867 if (model == PCI_PRODUCT_MARVELL_88F6281) { 868 reg = *(volatile uint32_t *)(regbase + KIRKWOOD_MISC_BASE + 869 KIRKWOOD_MISC_DEVICEID); 870 if (reg == 1) /* 88F6192 is 1 */ 871 model = MARVELL_KIRKWOOD_88F6192; 872 } 873 #endif 874 875 return model; 876 } 877 878 uint8_t 879 mvsoc_rev(void) 880 { 881 uint32_t reg; 882 uint8_t rev; 883 884 KASSERT(regbase != 0xffffffff); 885 886 reg = *(volatile uint32_t *)(pex_base + PCI_CLASS_REG); 887 rev = PCI_REVISION(reg); 888 889 return rev; 890 } 891 892 893 int 894 mvsoc_target(int tag, uint32_t *target, uint32_t *attr, uint32_t *base, 895 uint32_t *size) 896 { 897 int i; 898 899 KASSERT(regbase != 0xffffffff); 900 901 if (tag == MVSOC_TAG_INTERNALREG) { 902 if (target != NULL) 903 *target = 0; 904 if (attr != NULL) 905 *attr = 0; 906 if (base != NULL) 907 *base = read_mlmbreg(MVSOC_MLMB_IRBAR) & 908 MVSOC_MLMB_IRBAR_BASE_MASK; 909 if (size != NULL) 910 *size = 0; 911 912 return 0; 913 } 914 915 /* sanity check */ 916 for (i = 0; i < __arraycount(mvsoc_tags); i++) 917 if (mvsoc_tags[i].tag == tag) 918 break; 919 if (i >= __arraycount(mvsoc_tags)) 920 return -1; 921 922 if (target != NULL) 923 *target = mvsoc_tags[i].target; 924 if (attr != NULL) 925 *attr = mvsoc_tags[i].attr; 926 927 if (mvsoc_tags[i].target == MVSOC_UNITID_DDR) { 928 /* 929 * Read DDR SDRAM Controller Address Decode Registers 930 */ 931 uint32_t baseaddrreg, sizereg; 932 int cs = 0; 933 934 switch (mvsoc_tags[i].attr) { 935 case MARVELL_ATTR_SDRAM_CS0: 936 cs = 0; 937 break; 938 case MARVELL_ATTR_SDRAM_CS1: 939 cs = 1; 940 break; 941 case MARVELL_ATTR_SDRAM_CS2: 942 cs = 2; 943 break; 944 case MARVELL_ATTR_SDRAM_CS3: 945 cs = 3; 946 break; 947 } 948 sizereg = *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSSR(cs)); 949 if (sizereg & MVSOC_DSC_CSSR_WINEN) { 950 baseaddrreg = *(volatile uint32_t *)(dsc_base + 951 MVSOC_DSC_CSBAR(cs)); 952 953 if (base != NULL) 954 *base = baseaddrreg & MVSOC_DSC_CSBAR_BASE_MASK; 955 if (size != NULL) 956 *size = (sizereg & MVSOC_DSC_CSSR_SIZE_MASK) + 957 (~MVSOC_DSC_CSSR_SIZE_MASK + 1); 958 } else { 959 if (base != NULL) 960 *base = 0; 961 if (size != NULL) 962 *size = 0; 963 } 964 return 0; 965 } else { 966 /* 967 * Read CPU Address Map Registers 968 */ 969 uint32_t basereg, ctrlreg, ta, tamask; 970 971 ta = MVSOC_MLMB_WCR_TARGET(mvsoc_tags[i].target) | 972 MVSOC_MLMB_WCR_ATTR(mvsoc_tags[i].attr); 973 tamask = MVSOC_MLMB_WCR_TARGET(MVSOC_UNITID_MASK) | 974 MVSOC_MLMB_WCR_ATTR(MARVELL_ATTR_MASK); 975 976 if (base != NULL) 977 *base = 0; 978 if (size != NULL) 979 *size = 0; 980 981 for (i = 0; i < nwindow; i++) { 982 ctrlreg = read_mlmbreg(MVSOC_MLMB_WCR(i)); 983 if ((ctrlreg & tamask) != ta) 984 continue; 985 if (ctrlreg & MVSOC_MLMB_WCR_WINEN) { 986 basereg = read_mlmbreg(MVSOC_MLMB_WBR(i)); 987 988 if (base != NULL) 989 *base = 990 basereg & MVSOC_MLMB_WBR_BASE_MASK; 991 if (size != NULL) 992 *size = (ctrlreg & 993 MVSOC_MLMB_WCR_SIZE_MASK) + 994 (~MVSOC_MLMB_WCR_SIZE_MASK + 1); 995 } 996 break; 997 } 998 return i; 999 } 1000 } 1001
Indexes created Thu Oct 23 22:10:10 GMT 2025