mvsoc.c revision 1.17
1 /* $NetBSD: mvsoc.c,v 1.17 2014/02/17 05:00:38 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2013, 2014 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.17 2014/02/17 05:00:38 kiyohara Exp $"); 30 31 #include "opt_cputypes.h" 32 #include "opt_mvsoc.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pcireg.h> 41 #include <dev/marvell/marvellreg.h> 42 #include <dev/marvell/marvellvar.h> 43 44 #include <arm/marvell/mvsocreg.h> 45 #include <arm/marvell/mvsocvar.h> 46 #include <arm/marvell/orionreg.h> 47 #include <arm/marvell/kirkwoodreg.h> 48 #include <arm/marvell/mv78xx0reg.h> 49 #include <arm/marvell/armadaxpreg.h> 50 51 #include <uvm/uvm.h> 52 53 #include "locators.h" 54 55 #ifdef MVSOC_CONSOLE_EARLY 56 #include <dev/ic/ns16550reg.h> 57 #include <dev/ic/comreg.h> 58 #include <dev/cons.h> 59 #endif 60 61 static int mvsoc_match(device_t, struct cfdata *, void *); 62 static void mvsoc_attach(device_t, device_t, void *); 63 64 static int mvsoc_print(void *, const char *); 65 static int mvsoc_search(device_t, cfdata_t, const int *, void *); 66 67 static int mvsoc_target_ddr(uint32_t, uint32_t *, uint32_t *); 68 static int mvsoc_target_ddr3(uint32_t, uint32_t *, uint32_t *); 69 static int mvsoc_target_peripheral(uint32_t, uint32_t, uint32_t *, uint32_t *); 70 71 uint32_t mvPclk, mvSysclk, mvTclk = 0; 72 int nwindow = 0, nremap = 0; 73 static vaddr_t regbase = 0xffffffff, dsc_base, pex_base; 74 vaddr_t mlmb_base; 75 76 void (*mvsoc_intr_init)(void); 77 int (*mvsoc_clkgating)(struct marvell_attach_args *); 78 79 80 #ifdef MVSOC_CONSOLE_EARLY 81 static vaddr_t com_base; 82 83 static inline uint32_t 84 uart_read(bus_size_t o) 85 { 86 return *(volatile uint32_t *)(com_base + (o << 2)); 87 } 88 89 static inline void 90 uart_write(bus_size_t o, uint32_t v) 91 { 92 *(volatile uint32_t *)(com_base + (o << 2)) = v; 93 } 94 95 static int 96 mvsoc_cngetc(dev_t dv) 97 { 98 if ((uart_read(com_lsr) & LSR_RXRDY) == 0) 99 return -1; 100 101 return uart_read(com_data) & 0xff; 102 } 103 104 static void 105 mvsoc_cnputc(dev_t dv, int c) 106 { 107 int timo = 150000; 108 109 while ((uart_read(com_lsr) & LSR_TXRDY) == 0 && --timo > 0) 110 ; 111 112 uart_write(com_data, c); 113 114 timo = 150000; 115 while ((uart_read(com_lsr) & LSR_TSRE) == 0 && --timo > 0) 116 ; 117 } 118 119 static struct consdev mvsoc_earlycons = { 120 .cn_putc = mvsoc_cnputc, 121 .cn_getc = mvsoc_cngetc, 122 .cn_pollc = nullcnpollc, 123 }; 124 #endif 125 126 127 /* attributes */ 128 static struct { 129 int tag; 130 uint32_t attr; 131 uint32_t target; 132 } mvsoc_tags[] = { 133 { MARVELL_TAG_SDRAM_CS0, 134 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 135 { MARVELL_TAG_SDRAM_CS1, 136 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 137 { MARVELL_TAG_SDRAM_CS2, 138 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 139 { MARVELL_TAG_SDRAM_CS3, 140 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 141 142 { MARVELL_TAG_DDR3_CS0, 143 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 144 { MARVELL_TAG_DDR3_CS1, 145 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 146 { MARVELL_TAG_DDR3_CS2, 147 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 148 { MARVELL_TAG_DDR3_CS3, 149 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 150 151 #if defined(ORION) 152 { ORION_TAG_DEVICE_CS0, 153 ORION_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 154 { ORION_TAG_DEVICE_CS1, 155 ORION_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 156 { ORION_TAG_DEVICE_CS2, 157 ORION_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 158 { ORION_TAG_DEVICE_BOOTCS, 159 ORION_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 160 { ORION_TAG_FLASH_CS, 161 ORION_ATTR_FLASH_CS, MVSOC_UNITID_DEVBUS }, 162 { ORION_TAG_PEX0_MEM, 163 ORION_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 164 { ORION_TAG_PEX0_IO, 165 ORION_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 166 { ORION_TAG_PEX1_MEM, 167 ORION_ATTR_PEX_MEM, ORION_UNITID_PEX1 }, 168 { ORION_TAG_PEX1_IO, 169 ORION_ATTR_PEX_IO, ORION_UNITID_PEX1 }, 170 { ORION_TAG_PCI_MEM, 171 ORION_ATTR_PCI_MEM, ORION_UNITID_PCI }, 172 { ORION_TAG_PCI_IO, 173 ORION_ATTR_PCI_IO, ORION_UNITID_PCI }, 174 { ORION_TAG_CRYPT, 175 ORION_ATTR_CRYPT, ORION_UNITID_CRYPT }, 176 #endif 177 178 #if defined(KIRKWOOD) 179 { KIRKWOOD_TAG_NAND, 180 KIRKWOOD_ATTR_NAND, MVSOC_UNITID_DEVBUS }, 181 { KIRKWOOD_TAG_SPI, 182 KIRKWOOD_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 183 { KIRKWOOD_TAG_BOOTROM, 184 KIRKWOOD_ATTR_BOOTROM, MVSOC_UNITID_DEVBUS }, 185 { KIRKWOOD_TAG_PEX_MEM, 186 KIRKWOOD_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 187 { KIRKWOOD_TAG_PEX_IO, 188 KIRKWOOD_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 189 { KIRKWOOD_TAG_PEX1_MEM, 190 KIRKWOOD_ATTR_PEX1_MEM, MVSOC_UNITID_PEX }, 191 { KIRKWOOD_TAG_PEX1_IO, 192 KIRKWOOD_ATTR_PEX1_IO, MVSOC_UNITID_PEX }, 193 { KIRKWOOD_TAG_CRYPT, 194 KIRKWOOD_ATTR_CRYPT, KIRKWOOD_UNITID_CRYPT }, 195 #endif 196 197 #if defined(MV78XX0) 198 { MV78XX0_TAG_DEVICE_CS0, 199 MV78XX0_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 200 { MV78XX0_TAG_DEVICE_CS1, 201 MV78XX0_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 202 { MV78XX0_TAG_DEVICE_CS2, 203 MV78XX0_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 204 { MV78XX0_TAG_DEVICE_CS3, 205 MV78XX0_ATTR_DEVICE_CS3, MVSOC_UNITID_DEVBUS }, 206 { MV78XX0_TAG_DEVICE_BOOTCS, 207 MV78XX0_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 208 { MV78XX0_TAG_SPI, 209 MV78XX0_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 210 { MV78XX0_TAG_PEX0_MEM, 211 MV78XX0_ATTR_PEX_0_MEM, MVSOC_UNITID_PEX }, 212 { MV78XX0_TAG_PEX01_MEM, 213 MV78XX0_ATTR_PEX_1_MEM, MVSOC_UNITID_PEX }, 214 { MV78XX0_TAG_PEX02_MEM, 215 MV78XX0_ATTR_PEX_2_MEM, MVSOC_UNITID_PEX }, 216 { MV78XX0_TAG_PEX03_MEM, 217 MV78XX0_ATTR_PEX_3_MEM, MVSOC_UNITID_PEX }, 218 { MV78XX0_TAG_PEX0_IO, 219 MV78XX0_ATTR_PEX_0_IO, MVSOC_UNITID_PEX }, 220 { MV78XX0_TAG_PEX01_IO, 221 MV78XX0_ATTR_PEX_1_IO, MVSOC_UNITID_PEX }, 222 { MV78XX0_TAG_PEX02_IO, 223 MV78XX0_ATTR_PEX_2_IO, MVSOC_UNITID_PEX }, 224 { MV78XX0_TAG_PEX03_IO, 225 MV78XX0_ATTR_PEX_3_IO, MVSOC_UNITID_PEX }, 226 { MV78XX0_TAG_PEX1_MEM, 227 MV78XX0_ATTR_PEX_0_MEM, MV78XX0_UNITID_PEX1 }, 228 { MV78XX0_TAG_PEX11_MEM, 229 MV78XX0_ATTR_PEX_1_MEM, MV78XX0_UNITID_PEX1 }, 230 { MV78XX0_TAG_PEX12_MEM, 231 MV78XX0_ATTR_PEX_2_MEM, MV78XX0_UNITID_PEX1 }, 232 { MV78XX0_TAG_PEX13_MEM, 233 MV78XX0_ATTR_PEX_3_MEM, MV78XX0_UNITID_PEX1 }, 234 { MV78XX0_TAG_PEX1_IO, 235 MV78XX0_ATTR_PEX_0_IO, MV78XX0_UNITID_PEX1 }, 236 { MV78XX0_TAG_PEX11_IO, 237 MV78XX0_ATTR_PEX_1_IO, MV78XX0_UNITID_PEX1 }, 238 { MV78XX0_TAG_PEX12_IO, 239 MV78XX0_ATTR_PEX_2_IO, MV78XX0_UNITID_PEX1 }, 240 { MV78XX0_TAG_PEX13_IO, 241 MV78XX0_ATTR_PEX_3_IO, MV78XX0_UNITID_PEX1 }, 242 { MV78XX0_TAG_CRYPT, 243 MV78XX0_ATTR_CRYPT, MV78XX0_UNITID_CRYPT }, 244 #endif 245 246 #if defined(ARMADAXP) 247 { ARMADAXP_TAG_PEX00_MEM, 248 ARMADAXP_ATTR_PEXx0_MEM, ARMADAXP_UNITID_PEX0 }, 249 { ARMADAXP_TAG_PEX00_IO, 250 ARMADAXP_ATTR_PEXx0_IO, ARMADAXP_UNITID_PEX0 }, 251 { ARMADAXP_TAG_PEX01_MEM, 252 ARMADAXP_ATTR_PEXx1_MEM, ARMADAXP_UNITID_PEX0 }, 253 { ARMADAXP_TAG_PEX01_IO, 254 ARMADAXP_ATTR_PEXx1_IO, ARMADAXP_UNITID_PEX0 }, 255 { ARMADAXP_TAG_PEX02_MEM, 256 ARMADAXP_ATTR_PEXx2_MEM, ARMADAXP_UNITID_PEX0 }, 257 { ARMADAXP_TAG_PEX02_IO, 258 ARMADAXP_ATTR_PEXx2_IO, ARMADAXP_UNITID_PEX0 }, 259 { ARMADAXP_TAG_PEX03_MEM, 260 ARMADAXP_ATTR_PEXx3_MEM, ARMADAXP_UNITID_PEX0 }, 261 { ARMADAXP_TAG_PEX03_IO, 262 ARMADAXP_ATTR_PEXx3_IO, ARMADAXP_UNITID_PEX0 }, 263 { ARMADAXP_TAG_PEX2_MEM, 264 ARMADAXP_ATTR_PEX2_MEM, ARMADAXP_UNITID_PEX2 }, 265 { ARMADAXP_TAG_PEX2_IO, 266 ARMADAXP_ATTR_PEX2_IO, ARMADAXP_UNITID_PEX2 }, 267 { ARMADAXP_TAG_PEX3_MEM, 268 ARMADAXP_ATTR_PEX3_MEM, ARMADAXP_UNITID_PEX3 }, 269 { ARMADAXP_TAG_PEX3_IO, 270 ARMADAXP_ATTR_PEX3_IO, ARMADAXP_UNITID_PEX3 }, 271 #endif 272 }; 273 274 #if defined(ARMADAXP) 275 #undef ARMADAXP 276 #define ARMADAXP(m) MARVELL_ARMADAXP_ ## m 277 #endif 278 #if defined(ORION) 279 #define ORION_1(m) MARVELL_ORION_1_ ## m 280 #define ORION_2(m) MARVELL_ORION_2_ ## m 281 #endif 282 #if defined(KIRKWOOD) 283 #undef KIRKWOOD 284 #define KIRKWOOD(m) MARVELL_KIRKWOOD_ ## m 285 #endif 286 #if defined(MV78XX0) 287 #undef MV78XX0 288 #define MV78XX0(m) MARVELL_MV78XX0_ ## m 289 #endif 290 static struct { 291 uint16_t model; 292 uint8_t rev; 293 const char *modelstr; 294 const char *revstr; 295 const char *typestr; 296 } nametbl[] = { 297 #if defined(ORION) 298 { ORION_1(88F1181), 0, "MV88F1181", NULL, "Orion1" }, 299 { ORION_1(88F5082), 2, "MV88F5082", "A2", "Orion1" }, 300 { ORION_1(88F5180N), 3, "MV88F5180N","B1", "Orion1" }, 301 { ORION_1(88F5181), 0, "MV88F5181", "A0", "Orion1" }, 302 { ORION_1(88F5181), 1, "MV88F5181", "A1", "Orion1" }, 303 { ORION_1(88F5181), 2, "MV88F5181", "B0", "Orion1" }, 304 { ORION_1(88F5181), 3, "MV88F5181", "B1", "Orion1" }, 305 { ORION_1(88F5181), 8, "MV88F5181L","A0", "Orion1" }, 306 { ORION_1(88F5181), 9, "MV88F5181L","A1", "Orion1" }, 307 { ORION_1(88F5182), 0, "MV88F5182", "A0", "Orion1" }, 308 { ORION_1(88F5182), 1, "MV88F5182", "A1", "Orion1" }, 309 { ORION_1(88F5182), 2, "MV88F5182", "A2", "Orion1" }, 310 { ORION_1(88F6082), 0, "MV88F6082", "A0", "Orion1" }, 311 { ORION_1(88F6082), 1, "MV88F6082", "A1", "Orion1" }, 312 { ORION_1(88F6183), 0, "MV88F6183", "A0", "Orion1" }, 313 { ORION_1(88F6183), 1, "MV88F6183", "Z0", "Orion1" }, 314 { ORION_1(88W8660), 0, "MV88W8660", "A0", "Orion1" }, 315 { ORION_1(88W8660), 1, "MV88W8660", "A1", "Orion1" }, 316 317 { ORION_2(88F1281), 0, "MV88F1281", "A0", "Orion2" }, 318 { ORION_2(88F5281), 0, "MV88F5281", "A0", "Orion2" }, 319 { ORION_2(88F5281), 1, "MV88F5281", "B0", "Orion2" }, 320 { ORION_2(88F5281), 2, "MV88F5281", "C0", "Orion2" }, 321 { ORION_2(88F5281), 3, "MV88F5281", "C1", "Orion2" }, 322 { ORION_2(88F5281), 4, "MV88F5281", "D0", "Orion2" }, 323 #endif 324 325 #if defined(KIRKWOOD) 326 { KIRKWOOD(88F6180), 2, "88F6180", "A0", "Kirkwood" }, 327 { KIRKWOOD(88F6180), 3, "88F6180", "A1", "Kirkwood" }, 328 { KIRKWOOD(88F6192), 0, "88F619x", "Z0", "Kirkwood" }, 329 { KIRKWOOD(88F6192), 2, "88F619x", "A0", "Kirkwood" }, 330 { KIRKWOOD(88F6192), 3, "88F619x", "A1", "Kirkwood" }, 331 { KIRKWOOD(88F6281), 0, "88F6281", "Z0", "Kirkwood" }, 332 { KIRKWOOD(88F6281), 2, "88F6281", "A0", "Kirkwood" }, 333 { KIRKWOOD(88F6281), 3, "88F6281", "A1", "Kirkwood" }, 334 { KIRKWOOD(88F6282), 0, "88F6282", "A0", "Kirkwood" }, 335 { KIRKWOOD(88F6282), 1, "88F6282", "A1", "Kirkwood" }, 336 #endif 337 338 #if defined(MV78XX0) 339 { MV78XX0(MV78100), 1, "MV78100", "A0", "Discovery Innovation" }, 340 { MV78XX0(MV78100), 2, "MV78100", "A1", "Discovery Innovation" }, 341 { MV78XX0(MV78200), 1, "MV78200", "A0", "Discovery Innovation" }, 342 #endif 343 344 #if defined(ARMADAXP) 345 { ARMADAXP(MV78130), 1, "MV78130", "A0", "Armada XP" }, 346 { ARMADAXP(MV78160), 1, "MV78160", "A0", "Armada XP" }, 347 { ARMADAXP(MV78230), 1, "MV78260", "A0", "Armada XP" }, 348 { ARMADAXP(MV78260), 1, "MV78260", "A0", "Armada XP" }, 349 { ARMADAXP(MV78460), 1, "MV78460", "A0", "Armada XP" }, 350 { ARMADAXP(MV78460), 2, "MV78460", "B0", "Armada XP" }, 351 #endif 352 }; 353 354 #define OFFSET_DEFAULT MVA_OFFSET_DEFAULT 355 #define IRQ_DEFAULT MVA_IRQ_DEFAULT 356 static const struct mvsoc_periph { 357 int model; 358 const char *name; 359 int unit; 360 bus_size_t offset; 361 int irq; 362 } mvsoc_periphs[] = { 363 #if defined(ORION) 364 #define ORION_IRQ_TMR (32 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 365 366 { ORION_1(88F1181), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 367 { ORION_1(88F1181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 368 { ORION_1(88F1181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 369 { ORION_1(88F1181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 370 { ORION_1(88F1181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 371 { ORION_1(88F1181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 372 { ORION_1(88F1181), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 373 374 { ORION_1(88F5082), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 375 { ORION_1(88F5082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 376 { ORION_1(88F5082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 377 { ORION_1(88F5082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 378 { ORION_1(88F5082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 379 { ORION_1(88F5082), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 380 { ORION_1(88F5082), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 381 { ORION_1(88F5082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 382 { ORION_1(88F5082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 383 { ORION_1(88F5082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 384 { ORION_1(88F5082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 385 { ORION_1(88F5082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 386 387 { ORION_1(88F5180N),"mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 388 { ORION_1(88F5180N),"mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 389 { ORION_1(88F5180N),"com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 390 { ORION_1(88F5180N),"com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 391 { ORION_1(88F5180N),"ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 392 { ORION_1(88F5180N),"gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 393 { ORION_1(88F5180N),"gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 394 { ORION_1(88F5180N),"gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 395 { ORION_1(88F5180N),"mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 396 { ORION_1(88F5180N),"mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 397 398 { ORION_1(88F5181), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 399 { ORION_1(88F5181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 400 { ORION_1(88F5181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 401 { ORION_1(88F5181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 402 { ORION_1(88F5181), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 403 { ORION_1(88F5181), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 404 { ORION_1(88F5181), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 405 { ORION_1(88F5181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 406 { ORION_1(88F5181), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 407 { ORION_1(88F5181), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 408 { ORION_1(88F5181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 409 410 { ORION_1(88F5182), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 411 { ORION_1(88F5182), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 412 { ORION_1(88F5182), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 413 { ORION_1(88F5182), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 414 { ORION_1(88F5182), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 415 { ORION_1(88F5182), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 416 { ORION_1(88F5182), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 417 { ORION_1(88F5182), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 418 { ORION_1(88F5182), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 419 { ORION_1(88F5182), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 420 { ORION_1(88F5182), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 421 { ORION_1(88F5182), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 422 423 { ORION_1(88F6082), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 424 { ORION_1(88F6082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 425 { ORION_1(88F6082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 426 { ORION_1(88F6082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 427 { ORION_1(88F6082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 428 { ORION_1(88F6082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 429 { ORION_1(88F6082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 430 { ORION_1(88F6082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 431 { ORION_1(88F6082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 432 { ORION_1(88F6082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 433 434 { ORION_1(88F6183), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 435 { ORION_1(88F6183), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 436 { ORION_1(88F6183), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 437 { ORION_1(88F6183), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 438 439 { ORION_1(88W8660), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 440 { ORION_1(88W8660), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 441 { ORION_1(88W8660), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 442 { ORION_1(88W8660), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 443 { ORION_1(88W8660), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 444 { ORION_1(88W8660), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 445 { ORION_1(88W8660), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 446 { ORION_1(88W8660), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 447 { ORION_1(88W8660), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 448 { ORION_1(88W8660), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 449 450 { ORION_2(88F1281), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 451 { ORION_2(88F1281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 452 { ORION_2(88F1281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 453 { ORION_2(88F1281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 454 { ORION_2(88F1281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 455 { ORION_2(88F1281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 456 { ORION_2(88F1281), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 457 458 { ORION_2(88F5281), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 459 { ORION_2(88F5281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 460 { ORION_2(88F5281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 461 { ORION_2(88F5281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 462 { ORION_2(88F5281), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 463 { ORION_2(88F5281), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 464 { ORION_2(88F5281), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 465 { ORION_2(88F5281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 466 { ORION_2(88F5281), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 467 { ORION_2(88F5281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 468 #endif 469 470 #if defined(KIRKWOOD) 471 #define KIRKWOOD_IRQ_TMR (64 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 472 473 { KIRKWOOD(88F6180),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 474 { KIRKWOOD(88F6180),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 475 { KIRKWOOD(88F6180),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 476 { KIRKWOOD(88F6180),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 477 { KIRKWOOD(88F6180),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 478 { KIRKWOOD(88F6180),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 479 { KIRKWOOD(88F6180),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 480 { KIRKWOOD(88F6180),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 481 { KIRKWOOD(88F6180),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 482 { KIRKWOOD(88F6180),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 483 { KIRKWOOD(88F6180),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 484 { KIRKWOOD(88F6180),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 485 486 { KIRKWOOD(88F6192),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 487 { KIRKWOOD(88F6192),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 488 { KIRKWOOD(88F6192),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 489 { KIRKWOOD(88F6192),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 490 { KIRKWOOD(88F6192),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 491 { KIRKWOOD(88F6192),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 492 { KIRKWOOD(88F6192),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 493 { KIRKWOOD(88F6192),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 494 { KIRKWOOD(88F6192),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 495 { KIRKWOOD(88F6192),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 496 { KIRKWOOD(88F6192),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 497 { KIRKWOOD(88F6192),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 498 { KIRKWOOD(88F6192),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 499 { KIRKWOOD(88F6192),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 500 501 { KIRKWOOD(88F6281),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 502 { KIRKWOOD(88F6281),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 503 { KIRKWOOD(88F6281),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 504 { KIRKWOOD(88F6281),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 505 { KIRKWOOD(88F6281),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 506 { KIRKWOOD(88F6281),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 507 { KIRKWOOD(88F6281),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 508 { KIRKWOOD(88F6281),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 509 { KIRKWOOD(88F6281),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT }, 510 { KIRKWOOD(88F6281),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 511 { KIRKWOOD(88F6281),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 512 { KIRKWOOD(88F6281),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 513 { KIRKWOOD(88F6281),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 514 { KIRKWOOD(88F6281),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 515 516 { KIRKWOOD(88F6282),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 517 { KIRKWOOD(88F6282),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 518 { KIRKWOOD(88F6282),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 519 { KIRKWOOD(88F6282),"mvsocts", 0, KIRKWOOD_TS_BASE, IRQ_DEFAULT }, 520 { KIRKWOOD(88F6282),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 521 { KIRKWOOD(88F6282),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 522 { KIRKWOOD(88F6282),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 523 { KIRKWOOD(88F6282),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 524 { KIRKWOOD(88F6282),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 525 { KIRKWOOD(88F6282),"gttwsi", 1, KIRKWOOD_TWSI1_BASE,KIRKWOOD_IRQ_TWSI1 }, 526 { KIRKWOOD(88F6282),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 527 { KIRKWOOD(88F6282),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 528 { KIRKWOOD(88F6282),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 529 { KIRKWOOD(88F6282),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 530 { KIRKWOOD(88F6282),"mvpex", 1, KIRKWOOD_PEX1_BASE,KIRKWOOD_IRQ_PEX1INT }, 531 { KIRKWOOD(88F6282),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 532 { KIRKWOOD(88F6282),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 533 #endif 534 535 #if defined(MV78XX0) 536 { MV78XX0(MV78100), "mvsoctmr",0, MVSOC_TMR_BASE, MV78XX0_IRQ_TIMER0 }, 537 { MV78XX0(MV78100), "mvsocgpp",0, MVSOC_GPP_BASE, MV78XX0_IRQ_GPIO0_7 }, 538 { MV78XX0(MV78100), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0 }, 539 { MV78XX0(MV78100), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1 }, 540 { MV78XX0(MV78100), "com", 2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 }, 541 { MV78XX0(MV78100), "com", 3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 }, 542 { MV78XX0(MV78100), "gttwsi", 0, MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI0 }, 543 { MV78XX0(MV78100), "gttwsi", 1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 }, 544 { MV78XX0(MV78100), "mvgbec", 0, MV78XX0_GBE0_BASE,IRQ_DEFAULT }, 545 { MV78XX0(MV78100), "mvgbec", 1, MV78XX0_GBE1_BASE,IRQ_DEFAULT }, 546 { MV78XX0(MV78100), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA }, 547 548 { MV78XX0(MV78200), "mvsoctmr",0, MVSOC_TMR_BASE, MV78XX0_IRQ_TIMER0 }, 549 { MV78XX0(MV78200), "mvsocgpp",0, MVSOC_GPP_BASE, MV78XX0_IRQ_GPIO0_7 }, 550 { MV78XX0(MV78200), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0 }, 551 { MV78XX0(MV78200), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1 }, 552 { MV78XX0(MV78200), "com", 2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 }, 553 { MV78XX0(MV78200), "com", 3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 }, 554 { MV78XX0(MV78200), "gttwsi", 0, MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI0 }, 555 { MV78XX0(MV78200), "gttwsi", 1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 }, 556 { MV78XX0(MV78200), "mvgbec", 0, MV78XX0_GBE0_BASE,IRQ_DEFAULT }, 557 { MV78XX0(MV78200), "mvgbec", 1, MV78XX0_GBE1_BASE,IRQ_DEFAULT }, 558 { MV78XX0(MV78200), "mvgbec", 2, MV78XX0_GBE2_BASE,IRQ_DEFAULT }, 559 { MV78XX0(MV78200), "mvgbec", 3, MV78XX0_GBE3_BASE,IRQ_DEFAULT }, 560 { MV78XX0(MV78200), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA }, 561 #endif 562 563 #if defined(ARMADAXP) 564 { ARMADAXP(MV78130), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 565 { ARMADAXP(MV78130), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 566 { ARMADAXP(MV78130), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 567 { ARMADAXP(MV78130), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 568 { ARMADAXP(MV78130), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 569 { ARMADAXP(MV78130), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 570 { ARMADAXP(MV78130), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 571 { ARMADAXP(MV78130), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 572 { ARMADAXP(MV78130), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 573 { ARMADAXP(MV78130), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 574 { ARMADAXP(MV78130), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 575 { ARMADAXP(MV78130), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 576 { ARMADAXP(MV78130), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 577 { ARMADAXP(MV78130), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 578 { ARMADAXP(MV78130), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 579 { ARMADAXP(MV78130), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 580 { ARMADAXP(MV78130), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 581 { ARMADAXP(MV78130), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 582 { ARMADAXP(MV78130), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 583 { ARMADAXP(MV78130), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 584 { ARMADAXP(MV78130), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 585 { ARMADAXP(MV78130), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 586 { ARMADAXP(MV78130), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 587 { ARMADAXP(MV78130), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 588 { ARMADAXP(MV78130), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 589 590 { ARMADAXP(MV78160), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 591 { ARMADAXP(MV78160), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 592 { ARMADAXP(MV78160), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 593 { ARMADAXP(MV78160), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 594 { ARMADAXP(MV78160), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 595 { ARMADAXP(MV78160), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 596 { ARMADAXP(MV78160), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 597 { ARMADAXP(MV78160), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 598 { ARMADAXP(MV78160), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 599 { ARMADAXP(MV78160), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 600 { ARMADAXP(MV78160), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 601 { ARMADAXP(MV78160), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 602 { ARMADAXP(MV78160), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 603 { ARMADAXP(MV78160), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 604 { ARMADAXP(MV78160), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 605 { ARMADAXP(MV78160), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 606 { ARMADAXP(MV78160), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 607 { ARMADAXP(MV78160), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 608 { ARMADAXP(MV78160), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 609 { ARMADAXP(MV78160), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 610 { ARMADAXP(MV78160), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 611 { ARMADAXP(MV78160), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 612 { ARMADAXP(MV78160), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 613 { ARMADAXP(MV78160), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 614 { ARMADAXP(MV78160), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 615 { ARMADAXP(MV78160), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 616 { ARMADAXP(MV78160), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 617 618 { ARMADAXP(MV78230), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 619 { ARMADAXP(MV78230), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 620 { ARMADAXP(MV78230), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 621 { ARMADAXP(MV78230), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 622 { ARMADAXP(MV78230), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 623 { ARMADAXP(MV78230), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 624 { ARMADAXP(MV78230), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 625 { ARMADAXP(MV78230), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 626 { ARMADAXP(MV78230), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 627 { ARMADAXP(MV78230), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 628 { ARMADAXP(MV78230), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 629 { ARMADAXP(MV78230), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 630 { ARMADAXP(MV78230), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 631 { ARMADAXP(MV78230), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 632 { ARMADAXP(MV78230), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 633 { ARMADAXP(MV78230), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 634 { ARMADAXP(MV78230), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 635 { ARMADAXP(MV78230), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 636 { ARMADAXP(MV78230), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 637 { ARMADAXP(MV78230), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 638 { ARMADAXP(MV78230), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 639 { ARMADAXP(MV78230), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 640 { ARMADAXP(MV78230), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 641 { ARMADAXP(MV78230), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 642 { ARMADAXP(MV78230), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 643 { ARMADAXP(MV78230), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 644 645 { ARMADAXP(MV78260), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 646 { ARMADAXP(MV78260), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 647 { ARMADAXP(MV78260), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 648 { ARMADAXP(MV78260), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 649 { ARMADAXP(MV78260), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 650 { ARMADAXP(MV78260), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 651 { ARMADAXP(MV78260), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 652 { ARMADAXP(MV78260), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 653 { ARMADAXP(MV78260), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 654 { ARMADAXP(MV78260), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 655 { ARMADAXP(MV78260), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 656 { ARMADAXP(MV78260), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 657 { ARMADAXP(MV78260), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 658 { ARMADAXP(MV78260), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 659 { ARMADAXP(MV78260), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 660 { ARMADAXP(MV78260), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 661 { ARMADAXP(MV78260), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 662 { ARMADAXP(MV78260), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 663 { ARMADAXP(MV78260), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 664 { ARMADAXP(MV78260), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 665 { ARMADAXP(MV78260), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 666 { ARMADAXP(MV78260), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 667 { ARMADAXP(MV78260), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 668 { ARMADAXP(MV78260), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 669 { ARMADAXP(MV78260), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 670 { ARMADAXP(MV78260), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 671 { ARMADAXP(MV78260), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 672 673 { ARMADAXP(MV78460), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 674 { ARMADAXP(MV78460), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 675 { ARMADAXP(MV78460), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 676 { ARMADAXP(MV78460), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 677 { ARMADAXP(MV78460), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 678 { ARMADAXP(MV78460), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 679 { ARMADAXP(MV78460), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 680 { ARMADAXP(MV78460), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 681 { ARMADAXP(MV78460), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 682 { ARMADAXP(MV78460), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 683 { ARMADAXP(MV78460), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 684 { ARMADAXP(MV78460), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 685 { ARMADAXP(MV78460), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 686 { ARMADAXP(MV78460), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 687 { ARMADAXP(MV78460), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 688 { ARMADAXP(MV78460), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 689 { ARMADAXP(MV78460), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 690 { ARMADAXP(MV78460), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 691 { ARMADAXP(MV78460), "mvpex", 5, ARMADAXP_PEX3_BASE,ARMADAXP_IRQ_PEX3 }, 692 { ARMADAXP(MV78460), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 693 { ARMADAXP(MV78460), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 694 { ARMADAXP(MV78460), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 695 { ARMADAXP(MV78460), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 696 { ARMADAXP(MV78460), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 697 { ARMADAXP(MV78460), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 698 { ARMADAXP(MV78460), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 699 { ARMADAXP(MV78460), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 700 { ARMADAXP(MV78460), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 701 #endif 702 }; 703 704 705 CFATTACH_DECL_NEW(mvsoc, sizeof(struct mvsoc_softc), 706 mvsoc_match, mvsoc_attach, NULL, NULL); 707 708 /* ARGSUSED */ 709 static int 710 mvsoc_match(device_t parent, struct cfdata *match, void *aux) 711 { 712 713 return 1; 714 } 715 716 /* ARGSUSED */ 717 static void 718 mvsoc_attach(device_t parent, device_t self, void *aux) 719 { 720 struct mvsoc_softc *sc = device_private(self); 721 struct marvell_attach_args mva; 722 uint16_t model; 723 uint8_t rev; 724 int i; 725 726 sc->sc_dev = self; 727 sc->sc_iot = &mvsoc_bs_tag; 728 sc->sc_addr = vtophys(regbase); 729 sc->sc_dmat = &mvsoc_bus_dma_tag; 730 if (bus_space_map(sc->sc_iot, sc->sc_addr, 0x100000, 0, &sc->sc_ioh) != 731 0) { 732 aprint_error_dev(self, "can't map registers\n"); 733 return; 734 } 735 736 model = mvsoc_model(); 737 rev = mvsoc_rev(); 738 for (i = 0; i < __arraycount(nametbl); i++) 739 if (nametbl[i].model == model && nametbl[i].rev == rev) 740 break; 741 if (i >= __arraycount(nametbl)) 742 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 743 744 aprint_normal(": Marvell %s %s%s %s\n", 745 nametbl[i].modelstr, 746 nametbl[i].revstr != NULL ? "Rev. " : "", 747 nametbl[i].revstr != NULL ? nametbl[i].revstr : "", 748 nametbl[i].typestr); 749 aprint_normal("%s: CPU Clock %d.%03d MHz" 750 " SysClock %d.%03d MHz TClock %d.%03d MHz\n", 751 device_xname(self), 752 mvPclk / 1000000, (mvPclk / 1000) % 1000, 753 mvSysclk / 1000000, (mvSysclk / 1000) % 1000, 754 mvTclk / 1000000, (mvTclk / 1000) % 1000); 755 aprint_naive("\n"); 756 757 mvsoc_intr_init(); 758 759 for (i = 0; i < __arraycount(mvsoc_periphs); i++) { 760 if (mvsoc_periphs[i].model != model) 761 continue; 762 763 mva.mva_name = mvsoc_periphs[i].name; 764 mva.mva_model = model; 765 mva.mva_revision = rev; 766 mva.mva_iot = sc->sc_iot; 767 mva.mva_ioh = sc->sc_ioh; 768 mva.mva_unit = mvsoc_periphs[i].unit; 769 mva.mva_addr = sc->sc_addr; 770 mva.mva_offset = mvsoc_periphs[i].offset; 771 mva.mva_size = 0; 772 mva.mva_dmat = sc->sc_dmat; 773 mva.mva_irq = mvsoc_periphs[i].irq; 774 775 /* Skip clock disabled devices */ 776 if (mvsoc_clkgating != NULL && mvsoc_clkgating(&mva)) { 777 aprint_normal_dev(self, "%s%d clock disabled\n", 778 mvsoc_periphs[i].name, mvsoc_periphs[i].unit); 779 continue; 780 } 781 782 config_found_sm_loc(sc->sc_dev, "mvsoc", NULL, &mva, 783 mvsoc_print, mvsoc_search); 784 } 785 } 786 787 static int 788 mvsoc_print(void *aux, const char *pnp) 789 { 790 struct marvell_attach_args *mva = aux; 791 792 if (pnp) 793 aprint_normal("%s at %s unit %d", 794 mva->mva_name, pnp, mva->mva_unit); 795 else { 796 if (mva->mva_unit != MVA_UNIT_DEFAULT) 797 aprint_normal(" unit %d", mva->mva_unit); 798 if (mva->mva_offset != MVA_OFFSET_DEFAULT) { 799 aprint_normal(" offset 0x%04lx", mva->mva_offset); 800 if (mva->mva_size > 0) 801 aprint_normal("-0x%04lx", 802 mva->mva_offset + mva->mva_size - 1); 803 } 804 if (mva->mva_irq != MVA_IRQ_DEFAULT) 805 aprint_normal(" irq %d", mva->mva_irq); 806 } 807 808 return UNCONF; 809 } 810 811 /* ARGSUSED */ 812 static int 813 mvsoc_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 814 { 815 816 return config_match(parent, cf, aux); 817 } 818 819 /* ARGSUSED */ 820 int 821 marvell_winparams_by_tag(device_t dev, int tag, int *target, int *attribute, 822 uint64_t *base, uint32_t *size) 823 { 824 uint32_t base32; 825 int rv; 826 827 rv = mvsoc_target(tag, target, attribute, &base32, size); 828 *base = base32; 829 if (rv == -1) 830 return -1; 831 return 0; 832 } 833 834 835 /* 836 * These functions is called before bus_space is initialized. 837 */ 838 839 void 840 mvsoc_bootstrap(bus_addr_t iobase) 841 { 842 843 regbase = iobase; 844 dsc_base = iobase + MVSOC_DSC_BASE; 845 mlmb_base = iobase + MVSOC_MLMB_BASE; 846 pex_base = iobase + MVSOC_PEX_BASE; 847 #ifdef MVSOC_CONSOLE_EARLY 848 com_base = iobase + MVSOC_COM0_BASE; 849 cn_tab = &mvsoc_earlycons; 850 printf("Hello\n"); 851 #endif 852 } 853 854 /* 855 * We can read register of PCI configurations from (MVSOC_PEX_BASE + 0). 856 */ 857 uint16_t 858 mvsoc_model(void) 859 { 860 /* 861 * We read product-id from vendor/device register of PCI-Express. 862 */ 863 uint32_t reg; 864 uint16_t model; 865 866 KASSERT(regbase != 0xffffffff); 867 868 reg = *(volatile uint32_t *)(pex_base + PCI_ID_REG); 869 model = PCI_PRODUCT(reg); 870 871 #if defined(ORION) 872 if (model == PCI_PRODUCT_MARVELL_88F5182) { 873 reg = *(volatile uint32_t *)(regbase + ORION_PMI_BASE + 874 ORION_PMI_SAMPLE_AT_RESET); 875 if ((reg & ORION_PMISMPL_TCLK_MASK) == 0) 876 model = PCI_PRODUCT_MARVELL_88F5082; 877 } 878 #endif 879 #if defined(KIRKWOOD) 880 if (model == PCI_PRODUCT_MARVELL_88F6281) { 881 reg = *(volatile uint32_t *)(regbase + KIRKWOOD_MISC_BASE + 882 KIRKWOOD_MISC_DEVICEID); 883 if (reg == 1) /* 88F6192 is 1 */ 884 model = MARVELL_KIRKWOOD_88F6192; 885 } 886 #endif 887 888 return model; 889 } 890 891 uint8_t 892 mvsoc_rev(void) 893 { 894 uint32_t reg; 895 uint8_t rev; 896 897 KASSERT(regbase != 0xffffffff); 898 899 reg = *(volatile uint32_t *)(pex_base + PCI_CLASS_REG); 900 rev = PCI_REVISION(reg); 901 902 return rev; 903 } 904 905 906 int 907 mvsoc_target(int tag, uint32_t *target, uint32_t *attr, uint32_t *base, 908 uint32_t *size) 909 { 910 int i; 911 912 KASSERT(regbase != 0xffffffff); 913 914 if (tag == MVSOC_TAG_INTERNALREG) { 915 if (target != NULL) 916 *target = 0; 917 if (attr != NULL) 918 *attr = 0; 919 if (base != NULL) 920 *base = read_mlmbreg(MVSOC_MLMB_IRBAR) & 921 MVSOC_MLMB_IRBAR_BASE_MASK; 922 if (size != NULL) 923 *size = 0; 924 925 return 0; 926 } 927 928 /* sanity check */ 929 for (i = 0; i < __arraycount(mvsoc_tags); i++) 930 if (mvsoc_tags[i].tag == tag) 931 break; 932 if (i >= __arraycount(mvsoc_tags)) 933 return -1; 934 935 if (target != NULL) 936 *target = mvsoc_tags[i].target; 937 if (attr != NULL) 938 *attr = mvsoc_tags[i].attr; 939 940 if (mvsoc_tags[i].target == MVSOC_UNITID_DDR) { 941 if (tag == MARVELL_TAG_SDRAM_CS0 || 942 tag == MARVELL_TAG_SDRAM_CS1 || 943 tag == MARVELL_TAG_SDRAM_CS2 || 944 tag == MARVELL_TAG_SDRAM_CS3) 945 return mvsoc_target_ddr(mvsoc_tags[i].attr, base, size); 946 else 947 return mvsoc_target_ddr3(mvsoc_tags[i].attr, base, 948 size); 949 } else 950 return mvsoc_target_peripheral(mvsoc_tags[i].target, 951 mvsoc_tags[i].attr, base, size); 952 } 953 954 static int 955 mvsoc_target_ddr(uint32_t attr, uint32_t *base, uint32_t *size) 956 { 957 uint32_t baseaddrreg, sizereg; 958 int cs; 959 960 /* 961 * Read DDR SDRAM Controller Address Decode Registers 962 */ 963 964 switch (attr) { 965 case MARVELL_ATTR_SDRAM_CS0: 966 cs = 0; 967 break; 968 case MARVELL_ATTR_SDRAM_CS1: 969 cs = 1; 970 break; 971 case MARVELL_ATTR_SDRAM_CS2: 972 cs = 2; 973 break; 974 case MARVELL_ATTR_SDRAM_CS3: 975 cs = 3; 976 break; 977 default: 978 aprint_error("unknwon ATTR: 0x%x", attr); 979 return -1; 980 } 981 sizereg = *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSSR(cs)); 982 if (sizereg & MVSOC_DSC_CSSR_WINEN) { 983 baseaddrreg = 984 *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSBAR(cs)); 985 986 if (base != NULL) 987 *base = baseaddrreg & MVSOC_DSC_CSBAR_BASE_MASK; 988 if (size != NULL) 989 *size = (sizereg & MVSOC_DSC_CSSR_SIZE_MASK) + 990 (~MVSOC_DSC_CSSR_SIZE_MASK + 1); 991 } else { 992 if (base != NULL) 993 *base = 0; 994 if (size != NULL) 995 *size = 0; 996 } 997 return 0; 998 } 999 1000 static int 1001 mvsoc_target_ddr3(uint32_t attr, uint32_t *base, uint32_t *size) 1002 { 1003 uint32_t baseaddrreg, sizereg; 1004 int cs, i; 1005 1006 /* 1007 * Read DDR3 SDRAM Address Decoding Registers 1008 */ 1009 1010 switch (attr) { 1011 case MARVELL_ATTR_SDRAM_CS0: 1012 cs = 0; 1013 break; 1014 case MARVELL_ATTR_SDRAM_CS1: 1015 cs = 1; 1016 break; 1017 case MARVELL_ATTR_SDRAM_CS2: 1018 cs = 2; 1019 break; 1020 case MARVELL_ATTR_SDRAM_CS3: 1021 cs = 3; 1022 break; 1023 default: 1024 aprint_error("unknwon ATTR: 0x%x", attr); 1025 return -1; 1026 } 1027 for (i = 0; i < MVSOC_MLMB_NWIN; i++) { 1028 sizereg = read_mlmbreg(MVSOC_MLMB_WINCR(i)); 1029 if ((sizereg & MVSOC_MLMB_WINCR_EN) && 1030 MVSOC_MLMB_WINCR_WINCS(sizereg) == cs) 1031 break; 1032 } 1033 if (i == MVSOC_MLMB_NWIN) { 1034 if (base != NULL) 1035 *base = 0; 1036 if (size != NULL) 1037 *size = 0; 1038 return 0; 1039 } 1040 1041 baseaddrreg = read_mlmbreg(MVSOC_MLMB_WINBAR(i)); 1042 if (base != NULL) 1043 *base = baseaddrreg & MVSOC_MLMB_WINBAR_BASE_MASK; 1044 if (size != NULL) 1045 *size = (sizereg & MVSOC_MLMB_WINCR_SIZE_MASK) + 1046 (~MVSOC_MLMB_WINCR_SIZE_MASK + 1); 1047 return 0; 1048 } 1049 1050 static int 1051 mvsoc_target_peripheral(uint32_t target, uint32_t attr, uint32_t *base, 1052 uint32_t *size) 1053 { 1054 uint32_t basereg, ctrlreg, ta, tamask; 1055 int i; 1056 1057 /* 1058 * Read CPU Address Map Registers 1059 */ 1060 1061 ta = MVSOC_MLMB_WCR_TARGET(target) | MVSOC_MLMB_WCR_ATTR(attr); 1062 tamask = MVSOC_MLMB_WCR_TARGET(MVSOC_UNITID_MASK) | 1063 MVSOC_MLMB_WCR_ATTR(MARVELL_ATTR_MASK); 1064 1065 if (base != NULL) 1066 *base = 0; 1067 if (size != NULL) 1068 *size = 0; 1069 1070 for (i = 0; i < nwindow; i++) { 1071 ctrlreg = read_mlmbreg(MVSOC_MLMB_WCR(i)); 1072 if ((ctrlreg & tamask) != ta) 1073 continue; 1074 if (ctrlreg & MVSOC_MLMB_WCR_WINEN) { 1075 basereg = read_mlmbreg(MVSOC_MLMB_WBR(i)); 1076 1077 if (base != NULL) 1078 *base = basereg & MVSOC_MLMB_WBR_BASE_MASK; 1079 if (size != NULL) 1080 *size = (ctrlreg & 1081 MVSOC_MLMB_WCR_SIZE_MASK) + 1082 (~MVSOC_MLMB_WCR_SIZE_MASK + 1); 1083 } 1084 break; 1085 } 1086 return i; 1087 } 1088
Indexes created Thu Oct 23 22:10:10 GMT 2025