mvsoc.c revision 1.18.6.2
1 /* $NetBSD: mvsoc.c,v 1.18.6.2 2015/12/27 12:09:31 skrll Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2013, 2014 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.18.6.2 2015/12/27 12:09:31 skrll Exp $"); 30 31 #include "opt_cputypes.h" 32 #include "opt_mvsoc.h" 33 #ifdef ARMADAXP 34 #include "mvxpe.h" 35 #include "mvxpsec.h" 36 #endif 37 38 #include <sys/param.h> 39 #include <sys/boot_flag.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/device.h> 43 #include <sys/errno.h> 44 45 #include <dev/pci/pcidevs.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/marvell/marvellreg.h> 48 #include <dev/marvell/marvellvar.h> 49 50 #include <arm/marvell/mvsocreg.h> 51 #include <arm/marvell/mvsocvar.h> 52 #include <arm/marvell/orionreg.h> 53 #include <arm/marvell/kirkwoodreg.h> 54 #include <arm/marvell/mv78xx0reg.h> 55 #include <arm/marvell/armadaxpvar.h> 56 #include <arm/marvell/armadaxpreg.h> 57 58 #include <uvm/uvm.h> 59 60 #include "locators.h" 61 62 #ifdef MVSOC_CONSOLE_EARLY 63 #include <dev/ic/ns16550reg.h> 64 #include <dev/ic/comreg.h> 65 #include <dev/cons.h> 66 #endif 67 68 static int mvsoc_match(device_t, struct cfdata *, void *); 69 static void mvsoc_attach(device_t, device_t, void *); 70 71 static int mvsoc_print(void *, const char *); 72 static int mvsoc_search(device_t, cfdata_t, const int *, void *); 73 74 static int mvsoc_target_ddr(uint32_t, uint32_t *, uint32_t *); 75 static int mvsoc_target_ddr3(uint32_t, uint32_t *, uint32_t *); 76 static int mvsoc_target_peripheral(uint32_t, uint32_t, uint32_t *, uint32_t *); 77 78 uint32_t mvPclk, mvSysclk, mvTclk = 0; 79 int nwindow = 0, nremap = 0; 80 static vaddr_t regbase = 0xffffffff, dsc_base, pex_base; 81 vaddr_t mlmb_base; 82 83 void (*mvsoc_intr_init)(void); 84 int (*mvsoc_clkgating)(struct marvell_attach_args *); 85 86 87 #ifdef MVSOC_CONSOLE_EARLY 88 static vaddr_t com_base; 89 90 static inline uint32_t 91 uart_read(bus_size_t o) 92 { 93 return *(volatile uint32_t *)(com_base + (o << 2)); 94 } 95 96 static inline void 97 uart_write(bus_size_t o, uint32_t v) 98 { 99 *(volatile uint32_t *)(com_base + (o << 2)) = v; 100 } 101 102 static int 103 mvsoc_cngetc(dev_t dv) 104 { 105 if ((uart_read(com_lsr) & LSR_RXRDY) == 0) 106 return -1; 107 108 return uart_read(com_data) & 0xff; 109 } 110 111 static void 112 mvsoc_cnputc(dev_t dv, int c) 113 { 114 int timo = 150000; 115 116 while ((uart_read(com_lsr) & LSR_TXRDY) == 0 && --timo > 0) 117 ; 118 119 uart_write(com_data, c); 120 121 timo = 150000; 122 while ((uart_read(com_lsr) & LSR_TSRE) == 0 && --timo > 0) 123 ; 124 } 125 126 static struct consdev mvsoc_earlycons = { 127 .cn_putc = mvsoc_cnputc, 128 .cn_getc = mvsoc_cngetc, 129 .cn_pollc = nullcnpollc, 130 }; 131 #endif 132 133 134 /* attributes */ 135 static struct { 136 int tag; 137 uint32_t attr; 138 uint32_t target; 139 } mvsoc_tags[] = { 140 { MARVELL_TAG_SDRAM_CS0, 141 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 142 { MARVELL_TAG_SDRAM_CS1, 143 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 144 { MARVELL_TAG_SDRAM_CS2, 145 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 146 { MARVELL_TAG_SDRAM_CS3, 147 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 148 149 { MARVELL_TAG_DDR3_CS0, 150 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 151 { MARVELL_TAG_DDR3_CS1, 152 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 153 { MARVELL_TAG_DDR3_CS2, 154 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 155 { MARVELL_TAG_DDR3_CS3, 156 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 157 158 #if defined(ORION) 159 { ORION_TAG_DEVICE_CS0, 160 ORION_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 161 { ORION_TAG_DEVICE_CS1, 162 ORION_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 163 { ORION_TAG_DEVICE_CS2, 164 ORION_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 165 { ORION_TAG_DEVICE_BOOTCS, 166 ORION_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 167 { ORION_TAG_FLASH_CS, 168 ORION_ATTR_FLASH_CS, MVSOC_UNITID_DEVBUS }, 169 { ORION_TAG_PEX0_MEM, 170 ORION_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 171 { ORION_TAG_PEX0_IO, 172 ORION_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 173 { ORION_TAG_PEX1_MEM, 174 ORION_ATTR_PEX_MEM, ORION_UNITID_PEX1 }, 175 { ORION_TAG_PEX1_IO, 176 ORION_ATTR_PEX_IO, ORION_UNITID_PEX1 }, 177 { ORION_TAG_PCI_MEM, 178 ORION_ATTR_PCI_MEM, ORION_UNITID_PCI }, 179 { ORION_TAG_PCI_IO, 180 ORION_ATTR_PCI_IO, ORION_UNITID_PCI }, 181 { ORION_TAG_CRYPT, 182 ORION_ATTR_CRYPT, ORION_UNITID_CRYPT }, 183 #endif 184 185 #if defined(KIRKWOOD) 186 { KIRKWOOD_TAG_NAND, 187 KIRKWOOD_ATTR_NAND, MVSOC_UNITID_DEVBUS }, 188 { KIRKWOOD_TAG_SPI, 189 KIRKWOOD_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 190 { KIRKWOOD_TAG_BOOTROM, 191 KIRKWOOD_ATTR_BOOTROM, MVSOC_UNITID_DEVBUS }, 192 { KIRKWOOD_TAG_PEX_MEM, 193 KIRKWOOD_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 194 { KIRKWOOD_TAG_PEX_IO, 195 KIRKWOOD_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 196 { KIRKWOOD_TAG_PEX1_MEM, 197 KIRKWOOD_ATTR_PEX1_MEM, MVSOC_UNITID_PEX }, 198 { KIRKWOOD_TAG_PEX1_IO, 199 KIRKWOOD_ATTR_PEX1_IO, MVSOC_UNITID_PEX }, 200 { KIRKWOOD_TAG_CRYPT, 201 KIRKWOOD_ATTR_CRYPT, KIRKWOOD_UNITID_CRYPT }, 202 #endif 203 204 #if defined(MV78XX0) 205 { MV78XX0_TAG_DEVICE_CS0, 206 MV78XX0_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 207 { MV78XX0_TAG_DEVICE_CS1, 208 MV78XX0_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 209 { MV78XX0_TAG_DEVICE_CS2, 210 MV78XX0_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 211 { MV78XX0_TAG_DEVICE_CS3, 212 MV78XX0_ATTR_DEVICE_CS3, MVSOC_UNITID_DEVBUS }, 213 { MV78XX0_TAG_DEVICE_BOOTCS, 214 MV78XX0_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 215 { MV78XX0_TAG_SPI, 216 MV78XX0_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 217 { MV78XX0_TAG_PEX0_MEM, 218 MV78XX0_ATTR_PEX_0_MEM, MVSOC_UNITID_PEX }, 219 { MV78XX0_TAG_PEX01_MEM, 220 MV78XX0_ATTR_PEX_1_MEM, MVSOC_UNITID_PEX }, 221 { MV78XX0_TAG_PEX02_MEM, 222 MV78XX0_ATTR_PEX_2_MEM, MVSOC_UNITID_PEX }, 223 { MV78XX0_TAG_PEX03_MEM, 224 MV78XX0_ATTR_PEX_3_MEM, MVSOC_UNITID_PEX }, 225 { MV78XX0_TAG_PEX0_IO, 226 MV78XX0_ATTR_PEX_0_IO, MVSOC_UNITID_PEX }, 227 { MV78XX0_TAG_PEX01_IO, 228 MV78XX0_ATTR_PEX_1_IO, MVSOC_UNITID_PEX }, 229 { MV78XX0_TAG_PEX02_IO, 230 MV78XX0_ATTR_PEX_2_IO, MVSOC_UNITID_PEX }, 231 { MV78XX0_TAG_PEX03_IO, 232 MV78XX0_ATTR_PEX_3_IO, MVSOC_UNITID_PEX }, 233 { MV78XX0_TAG_PEX1_MEM, 234 MV78XX0_ATTR_PEX_0_MEM, MV78XX0_UNITID_PEX1 }, 235 { MV78XX0_TAG_PEX11_MEM, 236 MV78XX0_ATTR_PEX_1_MEM, MV78XX0_UNITID_PEX1 }, 237 { MV78XX0_TAG_PEX12_MEM, 238 MV78XX0_ATTR_PEX_2_MEM, MV78XX0_UNITID_PEX1 }, 239 { MV78XX0_TAG_PEX13_MEM, 240 MV78XX0_ATTR_PEX_3_MEM, MV78XX0_UNITID_PEX1 }, 241 { MV78XX0_TAG_PEX1_IO, 242 MV78XX0_ATTR_PEX_0_IO, MV78XX0_UNITID_PEX1 }, 243 { MV78XX0_TAG_PEX11_IO, 244 MV78XX0_ATTR_PEX_1_IO, MV78XX0_UNITID_PEX1 }, 245 { MV78XX0_TAG_PEX12_IO, 246 MV78XX0_ATTR_PEX_2_IO, MV78XX0_UNITID_PEX1 }, 247 { MV78XX0_TAG_PEX13_IO, 248 MV78XX0_ATTR_PEX_3_IO, MV78XX0_UNITID_PEX1 }, 249 { MV78XX0_TAG_CRYPT, 250 MV78XX0_ATTR_CRYPT, MV78XX0_UNITID_CRYPT }, 251 #endif 252 253 #if defined(ARMADAXP) 254 { ARMADAXP_TAG_PEX00_MEM, 255 ARMADAXP_ATTR_PEXx0_MEM, ARMADAXP_UNITID_PEX0 }, 256 { ARMADAXP_TAG_PEX00_IO, 257 ARMADAXP_ATTR_PEXx0_IO, ARMADAXP_UNITID_PEX0 }, 258 { ARMADAXP_TAG_PEX01_MEM, 259 ARMADAXP_ATTR_PEXx1_MEM, ARMADAXP_UNITID_PEX0 }, 260 { ARMADAXP_TAG_PEX01_IO, 261 ARMADAXP_ATTR_PEXx1_IO, ARMADAXP_UNITID_PEX0 }, 262 { ARMADAXP_TAG_PEX02_MEM, 263 ARMADAXP_ATTR_PEXx2_MEM, ARMADAXP_UNITID_PEX0 }, 264 { ARMADAXP_TAG_PEX02_IO, 265 ARMADAXP_ATTR_PEXx2_IO, ARMADAXP_UNITID_PEX0 }, 266 { ARMADAXP_TAG_PEX03_MEM, 267 ARMADAXP_ATTR_PEXx3_MEM, ARMADAXP_UNITID_PEX0 }, 268 { ARMADAXP_TAG_PEX03_IO, 269 ARMADAXP_ATTR_PEXx3_IO, ARMADAXP_UNITID_PEX0 }, 270 { ARMADAXP_TAG_PEX2_MEM, 271 ARMADAXP_ATTR_PEX2_MEM, ARMADAXP_UNITID_PEX2 }, 272 { ARMADAXP_TAG_PEX2_IO, 273 ARMADAXP_ATTR_PEX2_IO, ARMADAXP_UNITID_PEX2 }, 274 { ARMADAXP_TAG_PEX3_MEM, 275 ARMADAXP_ATTR_PEX3_MEM, ARMADAXP_UNITID_PEX3 }, 276 { ARMADAXP_TAG_PEX3_IO, 277 ARMADAXP_ATTR_PEX3_IO, ARMADAXP_UNITID_PEX3 }, 278 { ARMADAXP_TAG_CRYPT0, 279 ARMADAXP_ATTR_CRYPT0_NOSWAP, ARMADAXP_UNITID_CRYPT }, 280 { ARMADAXP_TAG_CRYPT1, 281 ARMADAXP_ATTR_CRYPT1_NOSWAP, ARMADAXP_UNITID_CRYPT }, 282 #endif 283 }; 284 285 #if defined(ORION) 286 #define ORION_1(m) MARVELL_ORION_1_ ## m 287 #define ORION_2(m) MARVELL_ORION_2_ ## m 288 #endif 289 #if defined(KIRKWOOD) 290 #undef KIRKWOOD 291 #define KIRKWOOD(m) MARVELL_KIRKWOOD_ ## m 292 #endif 293 #if defined(MV78XX0) 294 #undef MV78XX0 295 #define MV78XX0(m) MARVELL_MV78XX0_ ## m 296 #endif 297 #if defined(ARMADAXP) 298 #undef ARMADAXP 299 #define ARMADAXP(m) MARVELL_ARMADAXP_ ## m 300 #define ARMADA370(m) MARVELL_ARMADA370_ ## m 301 #endif 302 static struct { 303 uint16_t model; 304 uint8_t rev; 305 const char *modelstr; 306 const char *revstr; 307 const char *typestr; 308 } nametbl[] = { 309 #if defined(ORION) 310 { ORION_1(88F1181), 0, "MV88F1181", NULL, "Orion1" }, 311 { ORION_1(88F5082), 2, "MV88F5082", "A2", "Orion1" }, 312 { ORION_1(88F5180N), 3, "MV88F5180N","B1", "Orion1" }, 313 { ORION_1(88F5181), 0, "MV88F5181", "A0", "Orion1" }, 314 { ORION_1(88F5181), 1, "MV88F5181", "A1", "Orion1" }, 315 { ORION_1(88F5181), 2, "MV88F5181", "B0", "Orion1" }, 316 { ORION_1(88F5181), 3, "MV88F5181", "B1", "Orion1" }, 317 { ORION_1(88F5181), 8, "MV88F5181L","A0", "Orion1" }, 318 { ORION_1(88F5181), 9, "MV88F5181L","A1", "Orion1" }, 319 { ORION_1(88F5182), 0, "MV88F5182", "A0", "Orion1" }, 320 { ORION_1(88F5182), 1, "MV88F5182", "A1", "Orion1" }, 321 { ORION_1(88F5182), 2, "MV88F5182", "A2", "Orion1" }, 322 { ORION_1(88F6082), 0, "MV88F6082", "A0", "Orion1" }, 323 { ORION_1(88F6082), 1, "MV88F6082", "A1", "Orion1" }, 324 { ORION_1(88F6183), 0, "MV88F6183", "A0", "Orion1" }, 325 { ORION_1(88F6183), 1, "MV88F6183", "Z0", "Orion1" }, 326 { ORION_1(88W8660), 0, "MV88W8660", "A0", "Orion1" }, 327 { ORION_1(88W8660), 1, "MV88W8660", "A1", "Orion1" }, 328 329 { ORION_2(88F1281), 0, "MV88F1281", "A0", "Orion2" }, 330 { ORION_2(88F5281), 0, "MV88F5281", "A0", "Orion2" }, 331 { ORION_2(88F5281), 1, "MV88F5281", "B0", "Orion2" }, 332 { ORION_2(88F5281), 2, "MV88F5281", "C0", "Orion2" }, 333 { ORION_2(88F5281), 3, "MV88F5281", "C1", "Orion2" }, 334 { ORION_2(88F5281), 4, "MV88F5281", "D0", "Orion2" }, 335 #endif 336 337 #if defined(KIRKWOOD) 338 { KIRKWOOD(88F6180), 2, "88F6180", "A0", "Kirkwood" }, 339 { KIRKWOOD(88F6180), 3, "88F6180", "A1", "Kirkwood" }, 340 { KIRKWOOD(88F6192), 0, "88F619x", "Z0", "Kirkwood" }, 341 { KIRKWOOD(88F6192), 2, "88F619x", "A0", "Kirkwood" }, 342 { KIRKWOOD(88F6192), 3, "88F619x", "A1", "Kirkwood" }, 343 { KIRKWOOD(88F6281), 0, "88F6281", "Z0", "Kirkwood" }, 344 { KIRKWOOD(88F6281), 2, "88F6281", "A0", "Kirkwood" }, 345 { KIRKWOOD(88F6281), 3, "88F6281", "A1", "Kirkwood" }, 346 { KIRKWOOD(88F6282), 0, "88F6282", "A0", "Kirkwood" }, 347 { KIRKWOOD(88F6282), 1, "88F6282", "A1", "Kirkwood" }, 348 #endif 349 350 #if defined(MV78XX0) 351 { MV78XX0(MV78100), 1, "MV78100", "A0", "Discovery Innovation" }, 352 { MV78XX0(MV78100), 2, "MV78100", "A1", "Discovery Innovation" }, 353 { MV78XX0(MV78200), 1, "MV78200", "A0", "Discovery Innovation" }, 354 #endif 355 356 #if defined(ARMADAXP) 357 { ARMADAXP(MV78130), 1, "MV78130", "A0", "Armada XP" }, 358 { ARMADAXP(MV78160), 1, "MV78160", "A0", "Armada XP" }, 359 { ARMADAXP(MV78230), 1, "MV78260", "A0", "Armada XP" }, 360 { ARMADAXP(MV78260), 1, "MV78260", "A0", "Armada XP" }, 361 { ARMADAXP(MV78260), 2, "MV78260", "B0", "Armada XP" }, 362 { ARMADAXP(MV78460), 1, "MV78460", "A0", "Armada XP" }, 363 { ARMADAXP(MV78460), 2, "MV78460", "B0", "Armada XP" }, 364 365 { ARMADA370(MV6707), 0, "MV6707", "A0", "Armada 370" }, 366 { ARMADA370(MV6707), 1, "MV6707", "A1", "Armada 370" }, 367 { ARMADA370(MV6710), 0, "MV6710", "A0", "Armada 370" }, 368 { ARMADA370(MV6710), 1, "MV6710", "A1", "Armada 370" }, 369 { ARMADA370(MV6W11), 0, "MV6W11", "A0", "Armada 370" }, 370 { ARMADA370(MV6W11), 1, "MV6W11", "A1", "Armada 370" }, 371 #endif 372 }; 373 374 enum marvell_tags ddr_tags[] = { 375 MARVELL_TAG_SDRAM_CS0, 376 MARVELL_TAG_SDRAM_CS1, 377 MARVELL_TAG_SDRAM_CS2, 378 MARVELL_TAG_SDRAM_CS3, 379 380 MARVELL_TAG_UNDEFINED 381 }; 382 enum marvell_tags ddr3_tags[] = { 383 MARVELL_TAG_DDR3_CS0, 384 MARVELL_TAG_DDR3_CS1, 385 MARVELL_TAG_DDR3_CS2, 386 MARVELL_TAG_DDR3_CS3, 387 388 MARVELL_TAG_UNDEFINED 389 }; 390 static struct { 391 uint16_t model; 392 uint8_t rev; 393 enum marvell_tags *tags; 394 } tagstbl[] = { 395 #if defined(ORION) 396 { ORION_1(88F1181), 0, ddr_tags }, 397 { ORION_1(88F5082), 2, ddr_tags }, 398 { ORION_1(88F5180N), 3, ddr_tags }, 399 { ORION_1(88F5181), 0, ddr_tags }, 400 { ORION_1(88F5181), 1, ddr_tags }, 401 { ORION_1(88F5181), 2, ddr_tags }, 402 { ORION_1(88F5181), 3, ddr_tags }, 403 { ORION_1(88F5181), 8, ddr_tags }, 404 { ORION_1(88F5181), 9, ddr_tags }, 405 { ORION_1(88F5182), 0, ddr_tags }, 406 { ORION_1(88F5182), 1, ddr_tags }, 407 { ORION_1(88F5182), 2, ddr_tags }, 408 { ORION_1(88F6082), 0, ddr_tags }, 409 { ORION_1(88F6082), 1, ddr_tags }, 410 { ORION_1(88F6183), 0, ddr_tags }, 411 { ORION_1(88F6183), 1, ddr_tags }, 412 { ORION_1(88W8660), 0, ddr_tags }, 413 { ORION_1(88W8660), 1, ddr_tags }, 414 415 { ORION_2(88F1281), 0, ddr_tags }, 416 { ORION_2(88F5281), 0, ddr_tags }, 417 { ORION_2(88F5281), 1, ddr_tags }, 418 { ORION_2(88F5281), 2, ddr_tags }, 419 { ORION_2(88F5281), 3, ddr_tags }, 420 { ORION_2(88F5281), 4, ddr_tags }, 421 #endif 422 423 #if defined(KIRKWOOD) 424 { KIRKWOOD(88F6180), 2, ddr_tags }, 425 { KIRKWOOD(88F6180), 3, ddr_tags }, 426 { KIRKWOOD(88F6192), 0, ddr_tags }, 427 { KIRKWOOD(88F6192), 2, ddr_tags }, 428 { KIRKWOOD(88F6192), 3, ddr_tags }, 429 { KIRKWOOD(88F6281), 0, ddr_tags }, 430 { KIRKWOOD(88F6281), 2, ddr_tags }, 431 { KIRKWOOD(88F6281), 3, ddr_tags }, 432 { KIRKWOOD(88F6282), 0, ddr_tags }, 433 { KIRKWOOD(88F6282), 1, ddr_tags }, 434 #endif 435 436 #if defined(MV78XX0) 437 { MV78XX0(MV78100), 1, ddr_tags }, 438 { MV78XX0(MV78100), 2, ddr_tags }, 439 { MV78XX0(MV78200), 1, ddr_tags }, 440 #endif 441 442 #if defined(ARMADAXP) 443 { ARMADAXP(MV78130), 1, ddr3_tags }, 444 { ARMADAXP(MV78160), 1, ddr3_tags }, 445 { ARMADAXP(MV78230), 1, ddr3_tags }, 446 { ARMADAXP(MV78260), 1, ddr3_tags }, 447 { ARMADAXP(MV78260), 2, ddr3_tags }, 448 { ARMADAXP(MV78460), 1, ddr3_tags }, 449 { ARMADAXP(MV78460), 2, ddr3_tags }, 450 451 { ARMADA370(MV6707), 0, ddr3_tags }, 452 { ARMADA370(MV6707), 1, ddr3_tags }, 453 { ARMADA370(MV6710), 0, ddr3_tags }, 454 { ARMADA370(MV6710), 1, ddr3_tags }, 455 { ARMADA370(MV6W11), 0, ddr3_tags }, 456 { ARMADA370(MV6W11), 1, ddr3_tags }, 457 #endif 458 }; 459 460 461 #define OFFSET_DEFAULT MVA_OFFSET_DEFAULT 462 #define IRQ_DEFAULT MVA_IRQ_DEFAULT 463 static const struct mvsoc_periph { 464 int model; 465 const char *name; 466 int unit; 467 bus_size_t offset; 468 int irq; 469 } mvsoc_periphs[] = { 470 #if defined(ORION) 471 #define ORION_IRQ_TMR (32 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 472 473 { ORION_1(88F1181), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 474 { ORION_1(88F1181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 475 { ORION_1(88F1181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 476 { ORION_1(88F1181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 477 { ORION_1(88F1181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 478 { ORION_1(88F1181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 479 { ORION_1(88F1181), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 480 481 { ORION_1(88F5082), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 482 { ORION_1(88F5082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 483 { ORION_1(88F5082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 484 { ORION_1(88F5082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 485 { ORION_1(88F5082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 486 { ORION_1(88F5082), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 487 { ORION_1(88F5082), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 488 { ORION_1(88F5082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 489 { ORION_1(88F5082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 490 { ORION_1(88F5082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 491 { ORION_1(88F5082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 492 { ORION_1(88F5082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 493 494 { ORION_1(88F5180N),"mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 495 { ORION_1(88F5180N),"mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 496 { ORION_1(88F5180N),"com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 497 { ORION_1(88F5180N),"com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 498 { ORION_1(88F5180N),"ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 499 { ORION_1(88F5180N),"gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 500 { ORION_1(88F5180N),"gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 501 { ORION_1(88F5180N),"gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 502 { ORION_1(88F5180N),"mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 503 { ORION_1(88F5180N),"mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 504 505 { ORION_1(88F5181), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 506 { ORION_1(88F5181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 507 { ORION_1(88F5181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 508 { ORION_1(88F5181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 509 { ORION_1(88F5181), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 510 { ORION_1(88F5181), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 511 { ORION_1(88F5181), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 512 { ORION_1(88F5181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 513 { ORION_1(88F5181), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 514 { ORION_1(88F5181), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 515 { ORION_1(88F5181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 516 517 { ORION_1(88F5182), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 518 { ORION_1(88F5182), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 519 { ORION_1(88F5182), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 520 { ORION_1(88F5182), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 521 { ORION_1(88F5182), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 522 { ORION_1(88F5182), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 523 { ORION_1(88F5182), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 524 { ORION_1(88F5182), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 525 { ORION_1(88F5182), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 526 { ORION_1(88F5182), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 527 { ORION_1(88F5182), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 528 { ORION_1(88F5182), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 529 530 { ORION_1(88F6082), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 531 { ORION_1(88F6082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 532 { ORION_1(88F6082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 533 { ORION_1(88F6082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 534 { ORION_1(88F6082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 535 { ORION_1(88F6082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 536 { ORION_1(88F6082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 537 { ORION_1(88F6082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 538 { ORION_1(88F6082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 539 { ORION_1(88F6082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 540 541 { ORION_1(88F6183), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 542 { ORION_1(88F6183), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 543 { ORION_1(88F6183), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 544 { ORION_1(88F6183), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 545 546 { ORION_1(88W8660), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 547 { ORION_1(88W8660), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 548 { ORION_1(88W8660), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 549 { ORION_1(88W8660), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 550 { ORION_1(88W8660), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 551 { ORION_1(88W8660), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 552 { ORION_1(88W8660), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 553 { ORION_1(88W8660), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 554 { ORION_1(88W8660), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 555 { ORION_1(88W8660), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 556 557 { ORION_2(88F1281), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 558 { ORION_2(88F1281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 559 { ORION_2(88F1281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 560 { ORION_2(88F1281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 561 { ORION_2(88F1281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 562 { ORION_2(88F1281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 563 { ORION_2(88F1281), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 564 565 { ORION_2(88F5281), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 566 { ORION_2(88F5281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 567 { ORION_2(88F5281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 568 { ORION_2(88F5281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 569 { ORION_2(88F5281), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 570 { ORION_2(88F5281), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 571 { ORION_2(88F5281), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 572 { ORION_2(88F5281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 573 { ORION_2(88F5281), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 574 { ORION_2(88F5281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 575 #endif 576 577 #if defined(KIRKWOOD) 578 #define KIRKWOOD_IRQ_TMR (64 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 579 580 { KIRKWOOD(88F6180),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 581 { KIRKWOOD(88F6180),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 582 { KIRKWOOD(88F6180),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 583 { KIRKWOOD(88F6180),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 584 { KIRKWOOD(88F6180),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 585 { KIRKWOOD(88F6180),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 586 { KIRKWOOD(88F6180),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 587 { KIRKWOOD(88F6180),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 588 { KIRKWOOD(88F6180),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 589 { KIRKWOOD(88F6180),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 590 { KIRKWOOD(88F6180),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 591 { KIRKWOOD(88F6180),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 592 593 { KIRKWOOD(88F6192),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 594 { KIRKWOOD(88F6192),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 595 { KIRKWOOD(88F6192),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 596 { KIRKWOOD(88F6192),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 597 { KIRKWOOD(88F6192),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 598 { KIRKWOOD(88F6192),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 599 { KIRKWOOD(88F6192),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 600 { KIRKWOOD(88F6192),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 601 { KIRKWOOD(88F6192),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 602 { KIRKWOOD(88F6192),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 603 { KIRKWOOD(88F6192),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 604 { KIRKWOOD(88F6192),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 605 { KIRKWOOD(88F6192),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 606 { KIRKWOOD(88F6192),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 607 608 { KIRKWOOD(88F6281),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 609 { KIRKWOOD(88F6281),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 610 { KIRKWOOD(88F6281),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 611 { KIRKWOOD(88F6281),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 612 { KIRKWOOD(88F6281),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 613 { KIRKWOOD(88F6281),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 614 { KIRKWOOD(88F6281),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 615 { KIRKWOOD(88F6281),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 616 { KIRKWOOD(88F6281),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT }, 617 { KIRKWOOD(88F6281),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 618 { KIRKWOOD(88F6281),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 619 { KIRKWOOD(88F6281),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 620 { KIRKWOOD(88F6281),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 621 { KIRKWOOD(88F6281),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 622 623 { KIRKWOOD(88F6282),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 624 { KIRKWOOD(88F6282),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 625 { KIRKWOOD(88F6282),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 626 { KIRKWOOD(88F6282),"mvsocts", 0, KIRKWOOD_TS_BASE, IRQ_DEFAULT }, 627 { KIRKWOOD(88F6282),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 628 { KIRKWOOD(88F6282),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 629 { KIRKWOOD(88F6282),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 630 { KIRKWOOD(88F6282),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 631 { KIRKWOOD(88F6282),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 632 { KIRKWOOD(88F6282),"gttwsi", 1, KIRKWOOD_TWSI1_BASE,KIRKWOOD_IRQ_TWSI1 }, 633 { KIRKWOOD(88F6282),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 634 { KIRKWOOD(88F6282),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 635 { KIRKWOOD(88F6282),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 636 { KIRKWOOD(88F6282),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 637 { KIRKWOOD(88F6282),"mvpex", 1, KIRKWOOD_PEX1_BASE,KIRKWOOD_IRQ_PEX1INT }, 638 { KIRKWOOD(88F6282),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 639 { KIRKWOOD(88F6282),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 640 #endif 641 642 #if defined(MV78XX0) 643 { MV78XX0(MV78100), "mvsoctmr",0, MVSOC_TMR_BASE, MV78XX0_IRQ_TIMER0 }, 644 { MV78XX0(MV78100), "mvsocgpp",0, MVSOC_GPP_BASE, MV78XX0_IRQ_GPIO0_7 }, 645 { MV78XX0(MV78100), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0 }, 646 { MV78XX0(MV78100), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1 }, 647 { MV78XX0(MV78100), "com", 2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 }, 648 { MV78XX0(MV78100), "com", 3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 }, 649 { MV78XX0(MV78100), "gttwsi", 0, MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI0 }, 650 { MV78XX0(MV78100), "gttwsi", 1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 }, 651 { MV78XX0(MV78100), "mvgbec", 0, MV78XX0_GBE0_BASE,IRQ_DEFAULT }, 652 { MV78XX0(MV78100), "mvgbec", 1, MV78XX0_GBE1_BASE,IRQ_DEFAULT }, 653 { MV78XX0(MV78100), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA }, 654 655 { MV78XX0(MV78200), "mvsoctmr",0, MVSOC_TMR_BASE, MV78XX0_IRQ_TIMER0 }, 656 { MV78XX0(MV78200), "mvsocgpp",0, MVSOC_GPP_BASE, MV78XX0_IRQ_GPIO0_7 }, 657 { MV78XX0(MV78200), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0 }, 658 { MV78XX0(MV78200), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1 }, 659 { MV78XX0(MV78200), "com", 2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 }, 660 { MV78XX0(MV78200), "com", 3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 }, 661 { MV78XX0(MV78200), "gttwsi", 0, MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI0 }, 662 { MV78XX0(MV78200), "gttwsi", 1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 }, 663 { MV78XX0(MV78200), "mvgbec", 0, MV78XX0_GBE0_BASE,IRQ_DEFAULT }, 664 { MV78XX0(MV78200), "mvgbec", 1, MV78XX0_GBE1_BASE,IRQ_DEFAULT }, 665 { MV78XX0(MV78200), "mvgbec", 2, MV78XX0_GBE2_BASE,IRQ_DEFAULT }, 666 { MV78XX0(MV78200), "mvgbec", 3, MV78XX0_GBE3_BASE,IRQ_DEFAULT }, 667 { MV78XX0(MV78200), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA }, 668 #endif 669 670 #if defined(ARMADAXP) 671 { ARMADAXP(MV78130), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 672 { ARMADAXP(MV78130), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 673 { ARMADAXP(MV78130), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 674 { ARMADAXP(MV78130), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 675 { ARMADAXP(MV78130), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 676 { ARMADAXP(MV78130), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 677 { ARMADAXP(MV78130), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 678 { ARMADAXP(MV78130), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 679 { ARMADAXP(MV78130), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 680 { ARMADAXP(MV78130), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 681 { ARMADAXP(MV78130), "mvsocts",0, ARMADAXP_TS_BASE, ARMADAXP_IRQ_PMU }, 682 { ARMADAXP(MV78130), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 683 { ARMADAXP(MV78130), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 684 { ARMADAXP(MV78130), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 685 { ARMADAXP(MV78130), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 686 { ARMADAXP(MV78130), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 687 { ARMADAXP(MV78130), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 688 { ARMADAXP(MV78130), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 689 { ARMADAXP(MV78130), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 690 { ARMADAXP(MV78130), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 691 { ARMADAXP(MV78130), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 692 { ARMADAXP(MV78130), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 693 #if NMVXPE > 0 694 { ARMADAXP(MV78130), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 695 { ARMADAXP(MV78130), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 696 { ARMADAXP(MV78130), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 697 #else 698 { ARMADAXP(MV78130), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 699 { ARMADAXP(MV78130), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 700 #endif 701 #if NMVXPSEC > 0 702 { ARMADAXP(MV78130), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 703 { ARMADAXP(MV78130), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 }, 704 #else 705 { ARMADAXP(MV78130), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 706 { ARMADAXP(MV78130), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 707 #endif 708 709 { ARMADAXP(MV78160), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 710 { ARMADAXP(MV78160), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 711 { ARMADAXP(MV78160), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 712 { ARMADAXP(MV78160), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 713 { ARMADAXP(MV78160), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 714 { ARMADAXP(MV78160), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 715 { ARMADAXP(MV78160), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 716 { ARMADAXP(MV78160), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 717 { ARMADAXP(MV78160), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 718 { ARMADAXP(MV78160), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 719 { ARMADAXP(MV78160), "mvsocts",0, ARMADAXP_TS_BASE, ARMADAXP_IRQ_PMU }, 720 { ARMADAXP(MV78160), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 721 { ARMADAXP(MV78160), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 722 { ARMADAXP(MV78160), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 723 { ARMADAXP(MV78160), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 724 { ARMADAXP(MV78160), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 725 { ARMADAXP(MV78160), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 726 { ARMADAXP(MV78160), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 727 { ARMADAXP(MV78160), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 728 { ARMADAXP(MV78160), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 729 { ARMADAXP(MV78160), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 730 { ARMADAXP(MV78160), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 731 #if NMVXPE > 0 732 { ARMADAXP(MV78160), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 733 { ARMADAXP(MV78160), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 734 { ARMADAXP(MV78160), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 735 { ARMADAXP(MV78160), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 736 { ARMADAXP(MV78160), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX }, 737 #else 738 { ARMADAXP(MV78160), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 739 { ARMADAXP(MV78160), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 740 { ARMADAXP(MV78160), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 741 { ARMADAXP(MV78160), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 742 #endif 743 #if NMVXPSEC > 0 744 { ARMADAXP(MV78160), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 745 { ARMADAXP(MV78160), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 }, 746 #else 747 { ARMADAXP(MV78160), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 748 { ARMADAXP(MV78160), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 749 #endif 750 751 { ARMADAXP(MV78230), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 752 { ARMADAXP(MV78230), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 753 { ARMADAXP(MV78230), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 754 { ARMADAXP(MV78230), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 755 { ARMADAXP(MV78230), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 756 { ARMADAXP(MV78230), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 757 { ARMADAXP(MV78230), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 758 { ARMADAXP(MV78230), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 759 { ARMADAXP(MV78230), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 760 { ARMADAXP(MV78230), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 761 { ARMADAXP(MV78230), "mvsocts",0, ARMADAXP_TS_BASE, ARMADAXP_IRQ_PMU }, 762 { ARMADAXP(MV78230), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 763 { ARMADAXP(MV78230), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 764 { ARMADAXP(MV78230), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 765 { ARMADAXP(MV78230), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 766 { ARMADAXP(MV78230), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 767 { ARMADAXP(MV78230), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 768 { ARMADAXP(MV78230), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 769 { ARMADAXP(MV78230), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 770 { ARMADAXP(MV78230), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 771 { ARMADAXP(MV78230), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 772 { ARMADAXP(MV78230), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 773 #if NMVXPE > 0 774 { ARMADAXP(MV78230), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 775 { ARMADAXP(MV78230), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 776 { ARMADAXP(MV78230), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 777 { ARMADAXP(MV78230), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 778 #else 779 { ARMADAXP(MV78230), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 780 { ARMADAXP(MV78230), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 781 { ARMADAXP(MV78230), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 782 #endif 783 #if NMVXPSEC > 0 784 { ARMADAXP(MV78230), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 785 { ARMADAXP(MV78230), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 }, 786 #else 787 { ARMADAXP(MV78230), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 788 { ARMADAXP(MV78230), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 789 #endif 790 791 { ARMADAXP(MV78260), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 792 { ARMADAXP(MV78260), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 793 { ARMADAXP(MV78260), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 794 { ARMADAXP(MV78260), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 795 { ARMADAXP(MV78260), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 796 { ARMADAXP(MV78260), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 797 { ARMADAXP(MV78260), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 798 { ARMADAXP(MV78260), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 799 { ARMADAXP(MV78260), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 800 { ARMADAXP(MV78260), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 801 { ARMADAXP(MV78260), "mvsocts",0, ARMADAXP_TS_BASE, ARMADAXP_IRQ_PMU }, 802 { ARMADAXP(MV78260), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 803 { ARMADAXP(MV78260), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 804 { ARMADAXP(MV78260), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 805 { ARMADAXP(MV78260), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 806 { ARMADAXP(MV78260), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 807 { ARMADAXP(MV78260), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 808 { ARMADAXP(MV78260), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 809 { ARMADAXP(MV78260), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 810 { ARMADAXP(MV78260), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 811 { ARMADAXP(MV78260), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 812 { ARMADAXP(MV78260), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 813 #if NMVXPE > 0 814 { ARMADAXP(MV78260), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 815 { ARMADAXP(MV78260), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 816 { ARMADAXP(MV78260), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 817 { ARMADAXP(MV78260), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 818 { ARMADAXP(MV78260), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX }, 819 #else 820 { ARMADAXP(MV78260), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 821 { ARMADAXP(MV78260), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 822 { ARMADAXP(MV78260), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 823 { ARMADAXP(MV78260), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 824 #endif 825 #if NMVXPSEC > 0 826 { ARMADAXP(MV78260), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 827 { ARMADAXP(MV78260), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 }, 828 #else 829 { ARMADAXP(MV78260), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 830 { ARMADAXP(MV78260), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 831 #endif 832 833 { ARMADAXP(MV78460), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 834 { ARMADAXP(MV78460), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 835 { ARMADAXP(MV78460), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 836 { ARMADAXP(MV78460), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 837 { ARMADAXP(MV78460), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 838 { ARMADAXP(MV78460), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 839 { ARMADAXP(MV78460), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 840 { ARMADAXP(MV78460), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 841 { ARMADAXP(MV78460), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 842 { ARMADAXP(MV78460), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 843 { ARMADAXP(MV78460), "mvsocts",0, ARMADAXP_TS_BASE, ARMADAXP_IRQ_PMU }, 844 { ARMADAXP(MV78460), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 845 { ARMADAXP(MV78460), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 846 { ARMADAXP(MV78460), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 847 { ARMADAXP(MV78460), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 848 { ARMADAXP(MV78460), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 849 { ARMADAXP(MV78460), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 850 { ARMADAXP(MV78460), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 851 { ARMADAXP(MV78460), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 852 { ARMADAXP(MV78460), "mvpex", 5, ARMADAXP_PEX3_BASE,ARMADAXP_IRQ_PEX3 }, 853 { ARMADAXP(MV78460), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 854 { ARMADAXP(MV78460), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 855 { ARMADAXP(MV78460), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 856 #if NMVXPE > 0 857 { ARMADAXP(MV78460), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 858 { ARMADAXP(MV78460), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 859 { ARMADAXP(MV78460), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 860 { ARMADAXP(MV78460), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 861 { ARMADAXP(MV78460), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX }, 862 #else 863 { ARMADAXP(MV78460), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 864 { ARMADAXP(MV78460), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 865 { ARMADAXP(MV78460), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 866 { ARMADAXP(MV78460), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 867 #endif 868 #if NMVXPSEC > 0 869 { ARMADAXP(MV78460), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 870 { ARMADAXP(MV78460), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 }, 871 #else 872 { ARMADAXP(MV78460), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 873 { ARMADAXP(MV78460), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 874 #endif 875 876 { ARMADA370(MV6710), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 877 { ARMADA370(MV6710), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 878 { ARMADA370(MV6710), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 879 { ARMADA370(MV6710), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 880 { ARMADA370(MV6710), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 881 { ARMADA370(MV6710), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 882 { ARMADA370(MV6710), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 883 { ARMADA370(MV6710), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 884 { ARMADA370(MV6710), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 885 { ARMADA370(MV6710), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 886 { ARMADA370(MV6710), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 887 { ARMADA370(MV6710), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 888 { ARMADA370(MV6710), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 889 { ARMADA370(MV6710), "mvspi", 1, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 890 { ARMADA370(MV6710), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 891 #if NMVXPE > 0 892 { ARMADA370(MV6710), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 893 { ARMADA370(MV6710), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 894 { ARMADA370(MV6710), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 895 #else 896 { ARMADA370(MV6710), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 897 { ARMADA370(MV6710), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 898 #endif 899 #if NMVXPSEC > 0 900 { ARMADA370(MV6710), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 901 #else 902 { ARMADA370(MV6710), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 903 #endif 904 #endif 905 }; 906 907 908 CFATTACH_DECL_NEW(mvsoc, sizeof(struct mvsoc_softc), 909 mvsoc_match, mvsoc_attach, NULL, NULL); 910 911 /* ARGSUSED */ 912 static int 913 mvsoc_match(device_t parent, struct cfdata *match, void *aux) 914 { 915 916 return 1; 917 } 918 919 /* ARGSUSED */ 920 static void 921 mvsoc_attach(device_t parent, device_t self, void *aux) 922 { 923 struct mvsoc_softc *sc = device_private(self); 924 struct marvell_attach_args mva; 925 enum marvell_tags *tags; 926 uint16_t model; 927 uint8_t rev; 928 int i; 929 930 sc->sc_dev = self; 931 sc->sc_iot = &mvsoc_bs_tag; 932 sc->sc_addr = vtophys(regbase); 933 sc->sc_dmat = &mvsoc_bus_dma_tag; 934 if (bus_space_map(sc->sc_iot, sc->sc_addr, 0x100000, 0, &sc->sc_ioh) != 935 0) { 936 aprint_error_dev(self, "can't map registers\n"); 937 return; 938 } 939 940 model = mvsoc_model(); 941 rev = mvsoc_rev(); 942 for (i = 0; i < __arraycount(nametbl); i++) 943 if (nametbl[i].model == model && nametbl[i].rev == rev) 944 break; 945 if (i >= __arraycount(nametbl)) 946 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 947 948 aprint_normal(": Marvell %s %s%s %s\n", 949 nametbl[i].modelstr, 950 nametbl[i].revstr != NULL ? "Rev. " : "", 951 nametbl[i].revstr != NULL ? nametbl[i].revstr : "", 952 nametbl[i].typestr); 953 aprint_normal("%s: CPU Clock %d.%03d MHz" 954 " SysClock %d.%03d MHz TClock %d.%03d MHz\n", 955 device_xname(self), 956 mvPclk / 1000000, (mvPclk / 1000) % 1000, 957 mvSysclk / 1000000, (mvSysclk / 1000) % 1000, 958 mvTclk / 1000000, (mvTclk / 1000) % 1000); 959 aprint_naive("\n"); 960 961 mvsoc_intr_init(); 962 963 for (i = 0; i < __arraycount(tagstbl); i++) 964 if (tagstbl[i].model == model && tagstbl[i].rev == rev) 965 break; 966 if (i >= __arraycount(tagstbl)) 967 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 968 tags = tagstbl[i].tags; 969 970 if (boothowto & (AB_VERBOSE | AB_DEBUG)) 971 mvsoc_target_dump(sc); 972 973 for (i = 0; i < __arraycount(mvsoc_periphs); i++) { 974 if (mvsoc_periphs[i].model != model) 975 continue; 976 977 mva.mva_name = mvsoc_periphs[i].name; 978 mva.mva_model = model; 979 mva.mva_revision = rev; 980 mva.mva_iot = sc->sc_iot; 981 mva.mva_ioh = sc->sc_ioh; 982 mva.mva_unit = mvsoc_periphs[i].unit; 983 mva.mva_addr = sc->sc_addr; 984 mva.mva_offset = mvsoc_periphs[i].offset; 985 mva.mva_size = 0; 986 mva.mva_dmat = sc->sc_dmat; 987 mva.mva_irq = mvsoc_periphs[i].irq; 988 mva.mva_tags = tags; 989 990 /* Skip clock disabled devices */ 991 if (mvsoc_clkgating != NULL && mvsoc_clkgating(&mva)) { 992 aprint_normal_dev(self, "%s%d clock disabled\n", 993 mvsoc_periphs[i].name, mvsoc_periphs[i].unit); 994 continue; 995 } 996 997 config_found_sm_loc(sc->sc_dev, "mvsoc", NULL, &mva, 998 mvsoc_print, mvsoc_search); 999 } 1000 } 1001 1002 static int 1003 mvsoc_print(void *aux, const char *pnp) 1004 { 1005 struct marvell_attach_args *mva = aux; 1006 1007 if (pnp) 1008 aprint_normal("%s at %s unit %d", 1009 mva->mva_name, pnp, mva->mva_unit); 1010 else { 1011 if (mva->mva_unit != MVA_UNIT_DEFAULT) 1012 aprint_normal(" unit %d", mva->mva_unit); 1013 if (mva->mva_offset != MVA_OFFSET_DEFAULT) { 1014 aprint_normal(" offset 0x%04lx", mva->mva_offset); 1015 if (mva->mva_size > 0) 1016 aprint_normal("-0x%04lx", 1017 mva->mva_offset + mva->mva_size - 1); 1018 } 1019 if (mva->mva_irq != MVA_IRQ_DEFAULT) 1020 aprint_normal(" irq %d", mva->mva_irq); 1021 } 1022 1023 return UNCONF; 1024 } 1025 1026 /* ARGSUSED */ 1027 static int 1028 mvsoc_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 1029 { 1030 1031 return config_match(parent, cf, aux); 1032 } 1033 1034 /* ARGSUSED */ 1035 int 1036 marvell_winparams_by_tag(device_t dev, int tag, int *target, int *attribute, 1037 uint64_t *base, uint32_t *size) 1038 { 1039 uint32_t base32; 1040 int rv; 1041 1042 rv = mvsoc_target(tag, target, attribute, &base32, size); 1043 *base = base32; 1044 if (rv == -1) 1045 return -1; 1046 return 0; 1047 } 1048 1049 1050 /* 1051 * These functions is called before bus_space is initialized. 1052 */ 1053 1054 void 1055 mvsoc_bootstrap(bus_addr_t iobase) 1056 { 1057 1058 regbase = iobase; 1059 dsc_base = iobase + MVSOC_DSC_BASE; 1060 mlmb_base = iobase + MVSOC_MLMB_BASE; 1061 pex_base = iobase + MVSOC_PEX_BASE; 1062 #ifdef MVSOC_CONSOLE_EARLY 1063 com_base = iobase + MVSOC_COM0_BASE; 1064 cn_tab = &mvsoc_earlycons; 1065 printf("Hello\n"); 1066 #endif 1067 } 1068 1069 /* 1070 * We can read register of PCI configurations from (MVSOC_PEX_BASE + 0). 1071 */ 1072 uint16_t 1073 mvsoc_model(void) 1074 { 1075 /* 1076 * We read product-id from vendor/device register of PCI-Express. 1077 */ 1078 uint32_t reg; 1079 uint16_t model; 1080 1081 KASSERT(regbase != 0xffffffff); 1082 1083 reg = *(volatile uint32_t *)(pex_base + PCI_ID_REG); 1084 model = PCI_PRODUCT(reg); 1085 1086 #if defined(ORION) 1087 if (model == PCI_PRODUCT_MARVELL_88F5182) { 1088 reg = *(volatile uint32_t *)(regbase + ORION_PMI_BASE + 1089 ORION_PMI_SAMPLE_AT_RESET); 1090 if ((reg & ORION_PMISMPL_TCLK_MASK) == 0) 1091 model = PCI_PRODUCT_MARVELL_88F5082; 1092 } 1093 #endif 1094 #if defined(KIRKWOOD) 1095 if (model == PCI_PRODUCT_MARVELL_88F6281) { 1096 reg = *(volatile uint32_t *)(regbase + KIRKWOOD_MISC_BASE + 1097 KIRKWOOD_MISC_DEVICEID); 1098 if (reg == 1) /* 88F6192 is 1 */ 1099 model = MARVELL_KIRKWOOD_88F6192; 1100 } 1101 #endif 1102 1103 return model; 1104 } 1105 1106 uint8_t 1107 mvsoc_rev(void) 1108 { 1109 uint32_t reg; 1110 uint8_t rev; 1111 1112 KASSERT(regbase != 0xffffffff); 1113 1114 reg = *(volatile uint32_t *)(pex_base + PCI_CLASS_REG); 1115 rev = PCI_REVISION(reg); 1116 1117 return rev; 1118 } 1119 1120 1121 int 1122 mvsoc_target(int tag, uint32_t *target, uint32_t *attr, uint32_t *base, 1123 uint32_t *size) 1124 { 1125 int i; 1126 1127 KASSERT(regbase != 0xffffffff); 1128 1129 if (tag == MVSOC_TAG_INTERNALREG) { 1130 if (target != NULL) 1131 *target = 0; 1132 if (attr != NULL) 1133 *attr = 0; 1134 if (base != NULL) 1135 *base = read_mlmbreg(MVSOC_MLMB_IRBAR) & 1136 MVSOC_MLMB_IRBAR_BASE_MASK; 1137 if (size != NULL) 1138 *size = 0; 1139 1140 return 0; 1141 } 1142 1143 /* sanity check */ 1144 for (i = 0; i < __arraycount(mvsoc_tags); i++) 1145 if (mvsoc_tags[i].tag == tag) 1146 break; 1147 if (i >= __arraycount(mvsoc_tags)) 1148 return -1; 1149 1150 if (target != NULL) 1151 *target = mvsoc_tags[i].target; 1152 if (attr != NULL) 1153 *attr = mvsoc_tags[i].attr; 1154 1155 if (mvsoc_tags[i].target == MVSOC_UNITID_DDR) { 1156 if (tag == MARVELL_TAG_SDRAM_CS0 || 1157 tag == MARVELL_TAG_SDRAM_CS1 || 1158 tag == MARVELL_TAG_SDRAM_CS2 || 1159 tag == MARVELL_TAG_SDRAM_CS3) 1160 return mvsoc_target_ddr(mvsoc_tags[i].attr, base, size); 1161 else 1162 return mvsoc_target_ddr3(mvsoc_tags[i].attr, base, 1163 size); 1164 } else 1165 return mvsoc_target_peripheral(mvsoc_tags[i].target, 1166 mvsoc_tags[i].attr, base, size); 1167 } 1168 1169 static int 1170 mvsoc_target_ddr(uint32_t attr, uint32_t *base, uint32_t *size) 1171 { 1172 uint32_t baseaddrreg, sizereg; 1173 int cs; 1174 1175 /* 1176 * Read DDR SDRAM Controller Address Decode Registers 1177 */ 1178 1179 switch (attr) { 1180 case MARVELL_ATTR_SDRAM_CS0: 1181 cs = 0; 1182 break; 1183 case MARVELL_ATTR_SDRAM_CS1: 1184 cs = 1; 1185 break; 1186 case MARVELL_ATTR_SDRAM_CS2: 1187 cs = 2; 1188 break; 1189 case MARVELL_ATTR_SDRAM_CS3: 1190 cs = 3; 1191 break; 1192 default: 1193 aprint_error("unknwon ATTR: 0x%x", attr); 1194 return -1; 1195 } 1196 sizereg = *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSSR(cs)); 1197 if (sizereg & MVSOC_DSC_CSSR_WINEN) { 1198 baseaddrreg = 1199 *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSBAR(cs)); 1200 1201 if (base != NULL) 1202 *base = baseaddrreg & MVSOC_DSC_CSBAR_BASE_MASK; 1203 if (size != NULL) 1204 *size = (sizereg & MVSOC_DSC_CSSR_SIZE_MASK) + 1205 (~MVSOC_DSC_CSSR_SIZE_MASK + 1); 1206 } else { 1207 if (base != NULL) 1208 *base = 0; 1209 if (size != NULL) 1210 *size = 0; 1211 } 1212 return 0; 1213 } 1214 1215 static int 1216 mvsoc_target_ddr3(uint32_t attr, uint32_t *base, uint32_t *size) 1217 { 1218 uint32_t baseaddrreg, sizereg; 1219 int cs, i; 1220 1221 /* 1222 * Read DDR3 SDRAM Address Decoding Registers 1223 */ 1224 1225 switch (attr) { 1226 case MARVELL_ATTR_SDRAM_CS0: 1227 cs = 0; 1228 break; 1229 case MARVELL_ATTR_SDRAM_CS1: 1230 cs = 1; 1231 break; 1232 case MARVELL_ATTR_SDRAM_CS2: 1233 cs = 2; 1234 break; 1235 case MARVELL_ATTR_SDRAM_CS3: 1236 cs = 3; 1237 break; 1238 default: 1239 aprint_error("unknwon ATTR: 0x%x", attr); 1240 return -1; 1241 } 1242 for (i = 0; i < MVSOC_MLMB_NWIN; i++) { 1243 sizereg = read_mlmbreg(MVSOC_MLMB_WINCR(i)); 1244 if ((sizereg & MVSOC_MLMB_WINCR_EN) && 1245 MVSOC_MLMB_WINCR_WINCS(sizereg) == cs) 1246 break; 1247 } 1248 if (i == MVSOC_MLMB_NWIN) { 1249 if (base != NULL) 1250 *base = 0; 1251 if (size != NULL) 1252 *size = 0; 1253 return 0; 1254 } 1255 1256 baseaddrreg = read_mlmbreg(MVSOC_MLMB_WINBAR(i)); 1257 if (base != NULL) 1258 *base = baseaddrreg & MVSOC_MLMB_WINBAR_BASE_MASK; 1259 if (size != NULL) 1260 *size = (sizereg & MVSOC_MLMB_WINCR_SIZE_MASK) + 1261 (~MVSOC_MLMB_WINCR_SIZE_MASK + 1); 1262 return 0; 1263 } 1264 1265 static int 1266 mvsoc_target_peripheral(uint32_t target, uint32_t attr, uint32_t *base, 1267 uint32_t *size) 1268 { 1269 uint32_t basereg, ctrlreg, ta, tamask; 1270 int i; 1271 1272 /* 1273 * Read CPU Address Map Registers 1274 */ 1275 1276 ta = MVSOC_MLMB_WCR_TARGET(target) | MVSOC_MLMB_WCR_ATTR(attr); 1277 tamask = MVSOC_MLMB_WCR_TARGET(MVSOC_UNITID_MASK) | 1278 MVSOC_MLMB_WCR_ATTR(MARVELL_ATTR_MASK); 1279 1280 if (base != NULL) 1281 *base = 0; 1282 if (size != NULL) 1283 *size = 0; 1284 1285 for (i = 0; i < nwindow; i++) { 1286 ctrlreg = read_mlmbreg(MVSOC_MLMB_WCR(i)); 1287 if ((ctrlreg & tamask) != ta) 1288 continue; 1289 if (ctrlreg & MVSOC_MLMB_WCR_WINEN) { 1290 basereg = read_mlmbreg(MVSOC_MLMB_WBR(i)); 1291 1292 if (base != NULL) 1293 *base = basereg & MVSOC_MLMB_WBR_BASE_MASK; 1294 if (size != NULL) 1295 *size = (ctrlreg & 1296 MVSOC_MLMB_WCR_SIZE_MASK) + 1297 (~MVSOC_MLMB_WCR_SIZE_MASK + 1); 1298 } 1299 break; 1300 } 1301 return i; 1302 } 1303 1304 int 1305 mvsoc_target_dump(struct mvsoc_softc *sc) 1306 { 1307 uint32_t reg, base, size, target, attr, enable; 1308 int i, n; 1309 1310 for (i = 0, n = 0; i < nwindow; i++) { 1311 reg = read_mlmbreg(MVSOC_MLMB_WCR(i)); 1312 enable = reg & MVSOC_MLMB_WCR_WINEN; 1313 target = MVSOC_MLMB_WCR_GET_TARGET(reg); 1314 attr = MVSOC_MLMB_WCR_GET_ATTR(reg); 1315 size = MVSOC_MLMB_WCR_GET_SIZE(reg); 1316 1317 reg = read_mlmbreg(MVSOC_MLMB_WBR(i)); 1318 base = MVSOC_MLMB_WBR_GET_BASE(reg); 1319 1320 if (!enable) 1321 continue; 1322 1323 aprint_verbose_dev(sc->sc_dev, 1324 "Mbus window %2d: Base 0x%08x Size 0x%08x ", i, base, size); 1325 #ifdef ARMADAXP 1326 armadaxp_attr_dump(sc, target, attr); 1327 #else 1328 mvsoc_attr_dump(sc, target, attr); 1329 #endif 1330 printf("\n"); 1331 n++; 1332 } 1333 1334 return n; 1335 } 1336 1337 int 1338 mvsoc_attr_dump(struct mvsoc_softc *sc, uint32_t target, uint32_t attr) 1339 { 1340 aprint_verbose_dev(sc->sc_dev, "target 0x%x(attr 0x%x)", target, attr); 1341 return 0; 1342 } 1343
Indexes created Thu Oct 23 22:10:10 GMT 2025