mvsoc.c revision 1.19
1 /* $NetBSD: mvsoc.c,v 1.19 2015/05/03 14:38:09 hsuenaga Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2013, 2014 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.19 2015/05/03 14:38:09 hsuenaga Exp $"); 30 31 #include "opt_cputypes.h" 32 #include "opt_mvsoc.h" 33 #include "mvxpe.h" 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/errno.h> 39 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pcireg.h> 42 #include <dev/marvell/marvellreg.h> 43 #include <dev/marvell/marvellvar.h> 44 45 #include <arm/marvell/mvsocreg.h> 46 #include <arm/marvell/mvsocvar.h> 47 #include <arm/marvell/orionreg.h> 48 #include <arm/marvell/kirkwoodreg.h> 49 #include <arm/marvell/mv78xx0reg.h> 50 #include <arm/marvell/armadaxpreg.h> 51 52 #include <uvm/uvm.h> 53 54 #include "locators.h" 55 56 #ifdef MVSOC_CONSOLE_EARLY 57 #include <dev/ic/ns16550reg.h> 58 #include <dev/ic/comreg.h> 59 #include <dev/cons.h> 60 #endif 61 62 static int mvsoc_match(device_t, struct cfdata *, void *); 63 static void mvsoc_attach(device_t, device_t, void *); 64 65 static int mvsoc_print(void *, const char *); 66 static int mvsoc_search(device_t, cfdata_t, const int *, void *); 67 68 static int mvsoc_target_ddr(uint32_t, uint32_t *, uint32_t *); 69 static int mvsoc_target_ddr3(uint32_t, uint32_t *, uint32_t *); 70 static int mvsoc_target_peripheral(uint32_t, uint32_t, uint32_t *, uint32_t *); 71 72 uint32_t mvPclk, mvSysclk, mvTclk = 0; 73 int nwindow = 0, nremap = 0; 74 static vaddr_t regbase = 0xffffffff, dsc_base, pex_base; 75 vaddr_t mlmb_base; 76 77 void (*mvsoc_intr_init)(void); 78 int (*mvsoc_clkgating)(struct marvell_attach_args *); 79 80 81 #ifdef MVSOC_CONSOLE_EARLY 82 static vaddr_t com_base; 83 84 static inline uint32_t 85 uart_read(bus_size_t o) 86 { 87 return *(volatile uint32_t *)(com_base + (o << 2)); 88 } 89 90 static inline void 91 uart_write(bus_size_t o, uint32_t v) 92 { 93 *(volatile uint32_t *)(com_base + (o << 2)) = v; 94 } 95 96 static int 97 mvsoc_cngetc(dev_t dv) 98 { 99 if ((uart_read(com_lsr) & LSR_RXRDY) == 0) 100 return -1; 101 102 return uart_read(com_data) & 0xff; 103 } 104 105 static void 106 mvsoc_cnputc(dev_t dv, int c) 107 { 108 int timo = 150000; 109 110 while ((uart_read(com_lsr) & LSR_TXRDY) == 0 && --timo > 0) 111 ; 112 113 uart_write(com_data, c); 114 115 timo = 150000; 116 while ((uart_read(com_lsr) & LSR_TSRE) == 0 && --timo > 0) 117 ; 118 } 119 120 static struct consdev mvsoc_earlycons = { 121 .cn_putc = mvsoc_cnputc, 122 .cn_getc = mvsoc_cngetc, 123 .cn_pollc = nullcnpollc, 124 }; 125 #endif 126 127 128 /* attributes */ 129 static struct { 130 int tag; 131 uint32_t attr; 132 uint32_t target; 133 } mvsoc_tags[] = { 134 { MARVELL_TAG_SDRAM_CS0, 135 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 136 { MARVELL_TAG_SDRAM_CS1, 137 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 138 { MARVELL_TAG_SDRAM_CS2, 139 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 140 { MARVELL_TAG_SDRAM_CS3, 141 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 142 143 { MARVELL_TAG_DDR3_CS0, 144 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 145 { MARVELL_TAG_DDR3_CS1, 146 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 147 { MARVELL_TAG_DDR3_CS2, 148 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 149 { MARVELL_TAG_DDR3_CS3, 150 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 151 152 #if defined(ORION) 153 { ORION_TAG_DEVICE_CS0, 154 ORION_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 155 { ORION_TAG_DEVICE_CS1, 156 ORION_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 157 { ORION_TAG_DEVICE_CS2, 158 ORION_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 159 { ORION_TAG_DEVICE_BOOTCS, 160 ORION_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 161 { ORION_TAG_FLASH_CS, 162 ORION_ATTR_FLASH_CS, MVSOC_UNITID_DEVBUS }, 163 { ORION_TAG_PEX0_MEM, 164 ORION_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 165 { ORION_TAG_PEX0_IO, 166 ORION_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 167 { ORION_TAG_PEX1_MEM, 168 ORION_ATTR_PEX_MEM, ORION_UNITID_PEX1 }, 169 { ORION_TAG_PEX1_IO, 170 ORION_ATTR_PEX_IO, ORION_UNITID_PEX1 }, 171 { ORION_TAG_PCI_MEM, 172 ORION_ATTR_PCI_MEM, ORION_UNITID_PCI }, 173 { ORION_TAG_PCI_IO, 174 ORION_ATTR_PCI_IO, ORION_UNITID_PCI }, 175 { ORION_TAG_CRYPT, 176 ORION_ATTR_CRYPT, ORION_UNITID_CRYPT }, 177 #endif 178 179 #if defined(KIRKWOOD) 180 { KIRKWOOD_TAG_NAND, 181 KIRKWOOD_ATTR_NAND, MVSOC_UNITID_DEVBUS }, 182 { KIRKWOOD_TAG_SPI, 183 KIRKWOOD_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 184 { KIRKWOOD_TAG_BOOTROM, 185 KIRKWOOD_ATTR_BOOTROM, MVSOC_UNITID_DEVBUS }, 186 { KIRKWOOD_TAG_PEX_MEM, 187 KIRKWOOD_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 188 { KIRKWOOD_TAG_PEX_IO, 189 KIRKWOOD_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 190 { KIRKWOOD_TAG_PEX1_MEM, 191 KIRKWOOD_ATTR_PEX1_MEM, MVSOC_UNITID_PEX }, 192 { KIRKWOOD_TAG_PEX1_IO, 193 KIRKWOOD_ATTR_PEX1_IO, MVSOC_UNITID_PEX }, 194 { KIRKWOOD_TAG_CRYPT, 195 KIRKWOOD_ATTR_CRYPT, KIRKWOOD_UNITID_CRYPT }, 196 #endif 197 198 #if defined(MV78XX0) 199 { MV78XX0_TAG_DEVICE_CS0, 200 MV78XX0_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 201 { MV78XX0_TAG_DEVICE_CS1, 202 MV78XX0_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 203 { MV78XX0_TAG_DEVICE_CS2, 204 MV78XX0_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 205 { MV78XX0_TAG_DEVICE_CS3, 206 MV78XX0_ATTR_DEVICE_CS3, MVSOC_UNITID_DEVBUS }, 207 { MV78XX0_TAG_DEVICE_BOOTCS, 208 MV78XX0_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 209 { MV78XX0_TAG_SPI, 210 MV78XX0_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 211 { MV78XX0_TAG_PEX0_MEM, 212 MV78XX0_ATTR_PEX_0_MEM, MVSOC_UNITID_PEX }, 213 { MV78XX0_TAG_PEX01_MEM, 214 MV78XX0_ATTR_PEX_1_MEM, MVSOC_UNITID_PEX }, 215 { MV78XX0_TAG_PEX02_MEM, 216 MV78XX0_ATTR_PEX_2_MEM, MVSOC_UNITID_PEX }, 217 { MV78XX0_TAG_PEX03_MEM, 218 MV78XX0_ATTR_PEX_3_MEM, MVSOC_UNITID_PEX }, 219 { MV78XX0_TAG_PEX0_IO, 220 MV78XX0_ATTR_PEX_0_IO, MVSOC_UNITID_PEX }, 221 { MV78XX0_TAG_PEX01_IO, 222 MV78XX0_ATTR_PEX_1_IO, MVSOC_UNITID_PEX }, 223 { MV78XX0_TAG_PEX02_IO, 224 MV78XX0_ATTR_PEX_2_IO, MVSOC_UNITID_PEX }, 225 { MV78XX0_TAG_PEX03_IO, 226 MV78XX0_ATTR_PEX_3_IO, MVSOC_UNITID_PEX }, 227 { MV78XX0_TAG_PEX1_MEM, 228 MV78XX0_ATTR_PEX_0_MEM, MV78XX0_UNITID_PEX1 }, 229 { MV78XX0_TAG_PEX11_MEM, 230 MV78XX0_ATTR_PEX_1_MEM, MV78XX0_UNITID_PEX1 }, 231 { MV78XX0_TAG_PEX12_MEM, 232 MV78XX0_ATTR_PEX_2_MEM, MV78XX0_UNITID_PEX1 }, 233 { MV78XX0_TAG_PEX13_MEM, 234 MV78XX0_ATTR_PEX_3_MEM, MV78XX0_UNITID_PEX1 }, 235 { MV78XX0_TAG_PEX1_IO, 236 MV78XX0_ATTR_PEX_0_IO, MV78XX0_UNITID_PEX1 }, 237 { MV78XX0_TAG_PEX11_IO, 238 MV78XX0_ATTR_PEX_1_IO, MV78XX0_UNITID_PEX1 }, 239 { MV78XX0_TAG_PEX12_IO, 240 MV78XX0_ATTR_PEX_2_IO, MV78XX0_UNITID_PEX1 }, 241 { MV78XX0_TAG_PEX13_IO, 242 MV78XX0_ATTR_PEX_3_IO, MV78XX0_UNITID_PEX1 }, 243 { MV78XX0_TAG_CRYPT, 244 MV78XX0_ATTR_CRYPT, MV78XX0_UNITID_CRYPT }, 245 #endif 246 247 #if defined(ARMADAXP) 248 { ARMADAXP_TAG_PEX00_MEM, 249 ARMADAXP_ATTR_PEXx0_MEM, ARMADAXP_UNITID_PEX0 }, 250 { ARMADAXP_TAG_PEX00_IO, 251 ARMADAXP_ATTR_PEXx0_IO, ARMADAXP_UNITID_PEX0 }, 252 { ARMADAXP_TAG_PEX01_MEM, 253 ARMADAXP_ATTR_PEXx1_MEM, ARMADAXP_UNITID_PEX0 }, 254 { ARMADAXP_TAG_PEX01_IO, 255 ARMADAXP_ATTR_PEXx1_IO, ARMADAXP_UNITID_PEX0 }, 256 { ARMADAXP_TAG_PEX02_MEM, 257 ARMADAXP_ATTR_PEXx2_MEM, ARMADAXP_UNITID_PEX0 }, 258 { ARMADAXP_TAG_PEX02_IO, 259 ARMADAXP_ATTR_PEXx2_IO, ARMADAXP_UNITID_PEX0 }, 260 { ARMADAXP_TAG_PEX03_MEM, 261 ARMADAXP_ATTR_PEXx3_MEM, ARMADAXP_UNITID_PEX0 }, 262 { ARMADAXP_TAG_PEX03_IO, 263 ARMADAXP_ATTR_PEXx3_IO, ARMADAXP_UNITID_PEX0 }, 264 { ARMADAXP_TAG_PEX2_MEM, 265 ARMADAXP_ATTR_PEX2_MEM, ARMADAXP_UNITID_PEX2 }, 266 { ARMADAXP_TAG_PEX2_IO, 267 ARMADAXP_ATTR_PEX2_IO, ARMADAXP_UNITID_PEX2 }, 268 { ARMADAXP_TAG_PEX3_MEM, 269 ARMADAXP_ATTR_PEX3_MEM, ARMADAXP_UNITID_PEX3 }, 270 { ARMADAXP_TAG_PEX3_IO, 271 ARMADAXP_ATTR_PEX3_IO, ARMADAXP_UNITID_PEX3 }, 272 #endif 273 }; 274 275 #if defined(ORION) 276 #define ORION_1(m) MARVELL_ORION_1_ ## m 277 #define ORION_2(m) MARVELL_ORION_2_ ## m 278 #endif 279 #if defined(KIRKWOOD) 280 #undef KIRKWOOD 281 #define KIRKWOOD(m) MARVELL_KIRKWOOD_ ## m 282 #endif 283 #if defined(MV78XX0) 284 #undef MV78XX0 285 #define MV78XX0(m) MARVELL_MV78XX0_ ## m 286 #endif 287 #if defined(ARMADAXP) 288 #undef ARMADAXP 289 #define ARMADAXP(m) MARVELL_ARMADAXP_ ## m 290 #define ARMADA370(m) MARVELL_ARMADA370_ ## m 291 #endif 292 static struct { 293 uint16_t model; 294 uint8_t rev; 295 const char *modelstr; 296 const char *revstr; 297 const char *typestr; 298 } nametbl[] = { 299 #if defined(ORION) 300 { ORION_1(88F1181), 0, "MV88F1181", NULL, "Orion1" }, 301 { ORION_1(88F5082), 2, "MV88F5082", "A2", "Orion1" }, 302 { ORION_1(88F5180N), 3, "MV88F5180N","B1", "Orion1" }, 303 { ORION_1(88F5181), 0, "MV88F5181", "A0", "Orion1" }, 304 { ORION_1(88F5181), 1, "MV88F5181", "A1", "Orion1" }, 305 { ORION_1(88F5181), 2, "MV88F5181", "B0", "Orion1" }, 306 { ORION_1(88F5181), 3, "MV88F5181", "B1", "Orion1" }, 307 { ORION_1(88F5181), 8, "MV88F5181L","A0", "Orion1" }, 308 { ORION_1(88F5181), 9, "MV88F5181L","A1", "Orion1" }, 309 { ORION_1(88F5182), 0, "MV88F5182", "A0", "Orion1" }, 310 { ORION_1(88F5182), 1, "MV88F5182", "A1", "Orion1" }, 311 { ORION_1(88F5182), 2, "MV88F5182", "A2", "Orion1" }, 312 { ORION_1(88F6082), 0, "MV88F6082", "A0", "Orion1" }, 313 { ORION_1(88F6082), 1, "MV88F6082", "A1", "Orion1" }, 314 { ORION_1(88F6183), 0, "MV88F6183", "A0", "Orion1" }, 315 { ORION_1(88F6183), 1, "MV88F6183", "Z0", "Orion1" }, 316 { ORION_1(88W8660), 0, "MV88W8660", "A0", "Orion1" }, 317 { ORION_1(88W8660), 1, "MV88W8660", "A1", "Orion1" }, 318 319 { ORION_2(88F1281), 0, "MV88F1281", "A0", "Orion2" }, 320 { ORION_2(88F5281), 0, "MV88F5281", "A0", "Orion2" }, 321 { ORION_2(88F5281), 1, "MV88F5281", "B0", "Orion2" }, 322 { ORION_2(88F5281), 2, "MV88F5281", "C0", "Orion2" }, 323 { ORION_2(88F5281), 3, "MV88F5281", "C1", "Orion2" }, 324 { ORION_2(88F5281), 4, "MV88F5281", "D0", "Orion2" }, 325 #endif 326 327 #if defined(KIRKWOOD) 328 { KIRKWOOD(88F6180), 2, "88F6180", "A0", "Kirkwood" }, 329 { KIRKWOOD(88F6180), 3, "88F6180", "A1", "Kirkwood" }, 330 { KIRKWOOD(88F6192), 0, "88F619x", "Z0", "Kirkwood" }, 331 { KIRKWOOD(88F6192), 2, "88F619x", "A0", "Kirkwood" }, 332 { KIRKWOOD(88F6192), 3, "88F619x", "A1", "Kirkwood" }, 333 { KIRKWOOD(88F6281), 0, "88F6281", "Z0", "Kirkwood" }, 334 { KIRKWOOD(88F6281), 2, "88F6281", "A0", "Kirkwood" }, 335 { KIRKWOOD(88F6281), 3, "88F6281", "A1", "Kirkwood" }, 336 { KIRKWOOD(88F6282), 0, "88F6282", "A0", "Kirkwood" }, 337 { KIRKWOOD(88F6282), 1, "88F6282", "A1", "Kirkwood" }, 338 #endif 339 340 #if defined(MV78XX0) 341 { MV78XX0(MV78100), 1, "MV78100", "A0", "Discovery Innovation" }, 342 { MV78XX0(MV78100), 2, "MV78100", "A1", "Discovery Innovation" }, 343 { MV78XX0(MV78200), 1, "MV78200", "A0", "Discovery Innovation" }, 344 #endif 345 346 #if defined(ARMADAXP) 347 { ARMADAXP(MV78130), 1, "MV78130", "A0", "Armada XP" }, 348 { ARMADAXP(MV78160), 1, "MV78160", "A0", "Armada XP" }, 349 { ARMADAXP(MV78230), 1, "MV78260", "A0", "Armada XP" }, 350 { ARMADAXP(MV78260), 1, "MV78260", "A0", "Armada XP" }, 351 { ARMADAXP(MV78460), 1, "MV78460", "A0", "Armada XP" }, 352 { ARMADAXP(MV78460), 2, "MV78460", "B0", "Armada XP" }, 353 354 { ARMADA370(MV6707), 0, "MV6707", "A0", "Armada 370" }, 355 { ARMADA370(MV6707), 1, "MV6707", "A1", "Armada 370" }, 356 { ARMADA370(MV6710), 0, "MV6710", "A0", "Armada 370" }, 357 { ARMADA370(MV6710), 1, "MV6710", "A1", "Armada 370" }, 358 { ARMADA370(MV6W11), 0, "MV6W11", "A0", "Armada 370" }, 359 { ARMADA370(MV6W11), 1, "MV6W11", "A1", "Armada 370" }, 360 #endif 361 }; 362 363 enum marvell_tags ddr_tags[] = { 364 MARVELL_TAG_SDRAM_CS0, 365 MARVELL_TAG_SDRAM_CS1, 366 MARVELL_TAG_SDRAM_CS2, 367 MARVELL_TAG_SDRAM_CS3, 368 369 MARVELL_TAG_UNDEFINED 370 }; 371 enum marvell_tags ddr3_tags[] = { 372 MARVELL_TAG_DDR3_CS0, 373 MARVELL_TAG_DDR3_CS1, 374 MARVELL_TAG_DDR3_CS2, 375 MARVELL_TAG_DDR3_CS3, 376 377 MARVELL_TAG_UNDEFINED 378 }; 379 static struct { 380 uint16_t model; 381 uint8_t rev; 382 enum marvell_tags *tags; 383 } tagstbl[] = { 384 #if defined(ORION) 385 { ORION_1(88F1181), 0, ddr_tags }, 386 { ORION_1(88F5082), 2, ddr_tags }, 387 { ORION_1(88F5180N), 3, ddr_tags }, 388 { ORION_1(88F5181), 0, ddr_tags }, 389 { ORION_1(88F5181), 1, ddr_tags }, 390 { ORION_1(88F5181), 2, ddr_tags }, 391 { ORION_1(88F5181), 3, ddr_tags }, 392 { ORION_1(88F5181), 8, ddr_tags }, 393 { ORION_1(88F5181), 9, ddr_tags }, 394 { ORION_1(88F5182), 0, ddr_tags }, 395 { ORION_1(88F5182), 1, ddr_tags }, 396 { ORION_1(88F5182), 2, ddr_tags }, 397 { ORION_1(88F6082), 0, ddr_tags }, 398 { ORION_1(88F6082), 1, ddr_tags }, 399 { ORION_1(88F6183), 0, ddr_tags }, 400 { ORION_1(88F6183), 1, ddr_tags }, 401 { ORION_1(88W8660), 0, ddr_tags }, 402 { ORION_1(88W8660), 1, ddr_tags }, 403 404 { ORION_2(88F1281), 0, ddr_tags }, 405 { ORION_2(88F5281), 0, ddr_tags }, 406 { ORION_2(88F5281), 1, ddr_tags }, 407 { ORION_2(88F5281), 2, ddr_tags }, 408 { ORION_2(88F5281), 3, ddr_tags }, 409 { ORION_2(88F5281), 4, ddr_tags }, 410 #endif 411 412 #if defined(KIRKWOOD) 413 { KIRKWOOD(88F6180), 2, ddr_tags }, 414 { KIRKWOOD(88F6180), 3, ddr_tags }, 415 { KIRKWOOD(88F6192), 0, ddr_tags }, 416 { KIRKWOOD(88F6192), 2, ddr_tags }, 417 { KIRKWOOD(88F6192), 3, ddr_tags }, 418 { KIRKWOOD(88F6281), 0, ddr_tags }, 419 { KIRKWOOD(88F6281), 2, ddr_tags }, 420 { KIRKWOOD(88F6281), 3, ddr_tags }, 421 { KIRKWOOD(88F6282), 0, ddr_tags }, 422 { KIRKWOOD(88F6282), 1, ddr_tags }, 423 #endif 424 425 #if defined(MV78XX0) 426 { MV78XX0(MV78100), 1, ddr_tags }, 427 { MV78XX0(MV78100), 2, ddr_tags }, 428 { MV78XX0(MV78200), 1, ddr_tags }, 429 #endif 430 431 #if defined(ARMADAXP) 432 { ARMADAXP(MV78130), 1, ddr3_tags }, 433 { ARMADAXP(MV78160), 1, ddr3_tags }, 434 { ARMADAXP(MV78230), 1, ddr3_tags }, 435 { ARMADAXP(MV78260), 1, ddr3_tags }, 436 { ARMADAXP(MV78460), 1, ddr3_tags }, 437 { ARMADAXP(MV78460), 2, ddr3_tags }, 438 439 { ARMADA370(MV6707), 0, ddr3_tags }, 440 { ARMADA370(MV6707), 1, ddr3_tags }, 441 { ARMADA370(MV6710), 0, ddr3_tags }, 442 { ARMADA370(MV6710), 1, ddr3_tags }, 443 { ARMADA370(MV6W11), 0, ddr3_tags }, 444 { ARMADA370(MV6W11), 1, ddr3_tags }, 445 #endif 446 }; 447 448 449 #define OFFSET_DEFAULT MVA_OFFSET_DEFAULT 450 #define IRQ_DEFAULT MVA_IRQ_DEFAULT 451 static const struct mvsoc_periph { 452 int model; 453 const char *name; 454 int unit; 455 bus_size_t offset; 456 int irq; 457 } mvsoc_periphs[] = { 458 #if defined(ORION) 459 #define ORION_IRQ_TMR (32 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 460 461 { ORION_1(88F1181), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 462 { ORION_1(88F1181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 463 { ORION_1(88F1181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 464 { ORION_1(88F1181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 465 { ORION_1(88F1181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 466 { ORION_1(88F1181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 467 { ORION_1(88F1181), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 468 469 { ORION_1(88F5082), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 470 { ORION_1(88F5082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 471 { ORION_1(88F5082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 472 { ORION_1(88F5082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 473 { ORION_1(88F5082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 474 { ORION_1(88F5082), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 475 { ORION_1(88F5082), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 476 { ORION_1(88F5082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 477 { ORION_1(88F5082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 478 { ORION_1(88F5082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 479 { ORION_1(88F5082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 480 { ORION_1(88F5082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 481 482 { ORION_1(88F5180N),"mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 483 { ORION_1(88F5180N),"mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 484 { ORION_1(88F5180N),"com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 485 { ORION_1(88F5180N),"com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 486 { ORION_1(88F5180N),"ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 487 { ORION_1(88F5180N),"gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 488 { ORION_1(88F5180N),"gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 489 { ORION_1(88F5180N),"gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 490 { ORION_1(88F5180N),"mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 491 { ORION_1(88F5180N),"mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 492 493 { ORION_1(88F5181), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 494 { ORION_1(88F5181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 495 { ORION_1(88F5181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 496 { ORION_1(88F5181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 497 { ORION_1(88F5181), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 498 { ORION_1(88F5181), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 499 { ORION_1(88F5181), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 500 { ORION_1(88F5181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 501 { ORION_1(88F5181), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 502 { ORION_1(88F5181), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 503 { ORION_1(88F5181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 504 505 { ORION_1(88F5182), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 506 { ORION_1(88F5182), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 507 { ORION_1(88F5182), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 508 { ORION_1(88F5182), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 509 { ORION_1(88F5182), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 510 { ORION_1(88F5182), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 511 { ORION_1(88F5182), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 512 { ORION_1(88F5182), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 513 { ORION_1(88F5182), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 514 { ORION_1(88F5182), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 515 { ORION_1(88F5182), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 516 { ORION_1(88F5182), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 517 518 { ORION_1(88F6082), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 519 { ORION_1(88F6082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 520 { ORION_1(88F6082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 521 { ORION_1(88F6082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 522 { ORION_1(88F6082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 523 { ORION_1(88F6082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 524 { ORION_1(88F6082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 525 { ORION_1(88F6082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 526 { ORION_1(88F6082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 527 { ORION_1(88F6082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 528 529 { ORION_1(88F6183), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 530 { ORION_1(88F6183), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 531 { ORION_1(88F6183), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 532 { ORION_1(88F6183), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 533 534 { ORION_1(88W8660), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 535 { ORION_1(88W8660), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 536 { ORION_1(88W8660), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 537 { ORION_1(88W8660), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 538 { ORION_1(88W8660), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 539 { ORION_1(88W8660), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 540 { ORION_1(88W8660), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 541 { ORION_1(88W8660), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 542 { ORION_1(88W8660), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 543 { ORION_1(88W8660), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 544 545 { ORION_2(88F1281), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 546 { ORION_2(88F1281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 547 { ORION_2(88F1281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 548 { ORION_2(88F1281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 549 { ORION_2(88F1281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 550 { ORION_2(88F1281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 551 { ORION_2(88F1281), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 552 553 { ORION_2(88F5281), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 554 { ORION_2(88F5281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 555 { ORION_2(88F5281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 556 { ORION_2(88F5281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 557 { ORION_2(88F5281), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 558 { ORION_2(88F5281), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 559 { ORION_2(88F5281), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 560 { ORION_2(88F5281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 561 { ORION_2(88F5281), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 562 { ORION_2(88F5281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 563 #endif 564 565 #if defined(KIRKWOOD) 566 #define KIRKWOOD_IRQ_TMR (64 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 567 568 { KIRKWOOD(88F6180),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 569 { KIRKWOOD(88F6180),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 570 { KIRKWOOD(88F6180),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 571 { KIRKWOOD(88F6180),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 572 { KIRKWOOD(88F6180),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 573 { KIRKWOOD(88F6180),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 574 { KIRKWOOD(88F6180),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 575 { KIRKWOOD(88F6180),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 576 { KIRKWOOD(88F6180),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 577 { KIRKWOOD(88F6180),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 578 { KIRKWOOD(88F6180),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 579 { KIRKWOOD(88F6180),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 580 581 { KIRKWOOD(88F6192),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 582 { KIRKWOOD(88F6192),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 583 { KIRKWOOD(88F6192),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 584 { KIRKWOOD(88F6192),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 585 { KIRKWOOD(88F6192),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 586 { KIRKWOOD(88F6192),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 587 { KIRKWOOD(88F6192),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 588 { KIRKWOOD(88F6192),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 589 { KIRKWOOD(88F6192),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 590 { KIRKWOOD(88F6192),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 591 { KIRKWOOD(88F6192),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 592 { KIRKWOOD(88F6192),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 593 { KIRKWOOD(88F6192),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 594 { KIRKWOOD(88F6192),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 595 596 { KIRKWOOD(88F6281),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 597 { KIRKWOOD(88F6281),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 598 { KIRKWOOD(88F6281),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 599 { KIRKWOOD(88F6281),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 600 { KIRKWOOD(88F6281),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 601 { KIRKWOOD(88F6281),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 602 { KIRKWOOD(88F6281),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 603 { KIRKWOOD(88F6281),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 604 { KIRKWOOD(88F6281),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT }, 605 { KIRKWOOD(88F6281),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 606 { KIRKWOOD(88F6281),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 607 { KIRKWOOD(88F6281),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 608 { KIRKWOOD(88F6281),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 609 { KIRKWOOD(88F6281),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 610 611 { KIRKWOOD(88F6282),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 612 { KIRKWOOD(88F6282),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 613 { KIRKWOOD(88F6282),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 614 { KIRKWOOD(88F6282),"mvsocts", 0, KIRKWOOD_TS_BASE, IRQ_DEFAULT }, 615 { KIRKWOOD(88F6282),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 616 { KIRKWOOD(88F6282),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 617 { KIRKWOOD(88F6282),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 618 { KIRKWOOD(88F6282),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 619 { KIRKWOOD(88F6282),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 620 { KIRKWOOD(88F6282),"gttwsi", 1, KIRKWOOD_TWSI1_BASE,KIRKWOOD_IRQ_TWSI1 }, 621 { KIRKWOOD(88F6282),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 622 { KIRKWOOD(88F6282),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 623 { KIRKWOOD(88F6282),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 624 { KIRKWOOD(88F6282),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 625 { KIRKWOOD(88F6282),"mvpex", 1, KIRKWOOD_PEX1_BASE,KIRKWOOD_IRQ_PEX1INT }, 626 { KIRKWOOD(88F6282),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 627 { KIRKWOOD(88F6282),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 628 #endif 629 630 #if defined(MV78XX0) 631 { MV78XX0(MV78100), "mvsoctmr",0, MVSOC_TMR_BASE, MV78XX0_IRQ_TIMER0 }, 632 { MV78XX0(MV78100), "mvsocgpp",0, MVSOC_GPP_BASE, MV78XX0_IRQ_GPIO0_7 }, 633 { MV78XX0(MV78100), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0 }, 634 { MV78XX0(MV78100), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1 }, 635 { MV78XX0(MV78100), "com", 2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 }, 636 { MV78XX0(MV78100), "com", 3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 }, 637 { MV78XX0(MV78100), "gttwsi", 0, MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI0 }, 638 { MV78XX0(MV78100), "gttwsi", 1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 }, 639 { MV78XX0(MV78100), "mvgbec", 0, MV78XX0_GBE0_BASE,IRQ_DEFAULT }, 640 { MV78XX0(MV78100), "mvgbec", 1, MV78XX0_GBE1_BASE,IRQ_DEFAULT }, 641 { MV78XX0(MV78100), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA }, 642 643 { MV78XX0(MV78200), "mvsoctmr",0, MVSOC_TMR_BASE, MV78XX0_IRQ_TIMER0 }, 644 { MV78XX0(MV78200), "mvsocgpp",0, MVSOC_GPP_BASE, MV78XX0_IRQ_GPIO0_7 }, 645 { MV78XX0(MV78200), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0 }, 646 { MV78XX0(MV78200), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1 }, 647 { MV78XX0(MV78200), "com", 2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 }, 648 { MV78XX0(MV78200), "com", 3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 }, 649 { MV78XX0(MV78200), "gttwsi", 0, MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI0 }, 650 { MV78XX0(MV78200), "gttwsi", 1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 }, 651 { MV78XX0(MV78200), "mvgbec", 0, MV78XX0_GBE0_BASE,IRQ_DEFAULT }, 652 { MV78XX0(MV78200), "mvgbec", 1, MV78XX0_GBE1_BASE,IRQ_DEFAULT }, 653 { MV78XX0(MV78200), "mvgbec", 2, MV78XX0_GBE2_BASE,IRQ_DEFAULT }, 654 { MV78XX0(MV78200), "mvgbec", 3, MV78XX0_GBE3_BASE,IRQ_DEFAULT }, 655 { MV78XX0(MV78200), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA }, 656 #endif 657 658 #if defined(ARMADAXP) 659 { ARMADAXP(MV78130), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 660 { ARMADAXP(MV78130), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 661 { ARMADAXP(MV78130), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 662 { ARMADAXP(MV78130), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 663 { ARMADAXP(MV78130), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 664 { ARMADAXP(MV78130), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 665 { ARMADAXP(MV78130), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 666 { ARMADAXP(MV78130), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 667 { ARMADAXP(MV78130), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 668 { ARMADAXP(MV78130), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 669 { ARMADAXP(MV78130), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 670 { ARMADAXP(MV78130), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 671 { ARMADAXP(MV78130), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 672 { ARMADAXP(MV78130), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 673 { ARMADAXP(MV78130), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 674 { ARMADAXP(MV78130), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 675 { ARMADAXP(MV78130), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 676 { ARMADAXP(MV78130), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 677 { ARMADAXP(MV78130), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 678 { ARMADAXP(MV78130), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 679 { ARMADAXP(MV78130), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 680 #if NMVXPE > 0 681 { ARMADAXP(MV78130), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 682 { ARMADAXP(MV78130), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 683 #else 684 { ARMADAXP(MV78130), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 685 { ARMADAXP(MV78130), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 686 #endif 687 { ARMADAXP(MV78130), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 688 { ARMADAXP(MV78130), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 689 690 { ARMADAXP(MV78160), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 691 { ARMADAXP(MV78160), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 692 { ARMADAXP(MV78160), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 693 { ARMADAXP(MV78160), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 694 { ARMADAXP(MV78160), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 695 { ARMADAXP(MV78160), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 696 { ARMADAXP(MV78160), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 697 { ARMADAXP(MV78160), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 698 { ARMADAXP(MV78160), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 699 { ARMADAXP(MV78160), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 700 { ARMADAXP(MV78160), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 701 { ARMADAXP(MV78160), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 702 { ARMADAXP(MV78160), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 703 { ARMADAXP(MV78160), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 704 { ARMADAXP(MV78160), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 705 { ARMADAXP(MV78160), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 706 { ARMADAXP(MV78160), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 707 { ARMADAXP(MV78160), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 708 { ARMADAXP(MV78160), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 709 { ARMADAXP(MV78160), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 710 { ARMADAXP(MV78160), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 711 #if NMVXPE > 0 712 { ARMADAXP(MV78160), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 713 { ARMADAXP(MV78160), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 714 { ARMADAXP(MV78160), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 715 { ARMADAXP(MV78160), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX }, 716 #else 717 { ARMADAXP(MV78160), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 718 { ARMADAXP(MV78160), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 719 { ARMADAXP(MV78160), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 720 { ARMADAXP(MV78160), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 721 #endif 722 { ARMADAXP(MV78160), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 723 { ARMADAXP(MV78160), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 724 725 { ARMADAXP(MV78230), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 726 { ARMADAXP(MV78230), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 727 { ARMADAXP(MV78230), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 728 { ARMADAXP(MV78230), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 729 { ARMADAXP(MV78230), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 730 { ARMADAXP(MV78230), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 731 { ARMADAXP(MV78230), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 732 { ARMADAXP(MV78230), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 733 { ARMADAXP(MV78230), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 734 { ARMADAXP(MV78230), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 735 { ARMADAXP(MV78230), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 736 { ARMADAXP(MV78230), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 737 { ARMADAXP(MV78230), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 738 { ARMADAXP(MV78230), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 739 { ARMADAXP(MV78230), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 740 { ARMADAXP(MV78230), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 741 { ARMADAXP(MV78230), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 742 { ARMADAXP(MV78230), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 743 { ARMADAXP(MV78230), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 744 { ARMADAXP(MV78230), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 745 { ARMADAXP(MV78230), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 746 #if NMVXPE > 0 747 { ARMADAXP(MV78230), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 748 { ARMADAXP(MV78230), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 749 { ARMADAXP(MV78230), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 750 #else 751 { ARMADAXP(MV78230), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 752 { ARMADAXP(MV78230), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 753 { ARMADAXP(MV78230), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 754 #endif 755 { ARMADAXP(MV78230), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 756 { ARMADAXP(MV78230), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 757 758 { ARMADAXP(MV78260), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 759 { ARMADAXP(MV78260), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 760 { ARMADAXP(MV78260), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 761 { ARMADAXP(MV78260), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 762 { ARMADAXP(MV78260), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 763 { ARMADAXP(MV78260), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 764 { ARMADAXP(MV78260), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 765 { ARMADAXP(MV78260), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 766 { ARMADAXP(MV78260), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 767 { ARMADAXP(MV78260), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 768 { ARMADAXP(MV78260), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 769 { ARMADAXP(MV78260), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 770 { ARMADAXP(MV78260), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 771 { ARMADAXP(MV78260), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 772 { ARMADAXP(MV78260), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 773 { ARMADAXP(MV78260), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 774 { ARMADAXP(MV78260), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 775 { ARMADAXP(MV78260), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 776 { ARMADAXP(MV78260), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 777 { ARMADAXP(MV78260), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 778 { ARMADAXP(MV78260), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 779 #if NMVXPE > 0 780 { ARMADAXP(MV78260), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 781 { ARMADAXP(MV78260), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 782 { ARMADAXP(MV78260), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 783 { ARMADAXP(MV78260), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX }, 784 #else 785 { ARMADAXP(MV78260), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 786 { ARMADAXP(MV78260), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 787 { ARMADAXP(MV78260), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 788 { ARMADAXP(MV78260), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 789 #endif 790 { ARMADAXP(MV78260), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 791 { ARMADAXP(MV78260), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 792 793 { ARMADAXP(MV78460), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 794 { ARMADAXP(MV78460), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 795 { ARMADAXP(MV78460), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 796 { ARMADAXP(MV78460), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 797 { ARMADAXP(MV78460), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 798 { ARMADAXP(MV78460), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 799 { ARMADAXP(MV78460), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 800 { ARMADAXP(MV78460), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 801 { ARMADAXP(MV78460), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 802 { ARMADAXP(MV78460), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 803 { ARMADAXP(MV78460), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 804 { ARMADAXP(MV78460), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 805 { ARMADAXP(MV78460), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 806 { ARMADAXP(MV78460), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 807 { ARMADAXP(MV78460), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 808 { ARMADAXP(MV78460), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 809 { ARMADAXP(MV78460), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 810 { ARMADAXP(MV78460), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 811 { ARMADAXP(MV78460), "mvpex", 5, ARMADAXP_PEX3_BASE,ARMADAXP_IRQ_PEX3 }, 812 { ARMADAXP(MV78460), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 813 { ARMADAXP(MV78460), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 814 { ARMADAXP(MV78460), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 815 #if NMVXPE > 0 816 { ARMADAXP(MV78460), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 817 { ARMADAXP(MV78460), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 818 { ARMADAXP(MV78460), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 819 { ARMADAXP(MV78460), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX }, 820 #else 821 { ARMADAXP(MV78460), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 822 { ARMADAXP(MV78460), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 823 { ARMADAXP(MV78460), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 824 { ARMADAXP(MV78460), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 825 #endif 826 { ARMADAXP(MV78460), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 827 { ARMADAXP(MV78460), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 828 829 { ARMADA370(MV6710), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 830 { ARMADA370(MV6710), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 831 { ARMADA370(MV6710), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 832 { ARMADA370(MV6710), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 833 { ARMADA370(MV6710), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 834 { ARMADA370(MV6710), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 835 { ARMADA370(MV6710), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 836 { ARMADA370(MV6710), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 837 { ARMADA370(MV6710), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 838 { ARMADA370(MV6710), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 839 { ARMADA370(MV6710), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 840 { ARMADA370(MV6710), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 841 { ARMADA370(MV6710), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 842 { ARMADA370(MV6710), "mvspi", 1, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 843 { ARMADA370(MV6710), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 844 #if NMVXPE > 0 845 { ARMADA370(MV6710), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 846 { ARMADA370(MV6710), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 847 #else 848 { ARMADA370(MV6710), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 849 { ARMADA370(MV6710), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 850 #endif 851 { ARMADA370(MV6710), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 852 #endif 853 }; 854 855 856 CFATTACH_DECL_NEW(mvsoc, sizeof(struct mvsoc_softc), 857 mvsoc_match, mvsoc_attach, NULL, NULL); 858 859 /* ARGSUSED */ 860 static int 861 mvsoc_match(device_t parent, struct cfdata *match, void *aux) 862 { 863 864 return 1; 865 } 866 867 /* ARGSUSED */ 868 static void 869 mvsoc_attach(device_t parent, device_t self, void *aux) 870 { 871 struct mvsoc_softc *sc = device_private(self); 872 struct marvell_attach_args mva; 873 enum marvell_tags *tags; 874 uint16_t model; 875 uint8_t rev; 876 int i; 877 878 sc->sc_dev = self; 879 sc->sc_iot = &mvsoc_bs_tag; 880 sc->sc_addr = vtophys(regbase); 881 sc->sc_dmat = &mvsoc_bus_dma_tag; 882 if (bus_space_map(sc->sc_iot, sc->sc_addr, 0x100000, 0, &sc->sc_ioh) != 883 0) { 884 aprint_error_dev(self, "can't map registers\n"); 885 return; 886 } 887 888 model = mvsoc_model(); 889 rev = mvsoc_rev(); 890 for (i = 0; i < __arraycount(nametbl); i++) 891 if (nametbl[i].model == model && nametbl[i].rev == rev) 892 break; 893 if (i >= __arraycount(nametbl)) 894 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 895 896 aprint_normal(": Marvell %s %s%s %s\n", 897 nametbl[i].modelstr, 898 nametbl[i].revstr != NULL ? "Rev. " : "", 899 nametbl[i].revstr != NULL ? nametbl[i].revstr : "", 900 nametbl[i].typestr); 901 aprint_normal("%s: CPU Clock %d.%03d MHz" 902 " SysClock %d.%03d MHz TClock %d.%03d MHz\n", 903 device_xname(self), 904 mvPclk / 1000000, (mvPclk / 1000) % 1000, 905 mvSysclk / 1000000, (mvSysclk / 1000) % 1000, 906 mvTclk / 1000000, (mvTclk / 1000) % 1000); 907 aprint_naive("\n"); 908 909 mvsoc_intr_init(); 910 911 for (i = 0; i < __arraycount(tagstbl); i++) 912 if (tagstbl[i].model == model && tagstbl[i].rev == rev) 913 break; 914 if (i >= __arraycount(tagstbl)) 915 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 916 tags = tagstbl[i].tags; 917 918 for (i = 0; i < __arraycount(mvsoc_periphs); i++) { 919 if (mvsoc_periphs[i].model != model) 920 continue; 921 922 mva.mva_name = mvsoc_periphs[i].name; 923 mva.mva_model = model; 924 mva.mva_revision = rev; 925 mva.mva_iot = sc->sc_iot; 926 mva.mva_ioh = sc->sc_ioh; 927 mva.mva_unit = mvsoc_periphs[i].unit; 928 mva.mva_addr = sc->sc_addr; 929 mva.mva_offset = mvsoc_periphs[i].offset; 930 mva.mva_size = 0; 931 mva.mva_dmat = sc->sc_dmat; 932 mva.mva_irq = mvsoc_periphs[i].irq; 933 mva.mva_tags = tags; 934 935 /* Skip clock disabled devices */ 936 if (mvsoc_clkgating != NULL && mvsoc_clkgating(&mva)) { 937 aprint_normal_dev(self, "%s%d clock disabled\n", 938 mvsoc_periphs[i].name, mvsoc_periphs[i].unit); 939 continue; 940 } 941 942 config_found_sm_loc(sc->sc_dev, "mvsoc", NULL, &mva, 943 mvsoc_print, mvsoc_search); 944 } 945 } 946 947 static int 948 mvsoc_print(void *aux, const char *pnp) 949 { 950 struct marvell_attach_args *mva = aux; 951 952 if (pnp) 953 aprint_normal("%s at %s unit %d", 954 mva->mva_name, pnp, mva->mva_unit); 955 else { 956 if (mva->mva_unit != MVA_UNIT_DEFAULT) 957 aprint_normal(" unit %d", mva->mva_unit); 958 if (mva->mva_offset != MVA_OFFSET_DEFAULT) { 959 aprint_normal(" offset 0x%04lx", mva->mva_offset); 960 if (mva->mva_size > 0) 961 aprint_normal("-0x%04lx", 962 mva->mva_offset + mva->mva_size - 1); 963 } 964 if (mva->mva_irq != MVA_IRQ_DEFAULT) 965 aprint_normal(" irq %d", mva->mva_irq); 966 } 967 968 return UNCONF; 969 } 970 971 /* ARGSUSED */ 972 static int 973 mvsoc_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 974 { 975 976 return config_match(parent, cf, aux); 977 } 978 979 /* ARGSUSED */ 980 int 981 marvell_winparams_by_tag(device_t dev, int tag, int *target, int *attribute, 982 uint64_t *base, uint32_t *size) 983 { 984 uint32_t base32; 985 int rv; 986 987 rv = mvsoc_target(tag, target, attribute, &base32, size); 988 *base = base32; 989 if (rv == -1) 990 return -1; 991 return 0; 992 } 993 994 995 /* 996 * These functions is called before bus_space is initialized. 997 */ 998 999 void 1000 mvsoc_bootstrap(bus_addr_t iobase) 1001 { 1002 1003 regbase = iobase; 1004 dsc_base = iobase + MVSOC_DSC_BASE; 1005 mlmb_base = iobase + MVSOC_MLMB_BASE; 1006 pex_base = iobase + MVSOC_PEX_BASE; 1007 #ifdef MVSOC_CONSOLE_EARLY 1008 com_base = iobase + MVSOC_COM0_BASE; 1009 cn_tab = &mvsoc_earlycons; 1010 printf("Hello\n"); 1011 #endif 1012 } 1013 1014 /* 1015 * We can read register of PCI configurations from (MVSOC_PEX_BASE + 0). 1016 */ 1017 uint16_t 1018 mvsoc_model(void) 1019 { 1020 /* 1021 * We read product-id from vendor/device register of PCI-Express. 1022 */ 1023 uint32_t reg; 1024 uint16_t model; 1025 1026 KASSERT(regbase != 0xffffffff); 1027 1028 reg = *(volatile uint32_t *)(pex_base + PCI_ID_REG); 1029 model = PCI_PRODUCT(reg); 1030 1031 #if defined(ORION) 1032 if (model == PCI_PRODUCT_MARVELL_88F5182) { 1033 reg = *(volatile uint32_t *)(regbase + ORION_PMI_BASE + 1034 ORION_PMI_SAMPLE_AT_RESET); 1035 if ((reg & ORION_PMISMPL_TCLK_MASK) == 0) 1036 model = PCI_PRODUCT_MARVELL_88F5082; 1037 } 1038 #endif 1039 #if defined(KIRKWOOD) 1040 if (model == PCI_PRODUCT_MARVELL_88F6281) { 1041 reg = *(volatile uint32_t *)(regbase + KIRKWOOD_MISC_BASE + 1042 KIRKWOOD_MISC_DEVICEID); 1043 if (reg == 1) /* 88F6192 is 1 */ 1044 model = MARVELL_KIRKWOOD_88F6192; 1045 } 1046 #endif 1047 1048 return model; 1049 } 1050 1051 uint8_t 1052 mvsoc_rev(void) 1053 { 1054 uint32_t reg; 1055 uint8_t rev; 1056 1057 KASSERT(regbase != 0xffffffff); 1058 1059 reg = *(volatile uint32_t *)(pex_base + PCI_CLASS_REG); 1060 rev = PCI_REVISION(reg); 1061 1062 return rev; 1063 } 1064 1065 1066 int 1067 mvsoc_target(int tag, uint32_t *target, uint32_t *attr, uint32_t *base, 1068 uint32_t *size) 1069 { 1070 int i; 1071 1072 KASSERT(regbase != 0xffffffff); 1073 1074 if (tag == MVSOC_TAG_INTERNALREG) { 1075 if (target != NULL) 1076 *target = 0; 1077 if (attr != NULL) 1078 *attr = 0; 1079 if (base != NULL) 1080 *base = read_mlmbreg(MVSOC_MLMB_IRBAR) & 1081 MVSOC_MLMB_IRBAR_BASE_MASK; 1082 if (size != NULL) 1083 *size = 0; 1084 1085 return 0; 1086 } 1087 1088 /* sanity check */ 1089 for (i = 0; i < __arraycount(mvsoc_tags); i++) 1090 if (mvsoc_tags[i].tag == tag) 1091 break; 1092 if (i >= __arraycount(mvsoc_tags)) 1093 return -1; 1094 1095 if (target != NULL) 1096 *target = mvsoc_tags[i].target; 1097 if (attr != NULL) 1098 *attr = mvsoc_tags[i].attr; 1099 1100 if (mvsoc_tags[i].target == MVSOC_UNITID_DDR) { 1101 if (tag == MARVELL_TAG_SDRAM_CS0 || 1102 tag == MARVELL_TAG_SDRAM_CS1 || 1103 tag == MARVELL_TAG_SDRAM_CS2 || 1104 tag == MARVELL_TAG_SDRAM_CS3) 1105 return mvsoc_target_ddr(mvsoc_tags[i].attr, base, size); 1106 else 1107 return mvsoc_target_ddr3(mvsoc_tags[i].attr, base, 1108 size); 1109 } else 1110 return mvsoc_target_peripheral(mvsoc_tags[i].target, 1111 mvsoc_tags[i].attr, base, size); 1112 } 1113 1114 static int 1115 mvsoc_target_ddr(uint32_t attr, uint32_t *base, uint32_t *size) 1116 { 1117 uint32_t baseaddrreg, sizereg; 1118 int cs; 1119 1120 /* 1121 * Read DDR SDRAM Controller Address Decode Registers 1122 */ 1123 1124 switch (attr) { 1125 case MARVELL_ATTR_SDRAM_CS0: 1126 cs = 0; 1127 break; 1128 case MARVELL_ATTR_SDRAM_CS1: 1129 cs = 1; 1130 break; 1131 case MARVELL_ATTR_SDRAM_CS2: 1132 cs = 2; 1133 break; 1134 case MARVELL_ATTR_SDRAM_CS3: 1135 cs = 3; 1136 break; 1137 default: 1138 aprint_error("unknwon ATTR: 0x%x", attr); 1139 return -1; 1140 } 1141 sizereg = *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSSR(cs)); 1142 if (sizereg & MVSOC_DSC_CSSR_WINEN) { 1143 baseaddrreg = 1144 *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSBAR(cs)); 1145 1146 if (base != NULL) 1147 *base = baseaddrreg & MVSOC_DSC_CSBAR_BASE_MASK; 1148 if (size != NULL) 1149 *size = (sizereg & MVSOC_DSC_CSSR_SIZE_MASK) + 1150 (~MVSOC_DSC_CSSR_SIZE_MASK + 1); 1151 } else { 1152 if (base != NULL) 1153 *base = 0; 1154 if (size != NULL) 1155 *size = 0; 1156 } 1157 return 0; 1158 } 1159 1160 static int 1161 mvsoc_target_ddr3(uint32_t attr, uint32_t *base, uint32_t *size) 1162 { 1163 uint32_t baseaddrreg, sizereg; 1164 int cs, i; 1165 1166 /* 1167 * Read DDR3 SDRAM Address Decoding Registers 1168 */ 1169 1170 switch (attr) { 1171 case MARVELL_ATTR_SDRAM_CS0: 1172 cs = 0; 1173 break; 1174 case MARVELL_ATTR_SDRAM_CS1: 1175 cs = 1; 1176 break; 1177 case MARVELL_ATTR_SDRAM_CS2: 1178 cs = 2; 1179 break; 1180 case MARVELL_ATTR_SDRAM_CS3: 1181 cs = 3; 1182 break; 1183 default: 1184 aprint_error("unknwon ATTR: 0x%x", attr); 1185 return -1; 1186 } 1187 for (i = 0; i < MVSOC_MLMB_NWIN; i++) { 1188 sizereg = read_mlmbreg(MVSOC_MLMB_WINCR(i)); 1189 if ((sizereg & MVSOC_MLMB_WINCR_EN) && 1190 MVSOC_MLMB_WINCR_WINCS(sizereg) == cs) 1191 break; 1192 } 1193 if (i == MVSOC_MLMB_NWIN) { 1194 if (base != NULL) 1195 *base = 0; 1196 if (size != NULL) 1197 *size = 0; 1198 return 0; 1199 } 1200 1201 baseaddrreg = read_mlmbreg(MVSOC_MLMB_WINBAR(i)); 1202 if (base != NULL) 1203 *base = baseaddrreg & MVSOC_MLMB_WINBAR_BASE_MASK; 1204 if (size != NULL) 1205 *size = (sizereg & MVSOC_MLMB_WINCR_SIZE_MASK) + 1206 (~MVSOC_MLMB_WINCR_SIZE_MASK + 1); 1207 return 0; 1208 } 1209 1210 static int 1211 mvsoc_target_peripheral(uint32_t target, uint32_t attr, uint32_t *base, 1212 uint32_t *size) 1213 { 1214 uint32_t basereg, ctrlreg, ta, tamask; 1215 int i; 1216 1217 /* 1218 * Read CPU Address Map Registers 1219 */ 1220 1221 ta = MVSOC_MLMB_WCR_TARGET(target) | MVSOC_MLMB_WCR_ATTR(attr); 1222 tamask = MVSOC_MLMB_WCR_TARGET(MVSOC_UNITID_MASK) | 1223 MVSOC_MLMB_WCR_ATTR(MARVELL_ATTR_MASK); 1224 1225 if (base != NULL) 1226 *base = 0; 1227 if (size != NULL) 1228 *size = 0; 1229 1230 for (i = 0; i < nwindow; i++) { 1231 ctrlreg = read_mlmbreg(MVSOC_MLMB_WCR(i)); 1232 if ((ctrlreg & tamask) != ta) 1233 continue; 1234 if (ctrlreg & MVSOC_MLMB_WCR_WINEN) { 1235 basereg = read_mlmbreg(MVSOC_MLMB_WBR(i)); 1236 1237 if (base != NULL) 1238 *base = basereg & MVSOC_MLMB_WBR_BASE_MASK; 1239 if (size != NULL) 1240 *size = (ctrlreg & 1241 MVSOC_MLMB_WCR_SIZE_MASK) + 1242 (~MVSOC_MLMB_WCR_SIZE_MASK + 1); 1243 } 1244 break; 1245 } 1246 return i; 1247 } 1248
Indexes created Thu Oct 23 22:10:10 GMT 2025