mvsoc.c revision 1.20
1 /* $NetBSD: mvsoc.c,v 1.20 2015/05/11 05:49:48 hsuenaga Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2013, 2014 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.20 2015/05/11 05:49:48 hsuenaga Exp $"); 30 31 #include "opt_cputypes.h" 32 #include "opt_mvsoc.h" 33 #include "mvxpe.h" 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/errno.h> 39 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pcireg.h> 42 #include <dev/marvell/marvellreg.h> 43 #include <dev/marvell/marvellvar.h> 44 45 #include <arm/marvell/mvsocreg.h> 46 #include <arm/marvell/mvsocvar.h> 47 #include <arm/marvell/orionreg.h> 48 #include <arm/marvell/kirkwoodreg.h> 49 #include <arm/marvell/mv78xx0reg.h> 50 #include <arm/marvell/armadaxpreg.h> 51 52 #include <uvm/uvm.h> 53 54 #include "locators.h" 55 56 #ifdef MVSOC_CONSOLE_EARLY 57 #include <dev/ic/ns16550reg.h> 58 #include <dev/ic/comreg.h> 59 #include <dev/cons.h> 60 #endif 61 62 static int mvsoc_match(device_t, struct cfdata *, void *); 63 static void mvsoc_attach(device_t, device_t, void *); 64 65 static int mvsoc_print(void *, const char *); 66 static int mvsoc_search(device_t, cfdata_t, const int *, void *); 67 68 static int mvsoc_target_ddr(uint32_t, uint32_t *, uint32_t *); 69 static int mvsoc_target_ddr3(uint32_t, uint32_t *, uint32_t *); 70 static int mvsoc_target_peripheral(uint32_t, uint32_t, uint32_t *, uint32_t *); 71 72 uint32_t mvPclk, mvSysclk, mvTclk = 0; 73 int nwindow = 0, nremap = 0; 74 static vaddr_t regbase = 0xffffffff, dsc_base, pex_base; 75 vaddr_t mlmb_base; 76 77 void (*mvsoc_intr_init)(void); 78 int (*mvsoc_clkgating)(struct marvell_attach_args *); 79 80 81 #ifdef MVSOC_CONSOLE_EARLY 82 static vaddr_t com_base; 83 84 static inline uint32_t 85 uart_read(bus_size_t o) 86 { 87 return *(volatile uint32_t *)(com_base + (o << 2)); 88 } 89 90 static inline void 91 uart_write(bus_size_t o, uint32_t v) 92 { 93 *(volatile uint32_t *)(com_base + (o << 2)) = v; 94 } 95 96 static int 97 mvsoc_cngetc(dev_t dv) 98 { 99 if ((uart_read(com_lsr) & LSR_RXRDY) == 0) 100 return -1; 101 102 return uart_read(com_data) & 0xff; 103 } 104 105 static void 106 mvsoc_cnputc(dev_t dv, int c) 107 { 108 int timo = 150000; 109 110 while ((uart_read(com_lsr) & LSR_TXRDY) == 0 && --timo > 0) 111 ; 112 113 uart_write(com_data, c); 114 115 timo = 150000; 116 while ((uart_read(com_lsr) & LSR_TSRE) == 0 && --timo > 0) 117 ; 118 } 119 120 static struct consdev mvsoc_earlycons = { 121 .cn_putc = mvsoc_cnputc, 122 .cn_getc = mvsoc_cngetc, 123 .cn_pollc = nullcnpollc, 124 }; 125 #endif 126 127 128 /* attributes */ 129 static struct { 130 int tag; 131 uint32_t attr; 132 uint32_t target; 133 } mvsoc_tags[] = { 134 { MARVELL_TAG_SDRAM_CS0, 135 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 136 { MARVELL_TAG_SDRAM_CS1, 137 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 138 { MARVELL_TAG_SDRAM_CS2, 139 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 140 { MARVELL_TAG_SDRAM_CS3, 141 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 142 143 { MARVELL_TAG_DDR3_CS0, 144 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 145 { MARVELL_TAG_DDR3_CS1, 146 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 147 { MARVELL_TAG_DDR3_CS2, 148 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 149 { MARVELL_TAG_DDR3_CS3, 150 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 151 152 #if defined(ORION) 153 { ORION_TAG_DEVICE_CS0, 154 ORION_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 155 { ORION_TAG_DEVICE_CS1, 156 ORION_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 157 { ORION_TAG_DEVICE_CS2, 158 ORION_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 159 { ORION_TAG_DEVICE_BOOTCS, 160 ORION_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 161 { ORION_TAG_FLASH_CS, 162 ORION_ATTR_FLASH_CS, MVSOC_UNITID_DEVBUS }, 163 { ORION_TAG_PEX0_MEM, 164 ORION_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 165 { ORION_TAG_PEX0_IO, 166 ORION_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 167 { ORION_TAG_PEX1_MEM, 168 ORION_ATTR_PEX_MEM, ORION_UNITID_PEX1 }, 169 { ORION_TAG_PEX1_IO, 170 ORION_ATTR_PEX_IO, ORION_UNITID_PEX1 }, 171 { ORION_TAG_PCI_MEM, 172 ORION_ATTR_PCI_MEM, ORION_UNITID_PCI }, 173 { ORION_TAG_PCI_IO, 174 ORION_ATTR_PCI_IO, ORION_UNITID_PCI }, 175 { ORION_TAG_CRYPT, 176 ORION_ATTR_CRYPT, ORION_UNITID_CRYPT }, 177 #endif 178 179 #if defined(KIRKWOOD) 180 { KIRKWOOD_TAG_NAND, 181 KIRKWOOD_ATTR_NAND, MVSOC_UNITID_DEVBUS }, 182 { KIRKWOOD_TAG_SPI, 183 KIRKWOOD_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 184 { KIRKWOOD_TAG_BOOTROM, 185 KIRKWOOD_ATTR_BOOTROM, MVSOC_UNITID_DEVBUS }, 186 { KIRKWOOD_TAG_PEX_MEM, 187 KIRKWOOD_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 188 { KIRKWOOD_TAG_PEX_IO, 189 KIRKWOOD_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 190 { KIRKWOOD_TAG_PEX1_MEM, 191 KIRKWOOD_ATTR_PEX1_MEM, MVSOC_UNITID_PEX }, 192 { KIRKWOOD_TAG_PEX1_IO, 193 KIRKWOOD_ATTR_PEX1_IO, MVSOC_UNITID_PEX }, 194 { KIRKWOOD_TAG_CRYPT, 195 KIRKWOOD_ATTR_CRYPT, KIRKWOOD_UNITID_CRYPT }, 196 #endif 197 198 #if defined(MV78XX0) 199 { MV78XX0_TAG_DEVICE_CS0, 200 MV78XX0_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 201 { MV78XX0_TAG_DEVICE_CS1, 202 MV78XX0_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 203 { MV78XX0_TAG_DEVICE_CS2, 204 MV78XX0_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 205 { MV78XX0_TAG_DEVICE_CS3, 206 MV78XX0_ATTR_DEVICE_CS3, MVSOC_UNITID_DEVBUS }, 207 { MV78XX0_TAG_DEVICE_BOOTCS, 208 MV78XX0_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 209 { MV78XX0_TAG_SPI, 210 MV78XX0_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 211 { MV78XX0_TAG_PEX0_MEM, 212 MV78XX0_ATTR_PEX_0_MEM, MVSOC_UNITID_PEX }, 213 { MV78XX0_TAG_PEX01_MEM, 214 MV78XX0_ATTR_PEX_1_MEM, MVSOC_UNITID_PEX }, 215 { MV78XX0_TAG_PEX02_MEM, 216 MV78XX0_ATTR_PEX_2_MEM, MVSOC_UNITID_PEX }, 217 { MV78XX0_TAG_PEX03_MEM, 218 MV78XX0_ATTR_PEX_3_MEM, MVSOC_UNITID_PEX }, 219 { MV78XX0_TAG_PEX0_IO, 220 MV78XX0_ATTR_PEX_0_IO, MVSOC_UNITID_PEX }, 221 { MV78XX0_TAG_PEX01_IO, 222 MV78XX0_ATTR_PEX_1_IO, MVSOC_UNITID_PEX }, 223 { MV78XX0_TAG_PEX02_IO, 224 MV78XX0_ATTR_PEX_2_IO, MVSOC_UNITID_PEX }, 225 { MV78XX0_TAG_PEX03_IO, 226 MV78XX0_ATTR_PEX_3_IO, MVSOC_UNITID_PEX }, 227 { MV78XX0_TAG_PEX1_MEM, 228 MV78XX0_ATTR_PEX_0_MEM, MV78XX0_UNITID_PEX1 }, 229 { MV78XX0_TAG_PEX11_MEM, 230 MV78XX0_ATTR_PEX_1_MEM, MV78XX0_UNITID_PEX1 }, 231 { MV78XX0_TAG_PEX12_MEM, 232 MV78XX0_ATTR_PEX_2_MEM, MV78XX0_UNITID_PEX1 }, 233 { MV78XX0_TAG_PEX13_MEM, 234 MV78XX0_ATTR_PEX_3_MEM, MV78XX0_UNITID_PEX1 }, 235 { MV78XX0_TAG_PEX1_IO, 236 MV78XX0_ATTR_PEX_0_IO, MV78XX0_UNITID_PEX1 }, 237 { MV78XX0_TAG_PEX11_IO, 238 MV78XX0_ATTR_PEX_1_IO, MV78XX0_UNITID_PEX1 }, 239 { MV78XX0_TAG_PEX12_IO, 240 MV78XX0_ATTR_PEX_2_IO, MV78XX0_UNITID_PEX1 }, 241 { MV78XX0_TAG_PEX13_IO, 242 MV78XX0_ATTR_PEX_3_IO, MV78XX0_UNITID_PEX1 }, 243 { MV78XX0_TAG_CRYPT, 244 MV78XX0_ATTR_CRYPT, MV78XX0_UNITID_CRYPT }, 245 #endif 246 247 #if defined(ARMADAXP) 248 { ARMADAXP_TAG_PEX00_MEM, 249 ARMADAXP_ATTR_PEXx0_MEM, ARMADAXP_UNITID_PEX0 }, 250 { ARMADAXP_TAG_PEX00_IO, 251 ARMADAXP_ATTR_PEXx0_IO, ARMADAXP_UNITID_PEX0 }, 252 { ARMADAXP_TAG_PEX01_MEM, 253 ARMADAXP_ATTR_PEXx1_MEM, ARMADAXP_UNITID_PEX0 }, 254 { ARMADAXP_TAG_PEX01_IO, 255 ARMADAXP_ATTR_PEXx1_IO, ARMADAXP_UNITID_PEX0 }, 256 { ARMADAXP_TAG_PEX02_MEM, 257 ARMADAXP_ATTR_PEXx2_MEM, ARMADAXP_UNITID_PEX0 }, 258 { ARMADAXP_TAG_PEX02_IO, 259 ARMADAXP_ATTR_PEXx2_IO, ARMADAXP_UNITID_PEX0 }, 260 { ARMADAXP_TAG_PEX03_MEM, 261 ARMADAXP_ATTR_PEXx3_MEM, ARMADAXP_UNITID_PEX0 }, 262 { ARMADAXP_TAG_PEX03_IO, 263 ARMADAXP_ATTR_PEXx3_IO, ARMADAXP_UNITID_PEX0 }, 264 { ARMADAXP_TAG_PEX2_MEM, 265 ARMADAXP_ATTR_PEX2_MEM, ARMADAXP_UNITID_PEX2 }, 266 { ARMADAXP_TAG_PEX2_IO, 267 ARMADAXP_ATTR_PEX2_IO, ARMADAXP_UNITID_PEX2 }, 268 { ARMADAXP_TAG_PEX3_MEM, 269 ARMADAXP_ATTR_PEX3_MEM, ARMADAXP_UNITID_PEX3 }, 270 { ARMADAXP_TAG_PEX3_IO, 271 ARMADAXP_ATTR_PEX3_IO, ARMADAXP_UNITID_PEX3 }, 272 #endif 273 }; 274 275 #if defined(ORION) 276 #define ORION_1(m) MARVELL_ORION_1_ ## m 277 #define ORION_2(m) MARVELL_ORION_2_ ## m 278 #endif 279 #if defined(KIRKWOOD) 280 #undef KIRKWOOD 281 #define KIRKWOOD(m) MARVELL_KIRKWOOD_ ## m 282 #endif 283 #if defined(MV78XX0) 284 #undef MV78XX0 285 #define MV78XX0(m) MARVELL_MV78XX0_ ## m 286 #endif 287 #if defined(ARMADAXP) 288 #undef ARMADAXP 289 #define ARMADAXP(m) MARVELL_ARMADAXP_ ## m 290 #define ARMADA370(m) MARVELL_ARMADA370_ ## m 291 #endif 292 static struct { 293 uint16_t model; 294 uint8_t rev; 295 const char *modelstr; 296 const char *revstr; 297 const char *typestr; 298 } nametbl[] = { 299 #if defined(ORION) 300 { ORION_1(88F1181), 0, "MV88F1181", NULL, "Orion1" }, 301 { ORION_1(88F5082), 2, "MV88F5082", "A2", "Orion1" }, 302 { ORION_1(88F5180N), 3, "MV88F5180N","B1", "Orion1" }, 303 { ORION_1(88F5181), 0, "MV88F5181", "A0", "Orion1" }, 304 { ORION_1(88F5181), 1, "MV88F5181", "A1", "Orion1" }, 305 { ORION_1(88F5181), 2, "MV88F5181", "B0", "Orion1" }, 306 { ORION_1(88F5181), 3, "MV88F5181", "B1", "Orion1" }, 307 { ORION_1(88F5181), 8, "MV88F5181L","A0", "Orion1" }, 308 { ORION_1(88F5181), 9, "MV88F5181L","A1", "Orion1" }, 309 { ORION_1(88F5182), 0, "MV88F5182", "A0", "Orion1" }, 310 { ORION_1(88F5182), 1, "MV88F5182", "A1", "Orion1" }, 311 { ORION_1(88F5182), 2, "MV88F5182", "A2", "Orion1" }, 312 { ORION_1(88F6082), 0, "MV88F6082", "A0", "Orion1" }, 313 { ORION_1(88F6082), 1, "MV88F6082", "A1", "Orion1" }, 314 { ORION_1(88F6183), 0, "MV88F6183", "A0", "Orion1" }, 315 { ORION_1(88F6183), 1, "MV88F6183", "Z0", "Orion1" }, 316 { ORION_1(88W8660), 0, "MV88W8660", "A0", "Orion1" }, 317 { ORION_1(88W8660), 1, "MV88W8660", "A1", "Orion1" }, 318 319 { ORION_2(88F1281), 0, "MV88F1281", "A0", "Orion2" }, 320 { ORION_2(88F5281), 0, "MV88F5281", "A0", "Orion2" }, 321 { ORION_2(88F5281), 1, "MV88F5281", "B0", "Orion2" }, 322 { ORION_2(88F5281), 2, "MV88F5281", "C0", "Orion2" }, 323 { ORION_2(88F5281), 3, "MV88F5281", "C1", "Orion2" }, 324 { ORION_2(88F5281), 4, "MV88F5281", "D0", "Orion2" }, 325 #endif 326 327 #if defined(KIRKWOOD) 328 { KIRKWOOD(88F6180), 2, "88F6180", "A0", "Kirkwood" }, 329 { KIRKWOOD(88F6180), 3, "88F6180", "A1", "Kirkwood" }, 330 { KIRKWOOD(88F6192), 0, "88F619x", "Z0", "Kirkwood" }, 331 { KIRKWOOD(88F6192), 2, "88F619x", "A0", "Kirkwood" }, 332 { KIRKWOOD(88F6192), 3, "88F619x", "A1", "Kirkwood" }, 333 { KIRKWOOD(88F6281), 0, "88F6281", "Z0", "Kirkwood" }, 334 { KIRKWOOD(88F6281), 2, "88F6281", "A0", "Kirkwood" }, 335 { KIRKWOOD(88F6281), 3, "88F6281", "A1", "Kirkwood" }, 336 { KIRKWOOD(88F6282), 0, "88F6282", "A0", "Kirkwood" }, 337 { KIRKWOOD(88F6282), 1, "88F6282", "A1", "Kirkwood" }, 338 #endif 339 340 #if defined(MV78XX0) 341 { MV78XX0(MV78100), 1, "MV78100", "A0", "Discovery Innovation" }, 342 { MV78XX0(MV78100), 2, "MV78100", "A1", "Discovery Innovation" }, 343 { MV78XX0(MV78200), 1, "MV78200", "A0", "Discovery Innovation" }, 344 #endif 345 346 #if defined(ARMADAXP) 347 { ARMADAXP(MV78130), 1, "MV78130", "A0", "Armada XP" }, 348 { ARMADAXP(MV78160), 1, "MV78160", "A0", "Armada XP" }, 349 { ARMADAXP(MV78230), 1, "MV78260", "A0", "Armada XP" }, 350 { ARMADAXP(MV78260), 1, "MV78260", "A0", "Armada XP" }, 351 { ARMADAXP(MV78260), 2, "MV78260", "B0", "Armada XP" }, 352 { ARMADAXP(MV78460), 1, "MV78460", "A0", "Armada XP" }, 353 { ARMADAXP(MV78460), 2, "MV78460", "B0", "Armada XP" }, 354 355 { ARMADA370(MV6707), 0, "MV6707", "A0", "Armada 370" }, 356 { ARMADA370(MV6707), 1, "MV6707", "A1", "Armada 370" }, 357 { ARMADA370(MV6710), 0, "MV6710", "A0", "Armada 370" }, 358 { ARMADA370(MV6710), 1, "MV6710", "A1", "Armada 370" }, 359 { ARMADA370(MV6W11), 0, "MV6W11", "A0", "Armada 370" }, 360 { ARMADA370(MV6W11), 1, "MV6W11", "A1", "Armada 370" }, 361 #endif 362 }; 363 364 enum marvell_tags ddr_tags[] = { 365 MARVELL_TAG_SDRAM_CS0, 366 MARVELL_TAG_SDRAM_CS1, 367 MARVELL_TAG_SDRAM_CS2, 368 MARVELL_TAG_SDRAM_CS3, 369 370 MARVELL_TAG_UNDEFINED 371 }; 372 enum marvell_tags ddr3_tags[] = { 373 MARVELL_TAG_DDR3_CS0, 374 MARVELL_TAG_DDR3_CS1, 375 MARVELL_TAG_DDR3_CS2, 376 MARVELL_TAG_DDR3_CS3, 377 378 MARVELL_TAG_UNDEFINED 379 }; 380 static struct { 381 uint16_t model; 382 uint8_t rev; 383 enum marvell_tags *tags; 384 } tagstbl[] = { 385 #if defined(ORION) 386 { ORION_1(88F1181), 0, ddr_tags }, 387 { ORION_1(88F5082), 2, ddr_tags }, 388 { ORION_1(88F5180N), 3, ddr_tags }, 389 { ORION_1(88F5181), 0, ddr_tags }, 390 { ORION_1(88F5181), 1, ddr_tags }, 391 { ORION_1(88F5181), 2, ddr_tags }, 392 { ORION_1(88F5181), 3, ddr_tags }, 393 { ORION_1(88F5181), 8, ddr_tags }, 394 { ORION_1(88F5181), 9, ddr_tags }, 395 { ORION_1(88F5182), 0, ddr_tags }, 396 { ORION_1(88F5182), 1, ddr_tags }, 397 { ORION_1(88F5182), 2, ddr_tags }, 398 { ORION_1(88F6082), 0, ddr_tags }, 399 { ORION_1(88F6082), 1, ddr_tags }, 400 { ORION_1(88F6183), 0, ddr_tags }, 401 { ORION_1(88F6183), 1, ddr_tags }, 402 { ORION_1(88W8660), 0, ddr_tags }, 403 { ORION_1(88W8660), 1, ddr_tags }, 404 405 { ORION_2(88F1281), 0, ddr_tags }, 406 { ORION_2(88F5281), 0, ddr_tags }, 407 { ORION_2(88F5281), 1, ddr_tags }, 408 { ORION_2(88F5281), 2, ddr_tags }, 409 { ORION_2(88F5281), 3, ddr_tags }, 410 { ORION_2(88F5281), 4, ddr_tags }, 411 #endif 412 413 #if defined(KIRKWOOD) 414 { KIRKWOOD(88F6180), 2, ddr_tags }, 415 { KIRKWOOD(88F6180), 3, ddr_tags }, 416 { KIRKWOOD(88F6192), 0, ddr_tags }, 417 { KIRKWOOD(88F6192), 2, ddr_tags }, 418 { KIRKWOOD(88F6192), 3, ddr_tags }, 419 { KIRKWOOD(88F6281), 0, ddr_tags }, 420 { KIRKWOOD(88F6281), 2, ddr_tags }, 421 { KIRKWOOD(88F6281), 3, ddr_tags }, 422 { KIRKWOOD(88F6282), 0, ddr_tags }, 423 { KIRKWOOD(88F6282), 1, ddr_tags }, 424 #endif 425 426 #if defined(MV78XX0) 427 { MV78XX0(MV78100), 1, ddr_tags }, 428 { MV78XX0(MV78100), 2, ddr_tags }, 429 { MV78XX0(MV78200), 1, ddr_tags }, 430 #endif 431 432 #if defined(ARMADAXP) 433 { ARMADAXP(MV78130), 1, ddr3_tags }, 434 { ARMADAXP(MV78160), 1, ddr3_tags }, 435 { ARMADAXP(MV78230), 1, ddr3_tags }, 436 { ARMADAXP(MV78260), 1, ddr3_tags }, 437 { ARMADAXP(MV78260), 2, ddr3_tags }, 438 { ARMADAXP(MV78460), 1, ddr3_tags }, 439 { ARMADAXP(MV78460), 2, ddr3_tags }, 440 441 { ARMADA370(MV6707), 0, ddr3_tags }, 442 { ARMADA370(MV6707), 1, ddr3_tags }, 443 { ARMADA370(MV6710), 0, ddr3_tags }, 444 { ARMADA370(MV6710), 1, ddr3_tags }, 445 { ARMADA370(MV6W11), 0, ddr3_tags }, 446 { ARMADA370(MV6W11), 1, ddr3_tags }, 447 #endif 448 }; 449 450 451 #define OFFSET_DEFAULT MVA_OFFSET_DEFAULT 452 #define IRQ_DEFAULT MVA_IRQ_DEFAULT 453 static const struct mvsoc_periph { 454 int model; 455 const char *name; 456 int unit; 457 bus_size_t offset; 458 int irq; 459 } mvsoc_periphs[] = { 460 #if defined(ORION) 461 #define ORION_IRQ_TMR (32 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 462 463 { ORION_1(88F1181), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 464 { ORION_1(88F1181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 465 { ORION_1(88F1181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 466 { ORION_1(88F1181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 467 { ORION_1(88F1181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 468 { ORION_1(88F1181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 469 { ORION_1(88F1181), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 470 471 { ORION_1(88F5082), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 472 { ORION_1(88F5082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 473 { ORION_1(88F5082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 474 { ORION_1(88F5082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 475 { ORION_1(88F5082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 476 { ORION_1(88F5082), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 477 { ORION_1(88F5082), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 478 { ORION_1(88F5082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 479 { ORION_1(88F5082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 480 { ORION_1(88F5082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 481 { ORION_1(88F5082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 482 { ORION_1(88F5082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 483 484 { ORION_1(88F5180N),"mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 485 { ORION_1(88F5180N),"mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 486 { ORION_1(88F5180N),"com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 487 { ORION_1(88F5180N),"com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 488 { ORION_1(88F5180N),"ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 489 { ORION_1(88F5180N),"gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 490 { ORION_1(88F5180N),"gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 491 { ORION_1(88F5180N),"gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 492 { ORION_1(88F5180N),"mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 493 { ORION_1(88F5180N),"mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 494 495 { ORION_1(88F5181), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 496 { ORION_1(88F5181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 497 { ORION_1(88F5181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 498 { ORION_1(88F5181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 499 { ORION_1(88F5181), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 500 { ORION_1(88F5181), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 501 { ORION_1(88F5181), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 502 { ORION_1(88F5181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 503 { ORION_1(88F5181), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 504 { ORION_1(88F5181), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 505 { ORION_1(88F5181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 506 507 { ORION_1(88F5182), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 508 { ORION_1(88F5182), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 509 { ORION_1(88F5182), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 510 { ORION_1(88F5182), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 511 { ORION_1(88F5182), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 512 { ORION_1(88F5182), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 513 { ORION_1(88F5182), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 514 { ORION_1(88F5182), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 515 { ORION_1(88F5182), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 516 { ORION_1(88F5182), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 517 { ORION_1(88F5182), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 518 { ORION_1(88F5182), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 519 520 { ORION_1(88F6082), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 521 { ORION_1(88F6082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 522 { ORION_1(88F6082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 523 { ORION_1(88F6082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 524 { ORION_1(88F6082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 525 { ORION_1(88F6082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 526 { ORION_1(88F6082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 527 { ORION_1(88F6082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 528 { ORION_1(88F6082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 529 { ORION_1(88F6082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 530 531 { ORION_1(88F6183), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 532 { ORION_1(88F6183), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 533 { ORION_1(88F6183), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 534 { ORION_1(88F6183), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 535 536 { ORION_1(88W8660), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 537 { ORION_1(88W8660), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 538 { ORION_1(88W8660), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 539 { ORION_1(88W8660), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 540 { ORION_1(88W8660), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 541 { ORION_1(88W8660), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 542 { ORION_1(88W8660), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 543 { ORION_1(88W8660), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 544 { ORION_1(88W8660), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 545 { ORION_1(88W8660), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 546 547 { ORION_2(88F1281), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 548 { ORION_2(88F1281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 549 { ORION_2(88F1281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 550 { ORION_2(88F1281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 551 { ORION_2(88F1281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 552 { ORION_2(88F1281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 553 { ORION_2(88F1281), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 554 555 { ORION_2(88F5281), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 556 { ORION_2(88F5281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 557 { ORION_2(88F5281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 558 { ORION_2(88F5281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 559 { ORION_2(88F5281), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 560 { ORION_2(88F5281), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 561 { ORION_2(88F5281), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 562 { ORION_2(88F5281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 563 { ORION_2(88F5281), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 564 { ORION_2(88F5281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 565 #endif 566 567 #if defined(KIRKWOOD) 568 #define KIRKWOOD_IRQ_TMR (64 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 569 570 { KIRKWOOD(88F6180),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 571 { KIRKWOOD(88F6180),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 572 { KIRKWOOD(88F6180),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 573 { KIRKWOOD(88F6180),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 574 { KIRKWOOD(88F6180),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 575 { KIRKWOOD(88F6180),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 576 { KIRKWOOD(88F6180),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 577 { KIRKWOOD(88F6180),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 578 { KIRKWOOD(88F6180),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 579 { KIRKWOOD(88F6180),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 580 { KIRKWOOD(88F6180),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 581 { KIRKWOOD(88F6180),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 582 583 { KIRKWOOD(88F6192),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 584 { KIRKWOOD(88F6192),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 585 { KIRKWOOD(88F6192),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 586 { KIRKWOOD(88F6192),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 587 { KIRKWOOD(88F6192),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 588 { KIRKWOOD(88F6192),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 589 { KIRKWOOD(88F6192),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 590 { KIRKWOOD(88F6192),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 591 { KIRKWOOD(88F6192),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 592 { KIRKWOOD(88F6192),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 593 { KIRKWOOD(88F6192),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 594 { KIRKWOOD(88F6192),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 595 { KIRKWOOD(88F6192),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 596 { KIRKWOOD(88F6192),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 597 598 { KIRKWOOD(88F6281),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 599 { KIRKWOOD(88F6281),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 600 { KIRKWOOD(88F6281),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 601 { KIRKWOOD(88F6281),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 602 { KIRKWOOD(88F6281),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 603 { KIRKWOOD(88F6281),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 604 { KIRKWOOD(88F6281),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 605 { KIRKWOOD(88F6281),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 606 { KIRKWOOD(88F6281),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT }, 607 { KIRKWOOD(88F6281),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 608 { KIRKWOOD(88F6281),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 609 { KIRKWOOD(88F6281),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 610 { KIRKWOOD(88F6281),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 611 { KIRKWOOD(88F6281),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 612 613 { KIRKWOOD(88F6282),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 614 { KIRKWOOD(88F6282),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 615 { KIRKWOOD(88F6282),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 616 { KIRKWOOD(88F6282),"mvsocts", 0, KIRKWOOD_TS_BASE, IRQ_DEFAULT }, 617 { KIRKWOOD(88F6282),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 618 { KIRKWOOD(88F6282),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 619 { KIRKWOOD(88F6282),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 620 { KIRKWOOD(88F6282),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 621 { KIRKWOOD(88F6282),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 622 { KIRKWOOD(88F6282),"gttwsi", 1, KIRKWOOD_TWSI1_BASE,KIRKWOOD_IRQ_TWSI1 }, 623 { KIRKWOOD(88F6282),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 624 { KIRKWOOD(88F6282),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 625 { KIRKWOOD(88F6282),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 626 { KIRKWOOD(88F6282),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 627 { KIRKWOOD(88F6282),"mvpex", 1, KIRKWOOD_PEX1_BASE,KIRKWOOD_IRQ_PEX1INT }, 628 { KIRKWOOD(88F6282),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 629 { KIRKWOOD(88F6282),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 630 #endif 631 632 #if defined(MV78XX0) 633 { MV78XX0(MV78100), "mvsoctmr",0, MVSOC_TMR_BASE, MV78XX0_IRQ_TIMER0 }, 634 { MV78XX0(MV78100), "mvsocgpp",0, MVSOC_GPP_BASE, MV78XX0_IRQ_GPIO0_7 }, 635 { MV78XX0(MV78100), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0 }, 636 { MV78XX0(MV78100), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1 }, 637 { MV78XX0(MV78100), "com", 2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 }, 638 { MV78XX0(MV78100), "com", 3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 }, 639 { MV78XX0(MV78100), "gttwsi", 0, MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI0 }, 640 { MV78XX0(MV78100), "gttwsi", 1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 }, 641 { MV78XX0(MV78100), "mvgbec", 0, MV78XX0_GBE0_BASE,IRQ_DEFAULT }, 642 { MV78XX0(MV78100), "mvgbec", 1, MV78XX0_GBE1_BASE,IRQ_DEFAULT }, 643 { MV78XX0(MV78100), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA }, 644 645 { MV78XX0(MV78200), "mvsoctmr",0, MVSOC_TMR_BASE, MV78XX0_IRQ_TIMER0 }, 646 { MV78XX0(MV78200), "mvsocgpp",0, MVSOC_GPP_BASE, MV78XX0_IRQ_GPIO0_7 }, 647 { MV78XX0(MV78200), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0 }, 648 { MV78XX0(MV78200), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1 }, 649 { MV78XX0(MV78200), "com", 2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 }, 650 { MV78XX0(MV78200), "com", 3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 }, 651 { MV78XX0(MV78200), "gttwsi", 0, MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI0 }, 652 { MV78XX0(MV78200), "gttwsi", 1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 }, 653 { MV78XX0(MV78200), "mvgbec", 0, MV78XX0_GBE0_BASE,IRQ_DEFAULT }, 654 { MV78XX0(MV78200), "mvgbec", 1, MV78XX0_GBE1_BASE,IRQ_DEFAULT }, 655 { MV78XX0(MV78200), "mvgbec", 2, MV78XX0_GBE2_BASE,IRQ_DEFAULT }, 656 { MV78XX0(MV78200), "mvgbec", 3, MV78XX0_GBE3_BASE,IRQ_DEFAULT }, 657 { MV78XX0(MV78200), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA }, 658 #endif 659 660 #if defined(ARMADAXP) 661 { ARMADAXP(MV78130), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 662 { ARMADAXP(MV78130), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 663 { ARMADAXP(MV78130), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 664 { ARMADAXP(MV78130), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 665 { ARMADAXP(MV78130), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 666 { ARMADAXP(MV78130), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 667 { ARMADAXP(MV78130), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 668 { ARMADAXP(MV78130), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 669 { ARMADAXP(MV78130), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 670 { ARMADAXP(MV78130), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 671 { ARMADAXP(MV78130), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 672 { ARMADAXP(MV78130), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 673 { ARMADAXP(MV78130), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 674 { ARMADAXP(MV78130), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 675 { ARMADAXP(MV78130), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 676 { ARMADAXP(MV78130), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 677 { ARMADAXP(MV78130), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 678 { ARMADAXP(MV78130), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 679 { ARMADAXP(MV78130), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 680 { ARMADAXP(MV78130), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 681 { ARMADAXP(MV78130), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 682 #if NMVXPE > 0 683 { ARMADAXP(MV78130), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 684 { ARMADAXP(MV78130), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 685 #else 686 { ARMADAXP(MV78130), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 687 { ARMADAXP(MV78130), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 688 #endif 689 { ARMADAXP(MV78130), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 690 { ARMADAXP(MV78130), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 691 692 { ARMADAXP(MV78160), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 693 { ARMADAXP(MV78160), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 694 { ARMADAXP(MV78160), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 695 { ARMADAXP(MV78160), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 696 { ARMADAXP(MV78160), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 697 { ARMADAXP(MV78160), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 698 { ARMADAXP(MV78160), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 699 { ARMADAXP(MV78160), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 700 { ARMADAXP(MV78160), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 701 { ARMADAXP(MV78160), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 702 { ARMADAXP(MV78160), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 703 { ARMADAXP(MV78160), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 704 { ARMADAXP(MV78160), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 705 { ARMADAXP(MV78160), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 706 { ARMADAXP(MV78160), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 707 { ARMADAXP(MV78160), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 708 { ARMADAXP(MV78160), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 709 { ARMADAXP(MV78160), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 710 { ARMADAXP(MV78160), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 711 { ARMADAXP(MV78160), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 712 { ARMADAXP(MV78160), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 713 #if NMVXPE > 0 714 { ARMADAXP(MV78160), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 715 { ARMADAXP(MV78160), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 716 { ARMADAXP(MV78160), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 717 { ARMADAXP(MV78160), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX }, 718 #else 719 { ARMADAXP(MV78160), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 720 { ARMADAXP(MV78160), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 721 { ARMADAXP(MV78160), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 722 { ARMADAXP(MV78160), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 723 #endif 724 { ARMADAXP(MV78160), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 725 { ARMADAXP(MV78160), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 726 727 { ARMADAXP(MV78230), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 728 { ARMADAXP(MV78230), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 729 { ARMADAXP(MV78230), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 730 { ARMADAXP(MV78230), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 731 { ARMADAXP(MV78230), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 732 { ARMADAXP(MV78230), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 733 { ARMADAXP(MV78230), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 734 { ARMADAXP(MV78230), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 735 { ARMADAXP(MV78230), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 736 { ARMADAXP(MV78230), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 737 { ARMADAXP(MV78230), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 738 { ARMADAXP(MV78230), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 739 { ARMADAXP(MV78230), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 740 { ARMADAXP(MV78230), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 741 { ARMADAXP(MV78230), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 742 { ARMADAXP(MV78230), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 743 { ARMADAXP(MV78230), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 744 { ARMADAXP(MV78230), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 745 { ARMADAXP(MV78230), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 746 { ARMADAXP(MV78230), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 747 { ARMADAXP(MV78230), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 748 #if NMVXPE > 0 749 { ARMADAXP(MV78230), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 750 { ARMADAXP(MV78230), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 751 { ARMADAXP(MV78230), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 752 #else 753 { ARMADAXP(MV78230), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 754 { ARMADAXP(MV78230), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 755 { ARMADAXP(MV78230), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 756 #endif 757 { ARMADAXP(MV78230), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 758 { ARMADAXP(MV78230), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 759 760 { ARMADAXP(MV78260), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 761 { ARMADAXP(MV78260), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 762 { ARMADAXP(MV78260), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 763 { ARMADAXP(MV78260), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 764 { ARMADAXP(MV78260), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 765 { ARMADAXP(MV78260), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 766 { ARMADAXP(MV78260), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 767 { ARMADAXP(MV78260), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 768 { ARMADAXP(MV78260), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 769 { ARMADAXP(MV78260), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 770 { ARMADAXP(MV78260), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 771 { ARMADAXP(MV78260), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 772 { ARMADAXP(MV78260), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 773 { ARMADAXP(MV78260), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 774 { ARMADAXP(MV78260), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 775 { ARMADAXP(MV78260), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 776 { ARMADAXP(MV78260), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 777 { ARMADAXP(MV78260), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 778 { ARMADAXP(MV78260), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 779 { ARMADAXP(MV78260), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 780 { ARMADAXP(MV78260), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 781 #if NMVXPE > 0 782 { ARMADAXP(MV78260), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 783 { ARMADAXP(MV78260), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 784 { ARMADAXP(MV78260), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 785 { ARMADAXP(MV78260), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX }, 786 #else 787 { ARMADAXP(MV78260), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 788 { ARMADAXP(MV78260), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 789 { ARMADAXP(MV78260), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 790 { ARMADAXP(MV78260), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 791 #endif 792 { ARMADAXP(MV78260), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 793 { ARMADAXP(MV78260), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 794 795 { ARMADAXP(MV78460), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 796 { ARMADAXP(MV78460), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 797 { ARMADAXP(MV78460), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 798 { ARMADAXP(MV78460), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 799 { ARMADAXP(MV78460), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 800 { ARMADAXP(MV78460), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 801 { ARMADAXP(MV78460), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 802 { ARMADAXP(MV78460), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 803 { ARMADAXP(MV78460), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 804 { ARMADAXP(MV78460), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 805 { ARMADAXP(MV78460), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 806 { ARMADAXP(MV78460), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 807 { ARMADAXP(MV78460), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 808 { ARMADAXP(MV78460), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 809 { ARMADAXP(MV78460), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 810 { ARMADAXP(MV78460), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 811 { ARMADAXP(MV78460), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 812 { ARMADAXP(MV78460), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 813 { ARMADAXP(MV78460), "mvpex", 5, ARMADAXP_PEX3_BASE,ARMADAXP_IRQ_PEX3 }, 814 { ARMADAXP(MV78460), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 815 { ARMADAXP(MV78460), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 816 { ARMADAXP(MV78460), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 817 #if NMVXPE > 0 818 { ARMADAXP(MV78460), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 819 { ARMADAXP(MV78460), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 820 { ARMADAXP(MV78460), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 821 { ARMADAXP(MV78460), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX }, 822 #else 823 { ARMADAXP(MV78460), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 824 { ARMADAXP(MV78460), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 825 { ARMADAXP(MV78460), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 826 { ARMADAXP(MV78460), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 827 #endif 828 { ARMADAXP(MV78460), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 829 { ARMADAXP(MV78460), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 830 831 { ARMADA370(MV6710), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 832 { ARMADA370(MV6710), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 833 { ARMADA370(MV6710), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 834 { ARMADA370(MV6710), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 835 { ARMADA370(MV6710), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 836 { ARMADA370(MV6710), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 837 { ARMADA370(MV6710), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 838 { ARMADA370(MV6710), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 839 { ARMADA370(MV6710), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 840 { ARMADA370(MV6710), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 841 { ARMADA370(MV6710), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 842 { ARMADA370(MV6710), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 843 { ARMADA370(MV6710), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 844 { ARMADA370(MV6710), "mvspi", 1, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 845 { ARMADA370(MV6710), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 846 #if NMVXPE > 0 847 { ARMADA370(MV6710), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 848 { ARMADA370(MV6710), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 849 #else 850 { ARMADA370(MV6710), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 851 { ARMADA370(MV6710), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 852 #endif 853 { ARMADA370(MV6710), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 854 #endif 855 }; 856 857 858 CFATTACH_DECL_NEW(mvsoc, sizeof(struct mvsoc_softc), 859 mvsoc_match, mvsoc_attach, NULL, NULL); 860 861 /* ARGSUSED */ 862 static int 863 mvsoc_match(device_t parent, struct cfdata *match, void *aux) 864 { 865 866 return 1; 867 } 868 869 /* ARGSUSED */ 870 static void 871 mvsoc_attach(device_t parent, device_t self, void *aux) 872 { 873 struct mvsoc_softc *sc = device_private(self); 874 struct marvell_attach_args mva; 875 enum marvell_tags *tags; 876 uint16_t model; 877 uint8_t rev; 878 int i; 879 880 sc->sc_dev = self; 881 sc->sc_iot = &mvsoc_bs_tag; 882 sc->sc_addr = vtophys(regbase); 883 sc->sc_dmat = &mvsoc_bus_dma_tag; 884 if (bus_space_map(sc->sc_iot, sc->sc_addr, 0x100000, 0, &sc->sc_ioh) != 885 0) { 886 aprint_error_dev(self, "can't map registers\n"); 887 return; 888 } 889 890 model = mvsoc_model(); 891 rev = mvsoc_rev(); 892 for (i = 0; i < __arraycount(nametbl); i++) 893 if (nametbl[i].model == model && nametbl[i].rev == rev) 894 break; 895 if (i >= __arraycount(nametbl)) 896 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 897 898 aprint_normal(": Marvell %s %s%s %s\n", 899 nametbl[i].modelstr, 900 nametbl[i].revstr != NULL ? "Rev. " : "", 901 nametbl[i].revstr != NULL ? nametbl[i].revstr : "", 902 nametbl[i].typestr); 903 aprint_normal("%s: CPU Clock %d.%03d MHz" 904 " SysClock %d.%03d MHz TClock %d.%03d MHz\n", 905 device_xname(self), 906 mvPclk / 1000000, (mvPclk / 1000) % 1000, 907 mvSysclk / 1000000, (mvSysclk / 1000) % 1000, 908 mvTclk / 1000000, (mvTclk / 1000) % 1000); 909 aprint_naive("\n"); 910 911 mvsoc_intr_init(); 912 913 for (i = 0; i < __arraycount(tagstbl); i++) 914 if (tagstbl[i].model == model && tagstbl[i].rev == rev) 915 break; 916 if (i >= __arraycount(tagstbl)) 917 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 918 tags = tagstbl[i].tags; 919 920 for (i = 0; i < __arraycount(mvsoc_periphs); i++) { 921 if (mvsoc_periphs[i].model != model) 922 continue; 923 924 mva.mva_name = mvsoc_periphs[i].name; 925 mva.mva_model = model; 926 mva.mva_revision = rev; 927 mva.mva_iot = sc->sc_iot; 928 mva.mva_ioh = sc->sc_ioh; 929 mva.mva_unit = mvsoc_periphs[i].unit; 930 mva.mva_addr = sc->sc_addr; 931 mva.mva_offset = mvsoc_periphs[i].offset; 932 mva.mva_size = 0; 933 mva.mva_dmat = sc->sc_dmat; 934 mva.mva_irq = mvsoc_periphs[i].irq; 935 mva.mva_tags = tags; 936 937 /* Skip clock disabled devices */ 938 if (mvsoc_clkgating != NULL && mvsoc_clkgating(&mva)) { 939 aprint_normal_dev(self, "%s%d clock disabled\n", 940 mvsoc_periphs[i].name, mvsoc_periphs[i].unit); 941 continue; 942 } 943 944 config_found_sm_loc(sc->sc_dev, "mvsoc", NULL, &mva, 945 mvsoc_print, mvsoc_search); 946 } 947 } 948 949 static int 950 mvsoc_print(void *aux, const char *pnp) 951 { 952 struct marvell_attach_args *mva = aux; 953 954 if (pnp) 955 aprint_normal("%s at %s unit %d", 956 mva->mva_name, pnp, mva->mva_unit); 957 else { 958 if (mva->mva_unit != MVA_UNIT_DEFAULT) 959 aprint_normal(" unit %d", mva->mva_unit); 960 if (mva->mva_offset != MVA_OFFSET_DEFAULT) { 961 aprint_normal(" offset 0x%04lx", mva->mva_offset); 962 if (mva->mva_size > 0) 963 aprint_normal("-0x%04lx", 964 mva->mva_offset + mva->mva_size - 1); 965 } 966 if (mva->mva_irq != MVA_IRQ_DEFAULT) 967 aprint_normal(" irq %d", mva->mva_irq); 968 } 969 970 return UNCONF; 971 } 972 973 /* ARGSUSED */ 974 static int 975 mvsoc_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 976 { 977 978 return config_match(parent, cf, aux); 979 } 980 981 /* ARGSUSED */ 982 int 983 marvell_winparams_by_tag(device_t dev, int tag, int *target, int *attribute, 984 uint64_t *base, uint32_t *size) 985 { 986 uint32_t base32; 987 int rv; 988 989 rv = mvsoc_target(tag, target, attribute, &base32, size); 990 *base = base32; 991 if (rv == -1) 992 return -1; 993 return 0; 994 } 995 996 997 /* 998 * These functions is called before bus_space is initialized. 999 */ 1000 1001 void 1002 mvsoc_bootstrap(bus_addr_t iobase) 1003 { 1004 1005 regbase = iobase; 1006 dsc_base = iobase + MVSOC_DSC_BASE; 1007 mlmb_base = iobase + MVSOC_MLMB_BASE; 1008 pex_base = iobase + MVSOC_PEX_BASE; 1009 #ifdef MVSOC_CONSOLE_EARLY 1010 com_base = iobase + MVSOC_COM0_BASE; 1011 cn_tab = &mvsoc_earlycons; 1012 printf("Hello\n"); 1013 #endif 1014 } 1015 1016 /* 1017 * We can read register of PCI configurations from (MVSOC_PEX_BASE + 0). 1018 */ 1019 uint16_t 1020 mvsoc_model(void) 1021 { 1022 /* 1023 * We read product-id from vendor/device register of PCI-Express. 1024 */ 1025 uint32_t reg; 1026 uint16_t model; 1027 1028 KASSERT(regbase != 0xffffffff); 1029 1030 reg = *(volatile uint32_t *)(pex_base + PCI_ID_REG); 1031 model = PCI_PRODUCT(reg); 1032 1033 #if defined(ORION) 1034 if (model == PCI_PRODUCT_MARVELL_88F5182) { 1035 reg = *(volatile uint32_t *)(regbase + ORION_PMI_BASE + 1036 ORION_PMI_SAMPLE_AT_RESET); 1037 if ((reg & ORION_PMISMPL_TCLK_MASK) == 0) 1038 model = PCI_PRODUCT_MARVELL_88F5082; 1039 } 1040 #endif 1041 #if defined(KIRKWOOD) 1042 if (model == PCI_PRODUCT_MARVELL_88F6281) { 1043 reg = *(volatile uint32_t *)(regbase + KIRKWOOD_MISC_BASE + 1044 KIRKWOOD_MISC_DEVICEID); 1045 if (reg == 1) /* 88F6192 is 1 */ 1046 model = MARVELL_KIRKWOOD_88F6192; 1047 } 1048 #endif 1049 1050 return model; 1051 } 1052 1053 uint8_t 1054 mvsoc_rev(void) 1055 { 1056 uint32_t reg; 1057 uint8_t rev; 1058 1059 KASSERT(regbase != 0xffffffff); 1060 1061 reg = *(volatile uint32_t *)(pex_base + PCI_CLASS_REG); 1062 rev = PCI_REVISION(reg); 1063 1064 return rev; 1065 } 1066 1067 1068 int 1069 mvsoc_target(int tag, uint32_t *target, uint32_t *attr, uint32_t *base, 1070 uint32_t *size) 1071 { 1072 int i; 1073 1074 KASSERT(regbase != 0xffffffff); 1075 1076 if (tag == MVSOC_TAG_INTERNALREG) { 1077 if (target != NULL) 1078 *target = 0; 1079 if (attr != NULL) 1080 *attr = 0; 1081 if (base != NULL) 1082 *base = read_mlmbreg(MVSOC_MLMB_IRBAR) & 1083 MVSOC_MLMB_IRBAR_BASE_MASK; 1084 if (size != NULL) 1085 *size = 0; 1086 1087 return 0; 1088 } 1089 1090 /* sanity check */ 1091 for (i = 0; i < __arraycount(mvsoc_tags); i++) 1092 if (mvsoc_tags[i].tag == tag) 1093 break; 1094 if (i >= __arraycount(mvsoc_tags)) 1095 return -1; 1096 1097 if (target != NULL) 1098 *target = mvsoc_tags[i].target; 1099 if (attr != NULL) 1100 *attr = mvsoc_tags[i].attr; 1101 1102 if (mvsoc_tags[i].target == MVSOC_UNITID_DDR) { 1103 if (tag == MARVELL_TAG_SDRAM_CS0 || 1104 tag == MARVELL_TAG_SDRAM_CS1 || 1105 tag == MARVELL_TAG_SDRAM_CS2 || 1106 tag == MARVELL_TAG_SDRAM_CS3) 1107 return mvsoc_target_ddr(mvsoc_tags[i].attr, base, size); 1108 else 1109 return mvsoc_target_ddr3(mvsoc_tags[i].attr, base, 1110 size); 1111 } else 1112 return mvsoc_target_peripheral(mvsoc_tags[i].target, 1113 mvsoc_tags[i].attr, base, size); 1114 } 1115 1116 static int 1117 mvsoc_target_ddr(uint32_t attr, uint32_t *base, uint32_t *size) 1118 { 1119 uint32_t baseaddrreg, sizereg; 1120 int cs; 1121 1122 /* 1123 * Read DDR SDRAM Controller Address Decode Registers 1124 */ 1125 1126 switch (attr) { 1127 case MARVELL_ATTR_SDRAM_CS0: 1128 cs = 0; 1129 break; 1130 case MARVELL_ATTR_SDRAM_CS1: 1131 cs = 1; 1132 break; 1133 case MARVELL_ATTR_SDRAM_CS2: 1134 cs = 2; 1135 break; 1136 case MARVELL_ATTR_SDRAM_CS3: 1137 cs = 3; 1138 break; 1139 default: 1140 aprint_error("unknwon ATTR: 0x%x", attr); 1141 return -1; 1142 } 1143 sizereg = *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSSR(cs)); 1144 if (sizereg & MVSOC_DSC_CSSR_WINEN) { 1145 baseaddrreg = 1146 *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSBAR(cs)); 1147 1148 if (base != NULL) 1149 *base = baseaddrreg & MVSOC_DSC_CSBAR_BASE_MASK; 1150 if (size != NULL) 1151 *size = (sizereg & MVSOC_DSC_CSSR_SIZE_MASK) + 1152 (~MVSOC_DSC_CSSR_SIZE_MASK + 1); 1153 } else { 1154 if (base != NULL) 1155 *base = 0; 1156 if (size != NULL) 1157 *size = 0; 1158 } 1159 return 0; 1160 } 1161 1162 static int 1163 mvsoc_target_ddr3(uint32_t attr, uint32_t *base, uint32_t *size) 1164 { 1165 uint32_t baseaddrreg, sizereg; 1166 int cs, i; 1167 1168 /* 1169 * Read DDR3 SDRAM Address Decoding Registers 1170 */ 1171 1172 switch (attr) { 1173 case MARVELL_ATTR_SDRAM_CS0: 1174 cs = 0; 1175 break; 1176 case MARVELL_ATTR_SDRAM_CS1: 1177 cs = 1; 1178 break; 1179 case MARVELL_ATTR_SDRAM_CS2: 1180 cs = 2; 1181 break; 1182 case MARVELL_ATTR_SDRAM_CS3: 1183 cs = 3; 1184 break; 1185 default: 1186 aprint_error("unknwon ATTR: 0x%x", attr); 1187 return -1; 1188 } 1189 for (i = 0; i < MVSOC_MLMB_NWIN; i++) { 1190 sizereg = read_mlmbreg(MVSOC_MLMB_WINCR(i)); 1191 if ((sizereg & MVSOC_MLMB_WINCR_EN) && 1192 MVSOC_MLMB_WINCR_WINCS(sizereg) == cs) 1193 break; 1194 } 1195 if (i == MVSOC_MLMB_NWIN) { 1196 if (base != NULL) 1197 *base = 0; 1198 if (size != NULL) 1199 *size = 0; 1200 return 0; 1201 } 1202 1203 baseaddrreg = read_mlmbreg(MVSOC_MLMB_WINBAR(i)); 1204 if (base != NULL) 1205 *base = baseaddrreg & MVSOC_MLMB_WINBAR_BASE_MASK; 1206 if (size != NULL) 1207 *size = (sizereg & MVSOC_MLMB_WINCR_SIZE_MASK) + 1208 (~MVSOC_MLMB_WINCR_SIZE_MASK + 1); 1209 return 0; 1210 } 1211 1212 static int 1213 mvsoc_target_peripheral(uint32_t target, uint32_t attr, uint32_t *base, 1214 uint32_t *size) 1215 { 1216 uint32_t basereg, ctrlreg, ta, tamask; 1217 int i; 1218 1219 /* 1220 * Read CPU Address Map Registers 1221 */ 1222 1223 ta = MVSOC_MLMB_WCR_TARGET(target) | MVSOC_MLMB_WCR_ATTR(attr); 1224 tamask = MVSOC_MLMB_WCR_TARGET(MVSOC_UNITID_MASK) | 1225 MVSOC_MLMB_WCR_ATTR(MARVELL_ATTR_MASK); 1226 1227 if (base != NULL) 1228 *base = 0; 1229 if (size != NULL) 1230 *size = 0; 1231 1232 for (i = 0; i < nwindow; i++) { 1233 ctrlreg = read_mlmbreg(MVSOC_MLMB_WCR(i)); 1234 if ((ctrlreg & tamask) != ta) 1235 continue; 1236 if (ctrlreg & MVSOC_MLMB_WCR_WINEN) { 1237 basereg = read_mlmbreg(MVSOC_MLMB_WBR(i)); 1238 1239 if (base != NULL) 1240 *base = basereg & MVSOC_MLMB_WBR_BASE_MASK; 1241 if (size != NULL) 1242 *size = (ctrlreg & 1243 MVSOC_MLMB_WCR_SIZE_MASK) + 1244 (~MVSOC_MLMB_WCR_SIZE_MASK + 1); 1245 } 1246 break; 1247 } 1248 return i; 1249 } 1250
Indexes created Thu Oct 23 22:10:10 GMT 2025