mvsoc.c revision 1.22
1 /* $NetBSD: mvsoc.c,v 1.22 2015/06/03 03:55:47 hsuenaga Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2013, 2014 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.22 2015/06/03 03:55:47 hsuenaga Exp $"); 30 31 #include "opt_cputypes.h" 32 #include "opt_mvsoc.h" 33 #ifdef ARMADAXP 34 #include "mvxpe.h" 35 #endif 36 37 #include <sys/param.h> 38 #include <sys/boot_flag.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 #include <sys/device.h> 42 #include <sys/errno.h> 43 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pcireg.h> 46 #include <dev/marvell/marvellreg.h> 47 #include <dev/marvell/marvellvar.h> 48 49 #include <arm/marvell/mvsocreg.h> 50 #include <arm/marvell/mvsocvar.h> 51 #include <arm/marvell/orionreg.h> 52 #include <arm/marvell/kirkwoodreg.h> 53 #include <arm/marvell/mv78xx0reg.h> 54 #include <arm/marvell/armadaxpvar.h> 55 #include <arm/marvell/armadaxpreg.h> 56 57 #include <uvm/uvm.h> 58 59 #include "locators.h" 60 61 #ifdef MVSOC_CONSOLE_EARLY 62 #include <dev/ic/ns16550reg.h> 63 #include <dev/ic/comreg.h> 64 #include <dev/cons.h> 65 #endif 66 67 static int mvsoc_match(device_t, struct cfdata *, void *); 68 static void mvsoc_attach(device_t, device_t, void *); 69 70 static int mvsoc_print(void *, const char *); 71 static int mvsoc_search(device_t, cfdata_t, const int *, void *); 72 73 static int mvsoc_target_ddr(uint32_t, uint32_t *, uint32_t *); 74 static int mvsoc_target_ddr3(uint32_t, uint32_t *, uint32_t *); 75 static int mvsoc_target_peripheral(uint32_t, uint32_t, uint32_t *, uint32_t *); 76 77 uint32_t mvPclk, mvSysclk, mvTclk = 0; 78 int nwindow = 0, nremap = 0; 79 static vaddr_t regbase = 0xffffffff, dsc_base, pex_base; 80 vaddr_t mlmb_base; 81 82 void (*mvsoc_intr_init)(void); 83 int (*mvsoc_clkgating)(struct marvell_attach_args *); 84 85 86 #ifdef MVSOC_CONSOLE_EARLY 87 static vaddr_t com_base; 88 89 static inline uint32_t 90 uart_read(bus_size_t o) 91 { 92 return *(volatile uint32_t *)(com_base + (o << 2)); 93 } 94 95 static inline void 96 uart_write(bus_size_t o, uint32_t v) 97 { 98 *(volatile uint32_t *)(com_base + (o << 2)) = v; 99 } 100 101 static int 102 mvsoc_cngetc(dev_t dv) 103 { 104 if ((uart_read(com_lsr) & LSR_RXRDY) == 0) 105 return -1; 106 107 return uart_read(com_data) & 0xff; 108 } 109 110 static void 111 mvsoc_cnputc(dev_t dv, int c) 112 { 113 int timo = 150000; 114 115 while ((uart_read(com_lsr) & LSR_TXRDY) == 0 && --timo > 0) 116 ; 117 118 uart_write(com_data, c); 119 120 timo = 150000; 121 while ((uart_read(com_lsr) & LSR_TSRE) == 0 && --timo > 0) 122 ; 123 } 124 125 static struct consdev mvsoc_earlycons = { 126 .cn_putc = mvsoc_cnputc, 127 .cn_getc = mvsoc_cngetc, 128 .cn_pollc = nullcnpollc, 129 }; 130 #endif 131 132 133 /* attributes */ 134 static struct { 135 int tag; 136 uint32_t attr; 137 uint32_t target; 138 } mvsoc_tags[] = { 139 { MARVELL_TAG_SDRAM_CS0, 140 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 141 { MARVELL_TAG_SDRAM_CS1, 142 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 143 { MARVELL_TAG_SDRAM_CS2, 144 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 145 { MARVELL_TAG_SDRAM_CS3, 146 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 147 148 { MARVELL_TAG_DDR3_CS0, 149 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 150 { MARVELL_TAG_DDR3_CS1, 151 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 152 { MARVELL_TAG_DDR3_CS2, 153 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 154 { MARVELL_TAG_DDR3_CS3, 155 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 156 157 #if defined(ORION) 158 { ORION_TAG_DEVICE_CS0, 159 ORION_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 160 { ORION_TAG_DEVICE_CS1, 161 ORION_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 162 { ORION_TAG_DEVICE_CS2, 163 ORION_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 164 { ORION_TAG_DEVICE_BOOTCS, 165 ORION_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 166 { ORION_TAG_FLASH_CS, 167 ORION_ATTR_FLASH_CS, MVSOC_UNITID_DEVBUS }, 168 { ORION_TAG_PEX0_MEM, 169 ORION_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 170 { ORION_TAG_PEX0_IO, 171 ORION_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 172 { ORION_TAG_PEX1_MEM, 173 ORION_ATTR_PEX_MEM, ORION_UNITID_PEX1 }, 174 { ORION_TAG_PEX1_IO, 175 ORION_ATTR_PEX_IO, ORION_UNITID_PEX1 }, 176 { ORION_TAG_PCI_MEM, 177 ORION_ATTR_PCI_MEM, ORION_UNITID_PCI }, 178 { ORION_TAG_PCI_IO, 179 ORION_ATTR_PCI_IO, ORION_UNITID_PCI }, 180 { ORION_TAG_CRYPT, 181 ORION_ATTR_CRYPT, ORION_UNITID_CRYPT }, 182 #endif 183 184 #if defined(KIRKWOOD) 185 { KIRKWOOD_TAG_NAND, 186 KIRKWOOD_ATTR_NAND, MVSOC_UNITID_DEVBUS }, 187 { KIRKWOOD_TAG_SPI, 188 KIRKWOOD_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 189 { KIRKWOOD_TAG_BOOTROM, 190 KIRKWOOD_ATTR_BOOTROM, MVSOC_UNITID_DEVBUS }, 191 { KIRKWOOD_TAG_PEX_MEM, 192 KIRKWOOD_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 193 { KIRKWOOD_TAG_PEX_IO, 194 KIRKWOOD_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 195 { KIRKWOOD_TAG_PEX1_MEM, 196 KIRKWOOD_ATTR_PEX1_MEM, MVSOC_UNITID_PEX }, 197 { KIRKWOOD_TAG_PEX1_IO, 198 KIRKWOOD_ATTR_PEX1_IO, MVSOC_UNITID_PEX }, 199 { KIRKWOOD_TAG_CRYPT, 200 KIRKWOOD_ATTR_CRYPT, KIRKWOOD_UNITID_CRYPT }, 201 #endif 202 203 #if defined(MV78XX0) 204 { MV78XX0_TAG_DEVICE_CS0, 205 MV78XX0_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 206 { MV78XX0_TAG_DEVICE_CS1, 207 MV78XX0_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 208 { MV78XX0_TAG_DEVICE_CS2, 209 MV78XX0_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 210 { MV78XX0_TAG_DEVICE_CS3, 211 MV78XX0_ATTR_DEVICE_CS3, MVSOC_UNITID_DEVBUS }, 212 { MV78XX0_TAG_DEVICE_BOOTCS, 213 MV78XX0_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 214 { MV78XX0_TAG_SPI, 215 MV78XX0_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 216 { MV78XX0_TAG_PEX0_MEM, 217 MV78XX0_ATTR_PEX_0_MEM, MVSOC_UNITID_PEX }, 218 { MV78XX0_TAG_PEX01_MEM, 219 MV78XX0_ATTR_PEX_1_MEM, MVSOC_UNITID_PEX }, 220 { MV78XX0_TAG_PEX02_MEM, 221 MV78XX0_ATTR_PEX_2_MEM, MVSOC_UNITID_PEX }, 222 { MV78XX0_TAG_PEX03_MEM, 223 MV78XX0_ATTR_PEX_3_MEM, MVSOC_UNITID_PEX }, 224 { MV78XX0_TAG_PEX0_IO, 225 MV78XX0_ATTR_PEX_0_IO, MVSOC_UNITID_PEX }, 226 { MV78XX0_TAG_PEX01_IO, 227 MV78XX0_ATTR_PEX_1_IO, MVSOC_UNITID_PEX }, 228 { MV78XX0_TAG_PEX02_IO, 229 MV78XX0_ATTR_PEX_2_IO, MVSOC_UNITID_PEX }, 230 { MV78XX0_TAG_PEX03_IO, 231 MV78XX0_ATTR_PEX_3_IO, MVSOC_UNITID_PEX }, 232 { MV78XX0_TAG_PEX1_MEM, 233 MV78XX0_ATTR_PEX_0_MEM, MV78XX0_UNITID_PEX1 }, 234 { MV78XX0_TAG_PEX11_MEM, 235 MV78XX0_ATTR_PEX_1_MEM, MV78XX0_UNITID_PEX1 }, 236 { MV78XX0_TAG_PEX12_MEM, 237 MV78XX0_ATTR_PEX_2_MEM, MV78XX0_UNITID_PEX1 }, 238 { MV78XX0_TAG_PEX13_MEM, 239 MV78XX0_ATTR_PEX_3_MEM, MV78XX0_UNITID_PEX1 }, 240 { MV78XX0_TAG_PEX1_IO, 241 MV78XX0_ATTR_PEX_0_IO, MV78XX0_UNITID_PEX1 }, 242 { MV78XX0_TAG_PEX11_IO, 243 MV78XX0_ATTR_PEX_1_IO, MV78XX0_UNITID_PEX1 }, 244 { MV78XX0_TAG_PEX12_IO, 245 MV78XX0_ATTR_PEX_2_IO, MV78XX0_UNITID_PEX1 }, 246 { MV78XX0_TAG_PEX13_IO, 247 MV78XX0_ATTR_PEX_3_IO, MV78XX0_UNITID_PEX1 }, 248 { MV78XX0_TAG_CRYPT, 249 MV78XX0_ATTR_CRYPT, MV78XX0_UNITID_CRYPT }, 250 #endif 251 252 #if defined(ARMADAXP) 253 { ARMADAXP_TAG_PEX00_MEM, 254 ARMADAXP_ATTR_PEXx0_MEM, ARMADAXP_UNITID_PEX0 }, 255 { ARMADAXP_TAG_PEX00_IO, 256 ARMADAXP_ATTR_PEXx0_IO, ARMADAXP_UNITID_PEX0 }, 257 { ARMADAXP_TAG_PEX01_MEM, 258 ARMADAXP_ATTR_PEXx1_MEM, ARMADAXP_UNITID_PEX0 }, 259 { ARMADAXP_TAG_PEX01_IO, 260 ARMADAXP_ATTR_PEXx1_IO, ARMADAXP_UNITID_PEX0 }, 261 { ARMADAXP_TAG_PEX02_MEM, 262 ARMADAXP_ATTR_PEXx2_MEM, ARMADAXP_UNITID_PEX0 }, 263 { ARMADAXP_TAG_PEX02_IO, 264 ARMADAXP_ATTR_PEXx2_IO, ARMADAXP_UNITID_PEX0 }, 265 { ARMADAXP_TAG_PEX03_MEM, 266 ARMADAXP_ATTR_PEXx3_MEM, ARMADAXP_UNITID_PEX0 }, 267 { ARMADAXP_TAG_PEX03_IO, 268 ARMADAXP_ATTR_PEXx3_IO, ARMADAXP_UNITID_PEX0 }, 269 { ARMADAXP_TAG_PEX2_MEM, 270 ARMADAXP_ATTR_PEX2_MEM, ARMADAXP_UNITID_PEX2 }, 271 { ARMADAXP_TAG_PEX2_IO, 272 ARMADAXP_ATTR_PEX2_IO, ARMADAXP_UNITID_PEX2 }, 273 { ARMADAXP_TAG_PEX3_MEM, 274 ARMADAXP_ATTR_PEX3_MEM, ARMADAXP_UNITID_PEX3 }, 275 { ARMADAXP_TAG_PEX3_IO, 276 ARMADAXP_ATTR_PEX3_IO, ARMADAXP_UNITID_PEX3 }, 277 #endif 278 }; 279 280 #if defined(ORION) 281 #define ORION_1(m) MARVELL_ORION_1_ ## m 282 #define ORION_2(m) MARVELL_ORION_2_ ## m 283 #endif 284 #if defined(KIRKWOOD) 285 #undef KIRKWOOD 286 #define KIRKWOOD(m) MARVELL_KIRKWOOD_ ## m 287 #endif 288 #if defined(MV78XX0) 289 #undef MV78XX0 290 #define MV78XX0(m) MARVELL_MV78XX0_ ## m 291 #endif 292 #if defined(ARMADAXP) 293 #undef ARMADAXP 294 #define ARMADAXP(m) MARVELL_ARMADAXP_ ## m 295 #define ARMADA370(m) MARVELL_ARMADA370_ ## m 296 #endif 297 static struct { 298 uint16_t model; 299 uint8_t rev; 300 const char *modelstr; 301 const char *revstr; 302 const char *typestr; 303 } nametbl[] = { 304 #if defined(ORION) 305 { ORION_1(88F1181), 0, "MV88F1181", NULL, "Orion1" }, 306 { ORION_1(88F5082), 2, "MV88F5082", "A2", "Orion1" }, 307 { ORION_1(88F5180N), 3, "MV88F5180N","B1", "Orion1" }, 308 { ORION_1(88F5181), 0, "MV88F5181", "A0", "Orion1" }, 309 { ORION_1(88F5181), 1, "MV88F5181", "A1", "Orion1" }, 310 { ORION_1(88F5181), 2, "MV88F5181", "B0", "Orion1" }, 311 { ORION_1(88F5181), 3, "MV88F5181", "B1", "Orion1" }, 312 { ORION_1(88F5181), 8, "MV88F5181L","A0", "Orion1" }, 313 { ORION_1(88F5181), 9, "MV88F5181L","A1", "Orion1" }, 314 { ORION_1(88F5182), 0, "MV88F5182", "A0", "Orion1" }, 315 { ORION_1(88F5182), 1, "MV88F5182", "A1", "Orion1" }, 316 { ORION_1(88F5182), 2, "MV88F5182", "A2", "Orion1" }, 317 { ORION_1(88F6082), 0, "MV88F6082", "A0", "Orion1" }, 318 { ORION_1(88F6082), 1, "MV88F6082", "A1", "Orion1" }, 319 { ORION_1(88F6183), 0, "MV88F6183", "A0", "Orion1" }, 320 { ORION_1(88F6183), 1, "MV88F6183", "Z0", "Orion1" }, 321 { ORION_1(88W8660), 0, "MV88W8660", "A0", "Orion1" }, 322 { ORION_1(88W8660), 1, "MV88W8660", "A1", "Orion1" }, 323 324 { ORION_2(88F1281), 0, "MV88F1281", "A0", "Orion2" }, 325 { ORION_2(88F5281), 0, "MV88F5281", "A0", "Orion2" }, 326 { ORION_2(88F5281), 1, "MV88F5281", "B0", "Orion2" }, 327 { ORION_2(88F5281), 2, "MV88F5281", "C0", "Orion2" }, 328 { ORION_2(88F5281), 3, "MV88F5281", "C1", "Orion2" }, 329 { ORION_2(88F5281), 4, "MV88F5281", "D0", "Orion2" }, 330 #endif 331 332 #if defined(KIRKWOOD) 333 { KIRKWOOD(88F6180), 2, "88F6180", "A0", "Kirkwood" }, 334 { KIRKWOOD(88F6180), 3, "88F6180", "A1", "Kirkwood" }, 335 { KIRKWOOD(88F6192), 0, "88F619x", "Z0", "Kirkwood" }, 336 { KIRKWOOD(88F6192), 2, "88F619x", "A0", "Kirkwood" }, 337 { KIRKWOOD(88F6192), 3, "88F619x", "A1", "Kirkwood" }, 338 { KIRKWOOD(88F6281), 0, "88F6281", "Z0", "Kirkwood" }, 339 { KIRKWOOD(88F6281), 2, "88F6281", "A0", "Kirkwood" }, 340 { KIRKWOOD(88F6281), 3, "88F6281", "A1", "Kirkwood" }, 341 { KIRKWOOD(88F6282), 0, "88F6282", "A0", "Kirkwood" }, 342 { KIRKWOOD(88F6282), 1, "88F6282", "A1", "Kirkwood" }, 343 #endif 344 345 #if defined(MV78XX0) 346 { MV78XX0(MV78100), 1, "MV78100", "A0", "Discovery Innovation" }, 347 { MV78XX0(MV78100), 2, "MV78100", "A1", "Discovery Innovation" }, 348 { MV78XX0(MV78200), 1, "MV78200", "A0", "Discovery Innovation" }, 349 #endif 350 351 #if defined(ARMADAXP) 352 { ARMADAXP(MV78130), 1, "MV78130", "A0", "Armada XP" }, 353 { ARMADAXP(MV78160), 1, "MV78160", "A0", "Armada XP" }, 354 { ARMADAXP(MV78230), 1, "MV78260", "A0", "Armada XP" }, 355 { ARMADAXP(MV78260), 1, "MV78260", "A0", "Armada XP" }, 356 { ARMADAXP(MV78260), 2, "MV78260", "B0", "Armada XP" }, 357 { ARMADAXP(MV78460), 1, "MV78460", "A0", "Armada XP" }, 358 { ARMADAXP(MV78460), 2, "MV78460", "B0", "Armada XP" }, 359 360 { ARMADA370(MV6707), 0, "MV6707", "A0", "Armada 370" }, 361 { ARMADA370(MV6707), 1, "MV6707", "A1", "Armada 370" }, 362 { ARMADA370(MV6710), 0, "MV6710", "A0", "Armada 370" }, 363 { ARMADA370(MV6710), 1, "MV6710", "A1", "Armada 370" }, 364 { ARMADA370(MV6W11), 0, "MV6W11", "A0", "Armada 370" }, 365 { ARMADA370(MV6W11), 1, "MV6W11", "A1", "Armada 370" }, 366 #endif 367 }; 368 369 enum marvell_tags ddr_tags[] = { 370 MARVELL_TAG_SDRAM_CS0, 371 MARVELL_TAG_SDRAM_CS1, 372 MARVELL_TAG_SDRAM_CS2, 373 MARVELL_TAG_SDRAM_CS3, 374 375 MARVELL_TAG_UNDEFINED 376 }; 377 enum marvell_tags ddr3_tags[] = { 378 MARVELL_TAG_DDR3_CS0, 379 MARVELL_TAG_DDR3_CS1, 380 MARVELL_TAG_DDR3_CS2, 381 MARVELL_TAG_DDR3_CS3, 382 383 MARVELL_TAG_UNDEFINED 384 }; 385 static struct { 386 uint16_t model; 387 uint8_t rev; 388 enum marvell_tags *tags; 389 } tagstbl[] = { 390 #if defined(ORION) 391 { ORION_1(88F1181), 0, ddr_tags }, 392 { ORION_1(88F5082), 2, ddr_tags }, 393 { ORION_1(88F5180N), 3, ddr_tags }, 394 { ORION_1(88F5181), 0, ddr_tags }, 395 { ORION_1(88F5181), 1, ddr_tags }, 396 { ORION_1(88F5181), 2, ddr_tags }, 397 { ORION_1(88F5181), 3, ddr_tags }, 398 { ORION_1(88F5181), 8, ddr_tags }, 399 { ORION_1(88F5181), 9, ddr_tags }, 400 { ORION_1(88F5182), 0, ddr_tags }, 401 { ORION_1(88F5182), 1, ddr_tags }, 402 { ORION_1(88F5182), 2, ddr_tags }, 403 { ORION_1(88F6082), 0, ddr_tags }, 404 { ORION_1(88F6082), 1, ddr_tags }, 405 { ORION_1(88F6183), 0, ddr_tags }, 406 { ORION_1(88F6183), 1, ddr_tags }, 407 { ORION_1(88W8660), 0, ddr_tags }, 408 { ORION_1(88W8660), 1, ddr_tags }, 409 410 { ORION_2(88F1281), 0, ddr_tags }, 411 { ORION_2(88F5281), 0, ddr_tags }, 412 { ORION_2(88F5281), 1, ddr_tags }, 413 { ORION_2(88F5281), 2, ddr_tags }, 414 { ORION_2(88F5281), 3, ddr_tags }, 415 { ORION_2(88F5281), 4, ddr_tags }, 416 #endif 417 418 #if defined(KIRKWOOD) 419 { KIRKWOOD(88F6180), 2, ddr_tags }, 420 { KIRKWOOD(88F6180), 3, ddr_tags }, 421 { KIRKWOOD(88F6192), 0, ddr_tags }, 422 { KIRKWOOD(88F6192), 2, ddr_tags }, 423 { KIRKWOOD(88F6192), 3, ddr_tags }, 424 { KIRKWOOD(88F6281), 0, ddr_tags }, 425 { KIRKWOOD(88F6281), 2, ddr_tags }, 426 { KIRKWOOD(88F6281), 3, ddr_tags }, 427 { KIRKWOOD(88F6282), 0, ddr_tags }, 428 { KIRKWOOD(88F6282), 1, ddr_tags }, 429 #endif 430 431 #if defined(MV78XX0) 432 { MV78XX0(MV78100), 1, ddr_tags }, 433 { MV78XX0(MV78100), 2, ddr_tags }, 434 { MV78XX0(MV78200), 1, ddr_tags }, 435 #endif 436 437 #if defined(ARMADAXP) 438 { ARMADAXP(MV78130), 1, ddr3_tags }, 439 { ARMADAXP(MV78160), 1, ddr3_tags }, 440 { ARMADAXP(MV78230), 1, ddr3_tags }, 441 { ARMADAXP(MV78260), 1, ddr3_tags }, 442 { ARMADAXP(MV78260), 2, ddr3_tags }, 443 { ARMADAXP(MV78460), 1, ddr3_tags }, 444 { ARMADAXP(MV78460), 2, ddr3_tags }, 445 446 { ARMADA370(MV6707), 0, ddr3_tags }, 447 { ARMADA370(MV6707), 1, ddr3_tags }, 448 { ARMADA370(MV6710), 0, ddr3_tags }, 449 { ARMADA370(MV6710), 1, ddr3_tags }, 450 { ARMADA370(MV6W11), 0, ddr3_tags }, 451 { ARMADA370(MV6W11), 1, ddr3_tags }, 452 #endif 453 }; 454 455 456 #define OFFSET_DEFAULT MVA_OFFSET_DEFAULT 457 #define IRQ_DEFAULT MVA_IRQ_DEFAULT 458 static const struct mvsoc_periph { 459 int model; 460 const char *name; 461 int unit; 462 bus_size_t offset; 463 int irq; 464 } mvsoc_periphs[] = { 465 #if defined(ORION) 466 #define ORION_IRQ_TMR (32 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 467 468 { ORION_1(88F1181), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 469 { ORION_1(88F1181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 470 { ORION_1(88F1181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 471 { ORION_1(88F1181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 472 { ORION_1(88F1181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 473 { ORION_1(88F1181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 474 { ORION_1(88F1181), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 475 476 { ORION_1(88F5082), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 477 { ORION_1(88F5082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 478 { ORION_1(88F5082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 479 { ORION_1(88F5082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 480 { ORION_1(88F5082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 481 { ORION_1(88F5082), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 482 { ORION_1(88F5082), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 483 { ORION_1(88F5082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 484 { ORION_1(88F5082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 485 { ORION_1(88F5082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 486 { ORION_1(88F5082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 487 { ORION_1(88F5082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 488 489 { ORION_1(88F5180N),"mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 490 { ORION_1(88F5180N),"mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 491 { ORION_1(88F5180N),"com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 492 { ORION_1(88F5180N),"com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 493 { ORION_1(88F5180N),"ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 494 { ORION_1(88F5180N),"gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 495 { ORION_1(88F5180N),"gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 496 { ORION_1(88F5180N),"gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 497 { ORION_1(88F5180N),"mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 498 { ORION_1(88F5180N),"mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 499 500 { ORION_1(88F5181), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 501 { ORION_1(88F5181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 502 { ORION_1(88F5181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 503 { ORION_1(88F5181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 504 { ORION_1(88F5181), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 505 { ORION_1(88F5181), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 506 { ORION_1(88F5181), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 507 { ORION_1(88F5181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 508 { ORION_1(88F5181), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 509 { ORION_1(88F5181), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 510 { ORION_1(88F5181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 511 512 { ORION_1(88F5182), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 513 { ORION_1(88F5182), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 514 { ORION_1(88F5182), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 515 { ORION_1(88F5182), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 516 { ORION_1(88F5182), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 517 { ORION_1(88F5182), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 518 { ORION_1(88F5182), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 519 { ORION_1(88F5182), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 520 { ORION_1(88F5182), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 521 { ORION_1(88F5182), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 522 { ORION_1(88F5182), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 523 { ORION_1(88F5182), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 524 525 { ORION_1(88F6082), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 526 { ORION_1(88F6082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 527 { ORION_1(88F6082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 528 { ORION_1(88F6082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 529 { ORION_1(88F6082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 530 { ORION_1(88F6082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 531 { ORION_1(88F6082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 532 { ORION_1(88F6082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 533 { ORION_1(88F6082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 534 { ORION_1(88F6082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 535 536 { ORION_1(88F6183), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 537 { ORION_1(88F6183), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 538 { ORION_1(88F6183), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 539 { ORION_1(88F6183), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 540 541 { ORION_1(88W8660), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 542 { ORION_1(88W8660), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 543 { ORION_1(88W8660), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 544 { ORION_1(88W8660), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 545 { ORION_1(88W8660), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 546 { ORION_1(88W8660), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 547 { ORION_1(88W8660), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 548 { ORION_1(88W8660), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 549 { ORION_1(88W8660), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 550 { ORION_1(88W8660), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 551 552 { ORION_2(88F1281), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 553 { ORION_2(88F1281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 554 { ORION_2(88F1281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 555 { ORION_2(88F1281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 556 { ORION_2(88F1281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 557 { ORION_2(88F1281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 558 { ORION_2(88F1281), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 559 560 { ORION_2(88F5281), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 561 { ORION_2(88F5281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 562 { ORION_2(88F5281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 563 { ORION_2(88F5281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 564 { ORION_2(88F5281), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 565 { ORION_2(88F5281), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 566 { ORION_2(88F5281), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 567 { ORION_2(88F5281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 568 { ORION_2(88F5281), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 569 { ORION_2(88F5281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 570 #endif 571 572 #if defined(KIRKWOOD) 573 #define KIRKWOOD_IRQ_TMR (64 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 574 575 { KIRKWOOD(88F6180),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 576 { KIRKWOOD(88F6180),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 577 { KIRKWOOD(88F6180),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 578 { KIRKWOOD(88F6180),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 579 { KIRKWOOD(88F6180),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 580 { KIRKWOOD(88F6180),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 581 { KIRKWOOD(88F6180),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 582 { KIRKWOOD(88F6180),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 583 { KIRKWOOD(88F6180),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 584 { KIRKWOOD(88F6180),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 585 { KIRKWOOD(88F6180),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 586 { KIRKWOOD(88F6180),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 587 588 { KIRKWOOD(88F6192),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 589 { KIRKWOOD(88F6192),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 590 { KIRKWOOD(88F6192),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 591 { KIRKWOOD(88F6192),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 592 { KIRKWOOD(88F6192),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 593 { KIRKWOOD(88F6192),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 594 { KIRKWOOD(88F6192),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 595 { KIRKWOOD(88F6192),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 596 { KIRKWOOD(88F6192),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 597 { KIRKWOOD(88F6192),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 598 { KIRKWOOD(88F6192),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 599 { KIRKWOOD(88F6192),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 600 { KIRKWOOD(88F6192),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 601 { KIRKWOOD(88F6192),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 602 603 { KIRKWOOD(88F6281),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 604 { KIRKWOOD(88F6281),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 605 { KIRKWOOD(88F6281),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 606 { KIRKWOOD(88F6281),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 607 { KIRKWOOD(88F6281),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 608 { KIRKWOOD(88F6281),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 609 { KIRKWOOD(88F6281),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 610 { KIRKWOOD(88F6281),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 611 { KIRKWOOD(88F6281),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT }, 612 { KIRKWOOD(88F6281),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 613 { KIRKWOOD(88F6281),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 614 { KIRKWOOD(88F6281),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 615 { KIRKWOOD(88F6281),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 616 { KIRKWOOD(88F6281),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 617 618 { KIRKWOOD(88F6282),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 619 { KIRKWOOD(88F6282),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 620 { KIRKWOOD(88F6282),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 621 { KIRKWOOD(88F6282),"mvsocts", 0, KIRKWOOD_TS_BASE, IRQ_DEFAULT }, 622 { KIRKWOOD(88F6282),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 623 { KIRKWOOD(88F6282),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 624 { KIRKWOOD(88F6282),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 625 { KIRKWOOD(88F6282),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 626 { KIRKWOOD(88F6282),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 627 { KIRKWOOD(88F6282),"gttwsi", 1, KIRKWOOD_TWSI1_BASE,KIRKWOOD_IRQ_TWSI1 }, 628 { KIRKWOOD(88F6282),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 629 { KIRKWOOD(88F6282),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 630 { KIRKWOOD(88F6282),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 631 { KIRKWOOD(88F6282),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 632 { KIRKWOOD(88F6282),"mvpex", 1, KIRKWOOD_PEX1_BASE,KIRKWOOD_IRQ_PEX1INT }, 633 { KIRKWOOD(88F6282),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 634 { KIRKWOOD(88F6282),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 635 #endif 636 637 #if defined(MV78XX0) 638 { MV78XX0(MV78100), "mvsoctmr",0, MVSOC_TMR_BASE, MV78XX0_IRQ_TIMER0 }, 639 { MV78XX0(MV78100), "mvsocgpp",0, MVSOC_GPP_BASE, MV78XX0_IRQ_GPIO0_7 }, 640 { MV78XX0(MV78100), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0 }, 641 { MV78XX0(MV78100), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1 }, 642 { MV78XX0(MV78100), "com", 2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 }, 643 { MV78XX0(MV78100), "com", 3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 }, 644 { MV78XX0(MV78100), "gttwsi", 0, MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI0 }, 645 { MV78XX0(MV78100), "gttwsi", 1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 }, 646 { MV78XX0(MV78100), "mvgbec", 0, MV78XX0_GBE0_BASE,IRQ_DEFAULT }, 647 { MV78XX0(MV78100), "mvgbec", 1, MV78XX0_GBE1_BASE,IRQ_DEFAULT }, 648 { MV78XX0(MV78100), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA }, 649 650 { MV78XX0(MV78200), "mvsoctmr",0, MVSOC_TMR_BASE, MV78XX0_IRQ_TIMER0 }, 651 { MV78XX0(MV78200), "mvsocgpp",0, MVSOC_GPP_BASE, MV78XX0_IRQ_GPIO0_7 }, 652 { MV78XX0(MV78200), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0 }, 653 { MV78XX0(MV78200), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1 }, 654 { MV78XX0(MV78200), "com", 2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 }, 655 { MV78XX0(MV78200), "com", 3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 }, 656 { MV78XX0(MV78200), "gttwsi", 0, MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI0 }, 657 { MV78XX0(MV78200), "gttwsi", 1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 }, 658 { MV78XX0(MV78200), "mvgbec", 0, MV78XX0_GBE0_BASE,IRQ_DEFAULT }, 659 { MV78XX0(MV78200), "mvgbec", 1, MV78XX0_GBE1_BASE,IRQ_DEFAULT }, 660 { MV78XX0(MV78200), "mvgbec", 2, MV78XX0_GBE2_BASE,IRQ_DEFAULT }, 661 { MV78XX0(MV78200), "mvgbec", 3, MV78XX0_GBE3_BASE,IRQ_DEFAULT }, 662 { MV78XX0(MV78200), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA }, 663 #endif 664 665 #if defined(ARMADAXP) 666 { ARMADAXP(MV78130), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 667 { ARMADAXP(MV78130), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 668 { ARMADAXP(MV78130), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 669 { ARMADAXP(MV78130), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 670 { ARMADAXP(MV78130), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 671 { ARMADAXP(MV78130), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 672 { ARMADAXP(MV78130), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 673 { ARMADAXP(MV78130), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 674 { ARMADAXP(MV78130), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 675 { ARMADAXP(MV78130), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 676 { ARMADAXP(MV78130), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 677 { ARMADAXP(MV78130), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 678 { ARMADAXP(MV78130), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 679 { ARMADAXP(MV78130), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 680 { ARMADAXP(MV78130), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 681 { ARMADAXP(MV78130), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 682 { ARMADAXP(MV78130), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 683 { ARMADAXP(MV78130), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 684 { ARMADAXP(MV78130), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 685 { ARMADAXP(MV78130), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 686 { ARMADAXP(MV78130), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 687 #if NMVXPE > 0 688 { ARMADAXP(MV78130), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 689 { ARMADAXP(MV78130), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 690 { ARMADAXP(MV78130), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 691 #else 692 { ARMADAXP(MV78130), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 693 { ARMADAXP(MV78130), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 694 #endif 695 { ARMADAXP(MV78130), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 696 { ARMADAXP(MV78130), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 697 698 { ARMADAXP(MV78160), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 699 { ARMADAXP(MV78160), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 700 { ARMADAXP(MV78160), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 701 { ARMADAXP(MV78160), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 702 { ARMADAXP(MV78160), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 703 { ARMADAXP(MV78160), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 704 { ARMADAXP(MV78160), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 705 { ARMADAXP(MV78160), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 706 { ARMADAXP(MV78160), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 707 { ARMADAXP(MV78160), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 708 { ARMADAXP(MV78160), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 709 { ARMADAXP(MV78160), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 710 { ARMADAXP(MV78160), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 711 { ARMADAXP(MV78160), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 712 { ARMADAXP(MV78160), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 713 { ARMADAXP(MV78160), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 714 { ARMADAXP(MV78160), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 715 { ARMADAXP(MV78160), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 716 { ARMADAXP(MV78160), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 717 { ARMADAXP(MV78160), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 718 { ARMADAXP(MV78160), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 719 #if NMVXPE > 0 720 { ARMADAXP(MV78160), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 721 { ARMADAXP(MV78160), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 722 { ARMADAXP(MV78160), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 723 { ARMADAXP(MV78160), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 724 { ARMADAXP(MV78160), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX }, 725 #else 726 { ARMADAXP(MV78160), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 727 { ARMADAXP(MV78160), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 728 { ARMADAXP(MV78160), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 729 { ARMADAXP(MV78160), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 730 #endif 731 { ARMADAXP(MV78160), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 732 { ARMADAXP(MV78160), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 733 734 { ARMADAXP(MV78230), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 735 { ARMADAXP(MV78230), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 736 { ARMADAXP(MV78230), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 737 { ARMADAXP(MV78230), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 738 { ARMADAXP(MV78230), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 739 { ARMADAXP(MV78230), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 740 { ARMADAXP(MV78230), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 741 { ARMADAXP(MV78230), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 742 { ARMADAXP(MV78230), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 743 { ARMADAXP(MV78230), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 744 { ARMADAXP(MV78230), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 745 { ARMADAXP(MV78230), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 746 { ARMADAXP(MV78230), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 747 { ARMADAXP(MV78230), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 748 { ARMADAXP(MV78230), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 749 { ARMADAXP(MV78230), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 750 { ARMADAXP(MV78230), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 751 { ARMADAXP(MV78230), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 752 { ARMADAXP(MV78230), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 753 { ARMADAXP(MV78230), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 754 { ARMADAXP(MV78230), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 755 #if NMVXPE > 0 756 { ARMADAXP(MV78230), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 757 { ARMADAXP(MV78230), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 758 { ARMADAXP(MV78230), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 759 { ARMADAXP(MV78230), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 760 #else 761 { ARMADAXP(MV78230), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 762 { ARMADAXP(MV78230), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 763 { ARMADAXP(MV78230), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 764 #endif 765 { ARMADAXP(MV78230), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 766 { ARMADAXP(MV78230), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 767 768 { ARMADAXP(MV78260), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 769 { ARMADAXP(MV78260), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 770 { ARMADAXP(MV78260), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 771 { ARMADAXP(MV78260), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 772 { ARMADAXP(MV78260), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 773 { ARMADAXP(MV78260), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 774 { ARMADAXP(MV78260), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 775 { ARMADAXP(MV78260), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 776 { ARMADAXP(MV78260), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 777 { ARMADAXP(MV78260), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 778 { ARMADAXP(MV78260), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 779 { ARMADAXP(MV78260), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 780 { ARMADAXP(MV78260), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 781 { ARMADAXP(MV78260), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 782 { ARMADAXP(MV78260), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 783 { ARMADAXP(MV78260), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 784 { ARMADAXP(MV78260), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 785 { ARMADAXP(MV78260), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 786 { ARMADAXP(MV78260), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 787 { ARMADAXP(MV78260), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 788 { ARMADAXP(MV78260), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 789 #if NMVXPE > 0 790 { ARMADAXP(MV78260), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 791 { ARMADAXP(MV78260), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 792 { ARMADAXP(MV78260), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 793 { ARMADAXP(MV78260), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 794 { ARMADAXP(MV78260), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX }, 795 #else 796 { ARMADAXP(MV78260), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 797 { ARMADAXP(MV78260), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 798 { ARMADAXP(MV78260), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 799 { ARMADAXP(MV78260), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 800 #endif 801 { ARMADAXP(MV78260), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 802 { ARMADAXP(MV78260), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 803 804 { ARMADAXP(MV78460), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 805 { ARMADAXP(MV78460), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 806 { ARMADAXP(MV78460), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 807 { ARMADAXP(MV78460), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 808 { ARMADAXP(MV78460), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 809 { ARMADAXP(MV78460), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 810 { ARMADAXP(MV78460), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 811 { ARMADAXP(MV78460), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 812 { ARMADAXP(MV78460), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 813 { ARMADAXP(MV78460), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 814 { ARMADAXP(MV78460), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 815 { ARMADAXP(MV78460), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 816 { ARMADAXP(MV78460), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 817 { ARMADAXP(MV78460), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 818 { ARMADAXP(MV78460), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 819 { ARMADAXP(MV78460), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 820 { ARMADAXP(MV78460), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 821 { ARMADAXP(MV78460), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 822 { ARMADAXP(MV78460), "mvpex", 5, ARMADAXP_PEX3_BASE,ARMADAXP_IRQ_PEX3 }, 823 { ARMADAXP(MV78460), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 824 { ARMADAXP(MV78460), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 825 { ARMADAXP(MV78460), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 826 #if NMVXPE > 0 827 { ARMADAXP(MV78460), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 828 { ARMADAXP(MV78460), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 829 { ARMADAXP(MV78460), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 830 { ARMADAXP(MV78460), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 831 { ARMADAXP(MV78460), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX }, 832 #else 833 { ARMADAXP(MV78460), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 834 { ARMADAXP(MV78460), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 835 { ARMADAXP(MV78460), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 836 { ARMADAXP(MV78460), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 837 #endif 838 { ARMADAXP(MV78460), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 839 { ARMADAXP(MV78460), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 840 841 { ARMADA370(MV6710), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 842 { ARMADA370(MV6710), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 843 { ARMADA370(MV6710), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 844 { ARMADA370(MV6710), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 845 { ARMADA370(MV6710), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 846 { ARMADA370(MV6710), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 847 { ARMADA370(MV6710), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 848 { ARMADA370(MV6710), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 849 { ARMADA370(MV6710), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 850 { ARMADA370(MV6710), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 851 { ARMADA370(MV6710), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 852 { ARMADA370(MV6710), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 853 { ARMADA370(MV6710), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 854 { ARMADA370(MV6710), "mvspi", 1, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 855 { ARMADA370(MV6710), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 856 #if NMVXPE > 0 857 { ARMADA370(MV6710), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 858 { ARMADA370(MV6710), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 859 { ARMADA370(MV6710), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 860 #else 861 { ARMADA370(MV6710), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 862 { ARMADA370(MV6710), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 863 #endif 864 { ARMADA370(MV6710), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 865 #endif 866 }; 867 868 869 CFATTACH_DECL_NEW(mvsoc, sizeof(struct mvsoc_softc), 870 mvsoc_match, mvsoc_attach, NULL, NULL); 871 872 /* ARGSUSED */ 873 static int 874 mvsoc_match(device_t parent, struct cfdata *match, void *aux) 875 { 876 877 return 1; 878 } 879 880 /* ARGSUSED */ 881 static void 882 mvsoc_attach(device_t parent, device_t self, void *aux) 883 { 884 struct mvsoc_softc *sc = device_private(self); 885 struct marvell_attach_args mva; 886 enum marvell_tags *tags; 887 uint16_t model; 888 uint8_t rev; 889 int i; 890 891 sc->sc_dev = self; 892 sc->sc_iot = &mvsoc_bs_tag; 893 sc->sc_addr = vtophys(regbase); 894 sc->sc_dmat = &mvsoc_bus_dma_tag; 895 if (bus_space_map(sc->sc_iot, sc->sc_addr, 0x100000, 0, &sc->sc_ioh) != 896 0) { 897 aprint_error_dev(self, "can't map registers\n"); 898 return; 899 } 900 901 model = mvsoc_model(); 902 rev = mvsoc_rev(); 903 for (i = 0; i < __arraycount(nametbl); i++) 904 if (nametbl[i].model == model && nametbl[i].rev == rev) 905 break; 906 if (i >= __arraycount(nametbl)) 907 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 908 909 aprint_normal(": Marvell %s %s%s %s\n", 910 nametbl[i].modelstr, 911 nametbl[i].revstr != NULL ? "Rev. " : "", 912 nametbl[i].revstr != NULL ? nametbl[i].revstr : "", 913 nametbl[i].typestr); 914 aprint_normal("%s: CPU Clock %d.%03d MHz" 915 " SysClock %d.%03d MHz TClock %d.%03d MHz\n", 916 device_xname(self), 917 mvPclk / 1000000, (mvPclk / 1000) % 1000, 918 mvSysclk / 1000000, (mvSysclk / 1000) % 1000, 919 mvTclk / 1000000, (mvTclk / 1000) % 1000); 920 aprint_naive("\n"); 921 922 mvsoc_intr_init(); 923 924 for (i = 0; i < __arraycount(tagstbl); i++) 925 if (tagstbl[i].model == model && tagstbl[i].rev == rev) 926 break; 927 if (i >= __arraycount(tagstbl)) 928 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 929 tags = tagstbl[i].tags; 930 931 if (boothowto & (AB_VERBOSE | AB_DEBUG)) 932 mvsoc_target_dump(sc); 933 934 for (i = 0; i < __arraycount(mvsoc_periphs); i++) { 935 if (mvsoc_periphs[i].model != model) 936 continue; 937 938 mva.mva_name = mvsoc_periphs[i].name; 939 mva.mva_model = model; 940 mva.mva_revision = rev; 941 mva.mva_iot = sc->sc_iot; 942 mva.mva_ioh = sc->sc_ioh; 943 mva.mva_unit = mvsoc_periphs[i].unit; 944 mva.mva_addr = sc->sc_addr; 945 mva.mva_offset = mvsoc_periphs[i].offset; 946 mva.mva_size = 0; 947 mva.mva_dmat = sc->sc_dmat; 948 mva.mva_irq = mvsoc_periphs[i].irq; 949 mva.mva_tags = tags; 950 951 /* Skip clock disabled devices */ 952 if (mvsoc_clkgating != NULL && mvsoc_clkgating(&mva)) { 953 aprint_normal_dev(self, "%s%d clock disabled\n", 954 mvsoc_periphs[i].name, mvsoc_periphs[i].unit); 955 continue; 956 } 957 958 config_found_sm_loc(sc->sc_dev, "mvsoc", NULL, &mva, 959 mvsoc_print, mvsoc_search); 960 } 961 } 962 963 static int 964 mvsoc_print(void *aux, const char *pnp) 965 { 966 struct marvell_attach_args *mva = aux; 967 968 if (pnp) 969 aprint_normal("%s at %s unit %d", 970 mva->mva_name, pnp, mva->mva_unit); 971 else { 972 if (mva->mva_unit != MVA_UNIT_DEFAULT) 973 aprint_normal(" unit %d", mva->mva_unit); 974 if (mva->mva_offset != MVA_OFFSET_DEFAULT) { 975 aprint_normal(" offset 0x%04lx", mva->mva_offset); 976 if (mva->mva_size > 0) 977 aprint_normal("-0x%04lx", 978 mva->mva_offset + mva->mva_size - 1); 979 } 980 if (mva->mva_irq != MVA_IRQ_DEFAULT) 981 aprint_normal(" irq %d", mva->mva_irq); 982 } 983 984 return UNCONF; 985 } 986 987 /* ARGSUSED */ 988 static int 989 mvsoc_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 990 { 991 992 return config_match(parent, cf, aux); 993 } 994 995 /* ARGSUSED */ 996 int 997 marvell_winparams_by_tag(device_t dev, int tag, int *target, int *attribute, 998 uint64_t *base, uint32_t *size) 999 { 1000 uint32_t base32; 1001 int rv; 1002 1003 rv = mvsoc_target(tag, target, attribute, &base32, size); 1004 *base = base32; 1005 if (rv == -1) 1006 return -1; 1007 return 0; 1008 } 1009 1010 1011 /* 1012 * These functions is called before bus_space is initialized. 1013 */ 1014 1015 void 1016 mvsoc_bootstrap(bus_addr_t iobase) 1017 { 1018 1019 regbase = iobase; 1020 dsc_base = iobase + MVSOC_DSC_BASE; 1021 mlmb_base = iobase + MVSOC_MLMB_BASE; 1022 pex_base = iobase + MVSOC_PEX_BASE; 1023 #ifdef MVSOC_CONSOLE_EARLY 1024 com_base = iobase + MVSOC_COM0_BASE; 1025 cn_tab = &mvsoc_earlycons; 1026 printf("Hello\n"); 1027 #endif 1028 } 1029 1030 /* 1031 * We can read register of PCI configurations from (MVSOC_PEX_BASE + 0). 1032 */ 1033 uint16_t 1034 mvsoc_model(void) 1035 { 1036 /* 1037 * We read product-id from vendor/device register of PCI-Express. 1038 */ 1039 uint32_t reg; 1040 uint16_t model; 1041 1042 KASSERT(regbase != 0xffffffff); 1043 1044 reg = *(volatile uint32_t *)(pex_base + PCI_ID_REG); 1045 model = PCI_PRODUCT(reg); 1046 1047 #if defined(ORION) 1048 if (model == PCI_PRODUCT_MARVELL_88F5182) { 1049 reg = *(volatile uint32_t *)(regbase + ORION_PMI_BASE + 1050 ORION_PMI_SAMPLE_AT_RESET); 1051 if ((reg & ORION_PMISMPL_TCLK_MASK) == 0) 1052 model = PCI_PRODUCT_MARVELL_88F5082; 1053 } 1054 #endif 1055 #if defined(KIRKWOOD) 1056 if (model == PCI_PRODUCT_MARVELL_88F6281) { 1057 reg = *(volatile uint32_t *)(regbase + KIRKWOOD_MISC_BASE + 1058 KIRKWOOD_MISC_DEVICEID); 1059 if (reg == 1) /* 88F6192 is 1 */ 1060 model = MARVELL_KIRKWOOD_88F6192; 1061 } 1062 #endif 1063 1064 return model; 1065 } 1066 1067 uint8_t 1068 mvsoc_rev(void) 1069 { 1070 uint32_t reg; 1071 uint8_t rev; 1072 1073 KASSERT(regbase != 0xffffffff); 1074 1075 reg = *(volatile uint32_t *)(pex_base + PCI_CLASS_REG); 1076 rev = PCI_REVISION(reg); 1077 1078 return rev; 1079 } 1080 1081 1082 int 1083 mvsoc_target(int tag, uint32_t *target, uint32_t *attr, uint32_t *base, 1084 uint32_t *size) 1085 { 1086 int i; 1087 1088 KASSERT(regbase != 0xffffffff); 1089 1090 if (tag == MVSOC_TAG_INTERNALREG) { 1091 if (target != NULL) 1092 *target = 0; 1093 if (attr != NULL) 1094 *attr = 0; 1095 if (base != NULL) 1096 *base = read_mlmbreg(MVSOC_MLMB_IRBAR) & 1097 MVSOC_MLMB_IRBAR_BASE_MASK; 1098 if (size != NULL) 1099 *size = 0; 1100 1101 return 0; 1102 } 1103 1104 /* sanity check */ 1105 for (i = 0; i < __arraycount(mvsoc_tags); i++) 1106 if (mvsoc_tags[i].tag == tag) 1107 break; 1108 if (i >= __arraycount(mvsoc_tags)) 1109 return -1; 1110 1111 if (target != NULL) 1112 *target = mvsoc_tags[i].target; 1113 if (attr != NULL) 1114 *attr = mvsoc_tags[i].attr; 1115 1116 if (mvsoc_tags[i].target == MVSOC_UNITID_DDR) { 1117 if (tag == MARVELL_TAG_SDRAM_CS0 || 1118 tag == MARVELL_TAG_SDRAM_CS1 || 1119 tag == MARVELL_TAG_SDRAM_CS2 || 1120 tag == MARVELL_TAG_SDRAM_CS3) 1121 return mvsoc_target_ddr(mvsoc_tags[i].attr, base, size); 1122 else 1123 return mvsoc_target_ddr3(mvsoc_tags[i].attr, base, 1124 size); 1125 } else 1126 return mvsoc_target_peripheral(mvsoc_tags[i].target, 1127 mvsoc_tags[i].attr, base, size); 1128 } 1129 1130 static int 1131 mvsoc_target_ddr(uint32_t attr, uint32_t *base, uint32_t *size) 1132 { 1133 uint32_t baseaddrreg, sizereg; 1134 int cs; 1135 1136 /* 1137 * Read DDR SDRAM Controller Address Decode Registers 1138 */ 1139 1140 switch (attr) { 1141 case MARVELL_ATTR_SDRAM_CS0: 1142 cs = 0; 1143 break; 1144 case MARVELL_ATTR_SDRAM_CS1: 1145 cs = 1; 1146 break; 1147 case MARVELL_ATTR_SDRAM_CS2: 1148 cs = 2; 1149 break; 1150 case MARVELL_ATTR_SDRAM_CS3: 1151 cs = 3; 1152 break; 1153 default: 1154 aprint_error("unknwon ATTR: 0x%x", attr); 1155 return -1; 1156 } 1157 sizereg = *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSSR(cs)); 1158 if (sizereg & MVSOC_DSC_CSSR_WINEN) { 1159 baseaddrreg = 1160 *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSBAR(cs)); 1161 1162 if (base != NULL) 1163 *base = baseaddrreg & MVSOC_DSC_CSBAR_BASE_MASK; 1164 if (size != NULL) 1165 *size = (sizereg & MVSOC_DSC_CSSR_SIZE_MASK) + 1166 (~MVSOC_DSC_CSSR_SIZE_MASK + 1); 1167 } else { 1168 if (base != NULL) 1169 *base = 0; 1170 if (size != NULL) 1171 *size = 0; 1172 } 1173 return 0; 1174 } 1175 1176 static int 1177 mvsoc_target_ddr3(uint32_t attr, uint32_t *base, uint32_t *size) 1178 { 1179 uint32_t baseaddrreg, sizereg; 1180 int cs, i; 1181 1182 /* 1183 * Read DDR3 SDRAM Address Decoding Registers 1184 */ 1185 1186 switch (attr) { 1187 case MARVELL_ATTR_SDRAM_CS0: 1188 cs = 0; 1189 break; 1190 case MARVELL_ATTR_SDRAM_CS1: 1191 cs = 1; 1192 break; 1193 case MARVELL_ATTR_SDRAM_CS2: 1194 cs = 2; 1195 break; 1196 case MARVELL_ATTR_SDRAM_CS3: 1197 cs = 3; 1198 break; 1199 default: 1200 aprint_error("unknwon ATTR: 0x%x", attr); 1201 return -1; 1202 } 1203 for (i = 0; i < MVSOC_MLMB_NWIN; i++) { 1204 sizereg = read_mlmbreg(MVSOC_MLMB_WINCR(i)); 1205 if ((sizereg & MVSOC_MLMB_WINCR_EN) && 1206 MVSOC_MLMB_WINCR_WINCS(sizereg) == cs) 1207 break; 1208 } 1209 if (i == MVSOC_MLMB_NWIN) { 1210 if (base != NULL) 1211 *base = 0; 1212 if (size != NULL) 1213 *size = 0; 1214 return 0; 1215 } 1216 1217 baseaddrreg = read_mlmbreg(MVSOC_MLMB_WINBAR(i)); 1218 if (base != NULL) 1219 *base = baseaddrreg & MVSOC_MLMB_WINBAR_BASE_MASK; 1220 if (size != NULL) 1221 *size = (sizereg & MVSOC_MLMB_WINCR_SIZE_MASK) + 1222 (~MVSOC_MLMB_WINCR_SIZE_MASK + 1); 1223 return 0; 1224 } 1225 1226 static int 1227 mvsoc_target_peripheral(uint32_t target, uint32_t attr, uint32_t *base, 1228 uint32_t *size) 1229 { 1230 uint32_t basereg, ctrlreg, ta, tamask; 1231 int i; 1232 1233 /* 1234 * Read CPU Address Map Registers 1235 */ 1236 1237 ta = MVSOC_MLMB_WCR_TARGET(target) | MVSOC_MLMB_WCR_ATTR(attr); 1238 tamask = MVSOC_MLMB_WCR_TARGET(MVSOC_UNITID_MASK) | 1239 MVSOC_MLMB_WCR_ATTR(MARVELL_ATTR_MASK); 1240 1241 if (base != NULL) 1242 *base = 0; 1243 if (size != NULL) 1244 *size = 0; 1245 1246 for (i = 0; i < nwindow; i++) { 1247 ctrlreg = read_mlmbreg(MVSOC_MLMB_WCR(i)); 1248 if ((ctrlreg & tamask) != ta) 1249 continue; 1250 if (ctrlreg & MVSOC_MLMB_WCR_WINEN) { 1251 basereg = read_mlmbreg(MVSOC_MLMB_WBR(i)); 1252 1253 if (base != NULL) 1254 *base = basereg & MVSOC_MLMB_WBR_BASE_MASK; 1255 if (size != NULL) 1256 *size = (ctrlreg & 1257 MVSOC_MLMB_WCR_SIZE_MASK) + 1258 (~MVSOC_MLMB_WCR_SIZE_MASK + 1); 1259 } 1260 break; 1261 } 1262 return i; 1263 } 1264 1265 int 1266 mvsoc_target_dump(struct mvsoc_softc *sc) 1267 { 1268 uint32_t reg, base, size, target, attr, enable; 1269 int i, n; 1270 1271 for (i = 0, n = 0; i < nwindow; i++) { 1272 reg = read_mlmbreg(MVSOC_MLMB_WCR(i)); 1273 enable = reg & MVSOC_MLMB_WCR_WINEN; 1274 target = MVSOC_MLMB_WCR_GET_TARGET(reg); 1275 attr = MVSOC_MLMB_WCR_GET_ATTR(reg); 1276 size = MVSOC_MLMB_WCR_GET_SIZE(reg); 1277 1278 reg = read_mlmbreg(MVSOC_MLMB_WBR(i)); 1279 base = MVSOC_MLMB_WBR_GET_BASE(reg); 1280 1281 if (!enable) 1282 continue; 1283 1284 aprint_verbose_dev(sc->sc_dev, 1285 "Mbus window %2d: Base 0x%08x Size 0x%08x ", i, base, size); 1286 #ifdef ARMADAXP 1287 armadaxp_attr_dump(sc, target, attr); 1288 #else 1289 mvsoc_attr_dump(sc, target, attr); 1290 #endif 1291 printf("\n"); 1292 n++; 1293 } 1294 1295 return n; 1296 } 1297 1298 int 1299 mvsoc_attr_dump(struct mvsoc_softc *sc, uint32_t target, uint32_t attr) 1300 { 1301 aprint_verbose_dev(sc->sc_dev, "target 0x%x(attr 0x%x)", target, attr); 1302 return 0; 1303 } 1304
Indexes created Thu Oct 23 22:10:10 GMT 2025