mvsoc.c revision 1.26
1 /* $NetBSD: mvsoc.c,v 1.26 2017/01/07 21:12:42 christos Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2013, 2014, 2016 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.26 2017/01/07 21:12:42 christos Exp $"); 30 31 #include "opt_cputypes.h" 32 #include "opt_mvsoc.h" 33 #ifdef ARMADAXP 34 #include "mvxpe.h" 35 #include "mvxpsec.h" 36 #endif 37 38 #include <sys/param.h> 39 #include <sys/boot_flag.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/device.h> 43 #include <sys/errno.h> 44 45 #include <dev/pci/pcidevs.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/marvell/marvellreg.h> 48 #include <dev/marvell/marvellvar.h> 49 50 #include <arm/marvell/mvsocreg.h> 51 #include <arm/marvell/mvsocvar.h> 52 #include <arm/marvell/orionreg.h> 53 #include <arm/marvell/kirkwoodreg.h> 54 #include <arm/marvell/mv78xx0reg.h> 55 #include <arm/marvell/dovereg.h> 56 #include <arm/marvell/armadaxpvar.h> 57 #include <arm/marvell/armadaxpreg.h> 58 59 #include <uvm/uvm.h> 60 61 #include "locators.h" 62 63 #ifdef MVSOC_CONSOLE_EARLY 64 #include <dev/ic/ns16550reg.h> 65 #include <dev/ic/comreg.h> 66 #include <dev/cons.h> 67 #endif 68 69 static int mvsoc_match(device_t, struct cfdata *, void *); 70 static void mvsoc_attach(device_t, device_t, void *); 71 72 static int mvsoc_print(void *, const char *); 73 static int mvsoc_search(device_t, cfdata_t, const int *, void *); 74 75 static int mvsoc_target_ddr(uint32_t, uint32_t *, uint32_t *); 76 static int mvsoc_target_ddr3(uint32_t, uint32_t *, uint32_t *); 77 static int mvsoc_target_axi(int, uint32_t *, uint32_t *); 78 static int mvsoc_target_peripheral(uint32_t, uint32_t, uint32_t *, uint32_t *); 79 80 uint32_t mvPclk, mvSysclk, mvTclk = 0; 81 int nwindow = 0, nremap = 0; 82 static vaddr_t regbase = 0xffffffff, dsc_base, pex_base; 83 vaddr_t mlmb_base; 84 85 void (*mvsoc_intr_init)(void); 86 int (*mvsoc_clkgating)(struct marvell_attach_args *); 87 88 89 #ifdef MVSOC_CONSOLE_EARLY 90 static vaddr_t com_base; 91 92 static inline uint32_t 93 uart_read(bus_size_t o) 94 { 95 return *(volatile uint32_t *)(com_base + (o << 2)); 96 } 97 98 static inline void 99 uart_write(bus_size_t o, uint32_t v) 100 { 101 *(volatile uint32_t *)(com_base + (o << 2)) = v; 102 } 103 104 static int 105 mvsoc_cngetc(dev_t dv) 106 { 107 if ((uart_read(com_lsr) & LSR_RXRDY) == 0) 108 return -1; 109 110 return uart_read(com_data) & 0xff; 111 } 112 113 static void 114 mvsoc_cnputc(dev_t dv, int c) 115 { 116 int timo = 150000; 117 118 while ((uart_read(com_lsr) & LSR_TXRDY) == 0 && --timo > 0) 119 ; 120 121 uart_write(com_data, c); 122 123 timo = 150000; 124 while ((uart_read(com_lsr) & LSR_TSRE) == 0 && --timo > 0) 125 ; 126 } 127 128 static struct consdev mvsoc_earlycons = { 129 .cn_putc = mvsoc_cnputc, 130 .cn_getc = mvsoc_cngetc, 131 .cn_pollc = nullcnpollc, 132 }; 133 #endif 134 135 136 /* attributes */ 137 static struct { 138 int tag; 139 uint32_t attr; 140 uint32_t target; 141 } mvsoc_tags[] = { 142 { MARVELL_TAG_SDRAM_CS0, 143 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 144 { MARVELL_TAG_SDRAM_CS1, 145 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 146 { MARVELL_TAG_SDRAM_CS2, 147 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 148 { MARVELL_TAG_SDRAM_CS3, 149 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 150 151 #ifdef MARVELL_ATTR_AXI_DDR /* XXX */ 152 { MARVELL_TAG_AXI_CS0, 153 MARVELL_ATTR_AXI_DDR, MVSOC_UNITID_DDR }, 154 { MARVELL_TAG_AXI_CS1, 155 MARVELL_ATTR_AXI_DDR, MVSOC_UNITID_DDR }, 156 #endif 157 158 { MARVELL_TAG_DDR3_CS0, 159 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 160 { MARVELL_TAG_DDR3_CS1, 161 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 162 { MARVELL_TAG_DDR3_CS2, 163 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 164 { MARVELL_TAG_DDR3_CS3, 165 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 166 167 #if defined(ORION) 168 { ORION_TAG_DEVICE_CS0, 169 ORION_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 170 { ORION_TAG_DEVICE_CS1, 171 ORION_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 172 { ORION_TAG_DEVICE_CS2, 173 ORION_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 174 { ORION_TAG_DEVICE_BOOTCS, 175 ORION_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 176 { ORION_TAG_FLASH_CS, 177 ORION_ATTR_FLASH_CS, MVSOC_UNITID_DEVBUS }, 178 { ORION_TAG_PEX0_MEM, 179 ORION_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 180 { ORION_TAG_PEX0_IO, 181 ORION_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 182 { ORION_TAG_PEX1_MEM, 183 ORION_ATTR_PEX_MEM, ORION_UNITID_PEX1 }, 184 { ORION_TAG_PEX1_IO, 185 ORION_ATTR_PEX_IO, ORION_UNITID_PEX1 }, 186 { ORION_TAG_PCI_MEM, 187 ORION_ATTR_PCI_MEM, ORION_UNITID_PCI }, 188 { ORION_TAG_PCI_IO, 189 ORION_ATTR_PCI_IO, ORION_UNITID_PCI }, 190 { ORION_TAG_CRYPT, 191 ORION_ATTR_CRYPT, ORION_UNITID_CRYPT }, 192 #endif 193 194 #if defined(KIRKWOOD) 195 { KIRKWOOD_TAG_NAND, 196 KIRKWOOD_ATTR_NAND, MVSOC_UNITID_DEVBUS }, 197 { KIRKWOOD_TAG_SPI, 198 KIRKWOOD_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 199 { KIRKWOOD_TAG_BOOTROM, 200 KIRKWOOD_ATTR_BOOTROM, MVSOC_UNITID_DEVBUS }, 201 { KIRKWOOD_TAG_PEX_MEM, 202 KIRKWOOD_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 203 { KIRKWOOD_TAG_PEX_IO, 204 KIRKWOOD_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 205 { KIRKWOOD_TAG_PEX1_MEM, 206 KIRKWOOD_ATTR_PEX1_MEM, MVSOC_UNITID_PEX }, 207 { KIRKWOOD_TAG_PEX1_IO, 208 KIRKWOOD_ATTR_PEX1_IO, MVSOC_UNITID_PEX }, 209 { KIRKWOOD_TAG_CRYPT, 210 KIRKWOOD_ATTR_CRYPT, KIRKWOOD_UNITID_CRYPT }, 211 #endif 212 213 #if defined(MV78XX0) 214 { MV78XX0_TAG_DEVICE_CS0, 215 MV78XX0_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 216 { MV78XX0_TAG_DEVICE_CS1, 217 MV78XX0_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 218 { MV78XX0_TAG_DEVICE_CS2, 219 MV78XX0_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 220 { MV78XX0_TAG_DEVICE_CS3, 221 MV78XX0_ATTR_DEVICE_CS3, MVSOC_UNITID_DEVBUS }, 222 { MV78XX0_TAG_DEVICE_BOOTCS, 223 MV78XX0_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 224 { MV78XX0_TAG_SPI, 225 MV78XX0_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 226 { MV78XX0_TAG_PEX0_MEM, 227 MV78XX0_ATTR_PEX_0_MEM, MVSOC_UNITID_PEX }, 228 { MV78XX0_TAG_PEX01_MEM, 229 MV78XX0_ATTR_PEX_1_MEM, MVSOC_UNITID_PEX }, 230 { MV78XX0_TAG_PEX02_MEM, 231 MV78XX0_ATTR_PEX_2_MEM, MVSOC_UNITID_PEX }, 232 { MV78XX0_TAG_PEX03_MEM, 233 MV78XX0_ATTR_PEX_3_MEM, MVSOC_UNITID_PEX }, 234 { MV78XX0_TAG_PEX0_IO, 235 MV78XX0_ATTR_PEX_0_IO, MVSOC_UNITID_PEX }, 236 { MV78XX0_TAG_PEX01_IO, 237 MV78XX0_ATTR_PEX_1_IO, MVSOC_UNITID_PEX }, 238 { MV78XX0_TAG_PEX02_IO, 239 MV78XX0_ATTR_PEX_2_IO, MVSOC_UNITID_PEX }, 240 { MV78XX0_TAG_PEX03_IO, 241 MV78XX0_ATTR_PEX_3_IO, MVSOC_UNITID_PEX }, 242 { MV78XX0_TAG_PEX1_MEM, 243 MV78XX0_ATTR_PEX_0_MEM, MV78XX0_UNITID_PEX1 }, 244 { MV78XX0_TAG_PEX11_MEM, 245 MV78XX0_ATTR_PEX_1_MEM, MV78XX0_UNITID_PEX1 }, 246 { MV78XX0_TAG_PEX12_MEM, 247 MV78XX0_ATTR_PEX_2_MEM, MV78XX0_UNITID_PEX1 }, 248 { MV78XX0_TAG_PEX13_MEM, 249 MV78XX0_ATTR_PEX_3_MEM, MV78XX0_UNITID_PEX1 }, 250 { MV78XX0_TAG_PEX1_IO, 251 MV78XX0_ATTR_PEX_0_IO, MV78XX0_UNITID_PEX1 }, 252 { MV78XX0_TAG_PEX11_IO, 253 MV78XX0_ATTR_PEX_1_IO, MV78XX0_UNITID_PEX1 }, 254 { MV78XX0_TAG_PEX12_IO, 255 MV78XX0_ATTR_PEX_2_IO, MV78XX0_UNITID_PEX1 }, 256 { MV78XX0_TAG_PEX13_IO, 257 MV78XX0_ATTR_PEX_3_IO, MV78XX0_UNITID_PEX1 }, 258 { MV78XX0_TAG_CRYPT, 259 MV78XX0_ATTR_CRYPT, MV78XX0_UNITID_CRYPT }, 260 #endif 261 262 #if defined(DOVE) 263 { DOVE_TAG_PEX0_MEM, 264 DOVE_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 265 { DOVE_TAG_PEX0_IO, 266 DOVE_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 267 { DOVE_TAG_PEX1_MEM, 268 DOVE_ATTR_PEX_MEM, DOVE_UNITID_PEX1 }, 269 { DOVE_TAG_PEX1_IO, 270 DOVE_ATTR_PEX_IO, DOVE_UNITID_PEX1 }, 271 { DOVE_TAG_CRYPT, 272 DOVE_ATTR_SA, DOVE_UNITID_SA }, 273 { DOVE_TAG_SPI0, 274 DOVE_ATTR_SPI0, MVSOC_UNITID_DEVBUS }, 275 { DOVE_TAG_SPI1, 276 DOVE_ATTR_SPI1, MVSOC_UNITID_DEVBUS }, 277 { DOVE_TAG_BOOTROM, 278 DOVE_ATTR_BOOTROM, MVSOC_UNITID_DEVBUS }, 279 { DOVE_TAG_PMU, 280 DOVE_ATTR_NAND, DOVE_UNITID_NAND }, 281 { DOVE_TAG_PMU, 282 DOVE_ATTR_PMU, DOVE_UNITID_PMU }, 283 #endif 284 285 #if defined(ARMADAXP) 286 { ARMADAXP_TAG_PEX00_MEM, 287 ARMADAXP_ATTR_PEXx0_MEM, ARMADAXP_UNITID_PEX0 }, 288 { ARMADAXP_TAG_PEX00_IO, 289 ARMADAXP_ATTR_PEXx0_IO, ARMADAXP_UNITID_PEX0 }, 290 { ARMADAXP_TAG_PEX01_MEM, 291 ARMADAXP_ATTR_PEXx1_MEM, ARMADAXP_UNITID_PEX0 }, 292 { ARMADAXP_TAG_PEX01_IO, 293 ARMADAXP_ATTR_PEXx1_IO, ARMADAXP_UNITID_PEX0 }, 294 { ARMADAXP_TAG_PEX02_MEM, 295 ARMADAXP_ATTR_PEXx2_MEM, ARMADAXP_UNITID_PEX0 }, 296 { ARMADAXP_TAG_PEX02_IO, 297 ARMADAXP_ATTR_PEXx2_IO, ARMADAXP_UNITID_PEX0 }, 298 { ARMADAXP_TAG_PEX03_MEM, 299 ARMADAXP_ATTR_PEXx3_MEM, ARMADAXP_UNITID_PEX0 }, 300 { ARMADAXP_TAG_PEX03_IO, 301 ARMADAXP_ATTR_PEXx3_IO, ARMADAXP_UNITID_PEX0 }, 302 { ARMADAXP_TAG_PEX2_MEM, 303 ARMADAXP_ATTR_PEX2_MEM, ARMADAXP_UNITID_PEX2 }, 304 { ARMADAXP_TAG_PEX2_IO, 305 ARMADAXP_ATTR_PEX2_IO, ARMADAXP_UNITID_PEX2 }, 306 { ARMADAXP_TAG_PEX3_MEM, 307 ARMADAXP_ATTR_PEX3_MEM, ARMADAXP_UNITID_PEX3 }, 308 { ARMADAXP_TAG_PEX3_IO, 309 ARMADAXP_ATTR_PEX3_IO, ARMADAXP_UNITID_PEX3 }, 310 { ARMADAXP_TAG_CRYPT0, 311 ARMADAXP_ATTR_CRYPT0_NOSWAP, ARMADAXP_UNITID_CRYPT }, 312 { ARMADAXP_TAG_CRYPT1, 313 ARMADAXP_ATTR_CRYPT1_NOSWAP, ARMADAXP_UNITID_CRYPT }, 314 #endif 315 }; 316 317 #if defined(ORION) 318 #define ORION_1(m) MARVELL_ORION_1_ ## m 319 #define ORION_2(m) MARVELL_ORION_2_ ## m 320 #endif 321 #if defined(KIRKWOOD) 322 #undef KIRKWOOD 323 #define KIRKWOOD(m) MARVELL_KIRKWOOD_ ## m 324 #endif 325 #if defined(MV78XX0) 326 #undef MV78XX0 327 #define MV78XX0(m) MARVELL_MV78XX0_ ## m 328 #endif 329 #if defined(DOVE) 330 #undef DOVE 331 #define DOVE(m) MARVELL_DOVE_ ## m 332 #endif 333 #if defined(ARMADAXP) 334 #undef ARMADAXP 335 #define ARMADAXP(m) MARVELL_ARMADAXP_ ## m 336 #define ARMADA370(m) MARVELL_ARMADA370_ ## m 337 #endif 338 static struct { 339 uint16_t model; 340 uint8_t rev; 341 const char *modelstr; 342 const char *revstr; 343 const char *typestr; 344 } nametbl[] = { 345 #if defined(ORION) 346 { ORION_1(88F1181), 0, "MV88F1181", NULL, "Orion1" }, 347 { ORION_1(88F5082), 2, "MV88F5082", "A2", "Orion1" }, 348 { ORION_1(88F5180N), 3, "MV88F5180N","B1", "Orion1" }, 349 { ORION_1(88F5181), 0, "MV88F5181", "A0", "Orion1" }, 350 { ORION_1(88F5181), 1, "MV88F5181", "A1", "Orion1" }, 351 { ORION_1(88F5181), 2, "MV88F5181", "B0", "Orion1" }, 352 { ORION_1(88F5181), 3, "MV88F5181", "B1", "Orion1" }, 353 { ORION_1(88F5181), 8, "MV88F5181L","A0", "Orion1" }, 354 { ORION_1(88F5181), 9, "MV88F5181L","A1", "Orion1" }, 355 { ORION_1(88F5182), 0, "MV88F5182", "A0", "Orion1" }, 356 { ORION_1(88F5182), 1, "MV88F5182", "A1", "Orion1" }, 357 { ORION_1(88F5182), 2, "MV88F5182", "A2", "Orion1" }, 358 { ORION_1(88F6082), 0, "MV88F6082", "A0", "Orion1" }, 359 { ORION_1(88F6082), 1, "MV88F6082", "A1", "Orion1" }, 360 { ORION_1(88F6183), 0, "MV88F6183", "A0", "Orion1" }, 361 { ORION_1(88F6183), 1, "MV88F6183", "Z0", "Orion1" }, 362 { ORION_1(88W8660), 0, "MV88W8660", "A0", "Orion1" }, 363 { ORION_1(88W8660), 1, "MV88W8660", "A1", "Orion1" }, 364 365 { ORION_2(88F1281), 0, "MV88F1281", "A0", "Orion2" }, 366 { ORION_2(88F5281), 0, "MV88F5281", "A0", "Orion2" }, 367 { ORION_2(88F5281), 1, "MV88F5281", "B0", "Orion2" }, 368 { ORION_2(88F5281), 2, "MV88F5281", "C0", "Orion2" }, 369 { ORION_2(88F5281), 3, "MV88F5281", "C1", "Orion2" }, 370 { ORION_2(88F5281), 4, "MV88F5281", "D0", "Orion2" }, 371 #endif 372 373 #if defined(KIRKWOOD) 374 { KIRKWOOD(88F6180), 2, "88F6180", "A0", "Kirkwood" }, 375 { KIRKWOOD(88F6180), 3, "88F6180", "A1", "Kirkwood" }, 376 { KIRKWOOD(88F6192), 0, "88F619x", "Z0", "Kirkwood" }, 377 { KIRKWOOD(88F6192), 2, "88F619x", "A0", "Kirkwood" }, 378 { KIRKWOOD(88F6192), 3, "88F619x", "A1", "Kirkwood" }, 379 { KIRKWOOD(88F6281), 0, "88F6281", "Z0", "Kirkwood" }, 380 { KIRKWOOD(88F6281), 2, "88F6281", "A0", "Kirkwood" }, 381 { KIRKWOOD(88F6281), 3, "88F6281", "A1", "Kirkwood" }, 382 { KIRKWOOD(88F6282), 0, "88F6282", "A0", "Kirkwood" }, 383 { KIRKWOOD(88F6282), 1, "88F6282", "A1", "Kirkwood" }, 384 #endif 385 386 #if defined(MV78XX0) 387 { MV78XX0(MV78100), 1, "MV78100", "A0", "Discovery Innovation" }, 388 { MV78XX0(MV78100), 2, "MV78100", "A1", "Discovery Innovation" }, 389 { MV78XX0(MV78200), 1, "MV78200", "A0", "Discovery Innovation" }, 390 #endif 391 392 #if defined(DOVE) 393 { DOVE(88AP510), 0, "88AP510", "Z0", "Dove" }, 394 { DOVE(88AP510), 1, "88AP510", "Z1", "Dove" }, 395 { DOVE(88AP510), 2, "88AP510", "Y0", "Dove" }, 396 { DOVE(88AP510), 3, "88AP510", "Y1", "Dove" }, 397 { DOVE(88AP510), 4, "88AP510", "X0", "Dove" }, 398 { DOVE(88AP510), 6, "88AP510", "A0", "Dove" }, 399 { DOVE(88AP510), 7, "88AP510", "A1", "Dove" }, 400 #endif 401 402 #if defined(ARMADAXP) 403 { ARMADAXP(MV78130), 1, "MV78130", "A0", "Armada XP" }, 404 { ARMADAXP(MV78160), 1, "MV78160", "A0", "Armada XP" }, 405 { ARMADAXP(MV78230), 1, "MV78260", "A0", "Armada XP" }, 406 { ARMADAXP(MV78260), 1, "MV78260", "A0", "Armada XP" }, 407 { ARMADAXP(MV78260), 2, "MV78260", "B0", "Armada XP" }, 408 { ARMADAXP(MV78460), 1, "MV78460", "A0", "Armada XP" }, 409 { ARMADAXP(MV78460), 2, "MV78460", "B0", "Armada XP" }, 410 411 { ARMADA370(MV6707), 0, "MV6707", "A0", "Armada 370" }, 412 { ARMADA370(MV6707), 1, "MV6707", "A1", "Armada 370" }, 413 { ARMADA370(MV6710), 0, "MV6710", "A0", "Armada 370" }, 414 { ARMADA370(MV6710), 1, "MV6710", "A1", "Armada 370" }, 415 { ARMADA370(MV6W11), 0, "MV6W11", "A0", "Armada 370" }, 416 { ARMADA370(MV6W11), 1, "MV6W11", "A1", "Armada 370" }, 417 #endif 418 }; 419 420 enum marvell_tags ddr_tags[] = { 421 MARVELL_TAG_SDRAM_CS0, 422 MARVELL_TAG_SDRAM_CS1, 423 MARVELL_TAG_SDRAM_CS2, 424 MARVELL_TAG_SDRAM_CS3, 425 426 MARVELL_TAG_UNDEFINED 427 }; 428 enum marvell_tags ddr3_tags[] = { 429 MARVELL_TAG_DDR3_CS0, 430 MARVELL_TAG_DDR3_CS1, 431 MARVELL_TAG_DDR3_CS2, 432 MARVELL_TAG_DDR3_CS3, 433 434 MARVELL_TAG_UNDEFINED 435 }; 436 enum marvell_tags axi_tags[] = { 437 MARVELL_TAG_AXI_CS0, 438 MARVELL_TAG_AXI_CS1, 439 440 MARVELL_TAG_UNDEFINED 441 }; 442 static struct { 443 uint16_t model; 444 uint8_t rev; 445 enum marvell_tags *tags; 446 } tagstbl[] = { 447 #if defined(ORION) 448 { ORION_1(88F1181), 0, ddr_tags }, 449 { ORION_1(88F5082), 2, ddr_tags }, 450 { ORION_1(88F5180N), 3, ddr_tags }, 451 { ORION_1(88F5181), 0, ddr_tags }, 452 { ORION_1(88F5181), 1, ddr_tags }, 453 { ORION_1(88F5181), 2, ddr_tags }, 454 { ORION_1(88F5181), 3, ddr_tags }, 455 { ORION_1(88F5181), 8, ddr_tags }, 456 { ORION_1(88F5181), 9, ddr_tags }, 457 { ORION_1(88F5182), 0, ddr_tags }, 458 { ORION_1(88F5182), 1, ddr_tags }, 459 { ORION_1(88F5182), 2, ddr_tags }, 460 { ORION_1(88F6082), 0, ddr_tags }, 461 { ORION_1(88F6082), 1, ddr_tags }, 462 { ORION_1(88F6183), 0, ddr_tags }, 463 { ORION_1(88F6183), 1, ddr_tags }, 464 { ORION_1(88W8660), 0, ddr_tags }, 465 { ORION_1(88W8660), 1, ddr_tags }, 466 467 { ORION_2(88F1281), 0, ddr_tags }, 468 { ORION_2(88F5281), 0, ddr_tags }, 469 { ORION_2(88F5281), 1, ddr_tags }, 470 { ORION_2(88F5281), 2, ddr_tags }, 471 { ORION_2(88F5281), 3, ddr_tags }, 472 { ORION_2(88F5281), 4, ddr_tags }, 473 #endif 474 475 #if defined(KIRKWOOD) 476 { KIRKWOOD(88F6180), 2, ddr_tags }, 477 { KIRKWOOD(88F6180), 3, ddr_tags }, 478 { KIRKWOOD(88F6192), 0, ddr_tags }, 479 { KIRKWOOD(88F6192), 2, ddr_tags }, 480 { KIRKWOOD(88F6192), 3, ddr_tags }, 481 { KIRKWOOD(88F6281), 0, ddr_tags }, 482 { KIRKWOOD(88F6281), 2, ddr_tags }, 483 { KIRKWOOD(88F6281), 3, ddr_tags }, 484 { KIRKWOOD(88F6282), 0, ddr_tags }, 485 { KIRKWOOD(88F6282), 1, ddr_tags }, 486 #endif 487 488 #if defined(MV78XX0) 489 { MV78XX0(MV78100), 1, ddr_tags }, 490 { MV78XX0(MV78100), 2, ddr_tags }, 491 { MV78XX0(MV78200), 1, ddr_tags }, 492 #endif 493 494 #if defined(DOVE) 495 { DOVE(88AP510), 0, axi_tags }, 496 { DOVE(88AP510), 1, axi_tags }, 497 { DOVE(88AP510), 2, axi_tags }, 498 { DOVE(88AP510), 3, axi_tags }, 499 { DOVE(88AP510), 4, axi_tags }, 500 { DOVE(88AP510), 5, axi_tags }, 501 { DOVE(88AP510), 6, axi_tags }, 502 { DOVE(88AP510), 7, axi_tags }, 503 #endif 504 505 #if defined(ARMADAXP) 506 { ARMADAXP(MV78130), 1, ddr3_tags }, 507 { ARMADAXP(MV78160), 1, ddr3_tags }, 508 { ARMADAXP(MV78230), 1, ddr3_tags }, 509 { ARMADAXP(MV78260), 1, ddr3_tags }, 510 { ARMADAXP(MV78260), 2, ddr3_tags }, 511 { ARMADAXP(MV78460), 1, ddr3_tags }, 512 { ARMADAXP(MV78460), 2, ddr3_tags }, 513 514 { ARMADA370(MV6707), 0, ddr3_tags }, 515 { ARMADA370(MV6707), 1, ddr3_tags }, 516 { ARMADA370(MV6710), 0, ddr3_tags }, 517 { ARMADA370(MV6710), 1, ddr3_tags }, 518 { ARMADA370(MV6W11), 0, ddr3_tags }, 519 { ARMADA370(MV6W11), 1, ddr3_tags }, 520 #endif 521 }; 522 523 524 #define OFFSET_DEFAULT MVA_OFFSET_DEFAULT 525 #define IRQ_DEFAULT MVA_IRQ_DEFAULT 526 static const struct mvsoc_periph { 527 int model; 528 const char *name; 529 int unit; 530 bus_size_t offset; 531 int irq; 532 } mvsoc_periphs[] = { 533 #if defined(ORION) 534 #define ORION_IRQ_TMR (32 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 535 536 { ORION_1(88F1181), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 537 { ORION_1(88F1181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 538 { ORION_1(88F1181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 539 { ORION_1(88F1181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 540 { ORION_1(88F1181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 541 { ORION_1(88F1181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 542 { ORION_1(88F1181), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 543 544 { ORION_1(88F5082), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 545 { ORION_1(88F5082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 546 { ORION_1(88F5082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 547 { ORION_1(88F5082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 548 { ORION_1(88F5082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 549 { ORION_1(88F5082), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 550 { ORION_1(88F5082), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 551 { ORION_1(88F5082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 552 { ORION_1(88F5082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 553 { ORION_1(88F5082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 554 { ORION_1(88F5082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 555 { ORION_1(88F5082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 556 557 { ORION_1(88F5180N),"mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 558 { ORION_1(88F5180N),"mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 559 { ORION_1(88F5180N),"com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 560 { ORION_1(88F5180N),"com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 561 { ORION_1(88F5180N),"ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 562 { ORION_1(88F5180N),"gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 563 { ORION_1(88F5180N),"gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 564 { ORION_1(88F5180N),"gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 565 { ORION_1(88F5180N),"mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 566 { ORION_1(88F5180N),"mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 567 568 { ORION_1(88F5181), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 569 { ORION_1(88F5181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 570 { ORION_1(88F5181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 571 { ORION_1(88F5181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 572 { ORION_1(88F5181), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 573 { ORION_1(88F5181), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 574 { ORION_1(88F5181), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 575 { ORION_1(88F5181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 576 { ORION_1(88F5181), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 577 { ORION_1(88F5181), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 578 { ORION_1(88F5181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 579 580 { ORION_1(88F5182), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 581 { ORION_1(88F5182), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 582 { ORION_1(88F5182), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 583 { ORION_1(88F5182), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 584 { ORION_1(88F5182), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 585 { ORION_1(88F5182), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 586 { ORION_1(88F5182), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 587 { ORION_1(88F5182), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 588 { ORION_1(88F5182), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 589 { ORION_1(88F5182), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 590 { ORION_1(88F5182), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 591 { ORION_1(88F5182), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 592 593 { ORION_1(88F6082), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 594 { ORION_1(88F6082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 595 { ORION_1(88F6082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 596 { ORION_1(88F6082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 597 { ORION_1(88F6082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 598 { ORION_1(88F6082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 599 { ORION_1(88F6082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 600 { ORION_1(88F6082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 601 { ORION_1(88F6082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 602 { ORION_1(88F6082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 603 604 { ORION_1(88F6183), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 605 { ORION_1(88F6183), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 606 { ORION_1(88F6183), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 607 { ORION_1(88F6183), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 608 609 { ORION_1(88W8660), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 610 { ORION_1(88W8660), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 611 { ORION_1(88W8660), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 612 { ORION_1(88W8660), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 613 { ORION_1(88W8660), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 614 { ORION_1(88W8660), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 615 { ORION_1(88W8660), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 616 { ORION_1(88W8660), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 617 { ORION_1(88W8660), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 618 { ORION_1(88W8660), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 619 620 { ORION_2(88F1281), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 621 { ORION_2(88F1281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 622 { ORION_2(88F1281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 623 { ORION_2(88F1281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 624 { ORION_2(88F1281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 625 { ORION_2(88F1281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 626 { ORION_2(88F1281), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 627 628 { ORION_2(88F5281), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 629 { ORION_2(88F5281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 630 { ORION_2(88F5281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 631 { ORION_2(88F5281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 632 { ORION_2(88F5281), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 633 { ORION_2(88F5281), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 634 { ORION_2(88F5281), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 635 { ORION_2(88F5281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 636 { ORION_2(88F5281), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 637 { ORION_2(88F5281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 638 #endif 639 640 #if defined(KIRKWOOD) 641 #define KIRKWOOD_IRQ_TMR (64 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 642 643 { KIRKWOOD(88F6180),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 644 { KIRKWOOD(88F6180),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 645 { KIRKWOOD(88F6180),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 646 { KIRKWOOD(88F6180),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 647 { KIRKWOOD(88F6180),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 648 { KIRKWOOD(88F6180),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 649 { KIRKWOOD(88F6180),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 650 { KIRKWOOD(88F6180),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 651 { KIRKWOOD(88F6180),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 652 { KIRKWOOD(88F6180),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 653 { KIRKWOOD(88F6180),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 654 { KIRKWOOD(88F6180),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 655 656 { KIRKWOOD(88F6192),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 657 { KIRKWOOD(88F6192),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 658 { KIRKWOOD(88F6192),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 659 { KIRKWOOD(88F6192),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 660 { KIRKWOOD(88F6192),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 661 { KIRKWOOD(88F6192),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 662 { KIRKWOOD(88F6192),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 663 { KIRKWOOD(88F6192),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 664 { KIRKWOOD(88F6192),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 665 { KIRKWOOD(88F6192),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 666 { KIRKWOOD(88F6192),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 667 { KIRKWOOD(88F6192),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 668 { KIRKWOOD(88F6192),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 669 { KIRKWOOD(88F6192),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 670 671 { KIRKWOOD(88F6281),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 672 { KIRKWOOD(88F6281),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 673 { KIRKWOOD(88F6281),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 674 { KIRKWOOD(88F6281),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 675 { KIRKWOOD(88F6281),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 676 { KIRKWOOD(88F6281),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 677 { KIRKWOOD(88F6281),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 678 { KIRKWOOD(88F6281),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 679 { KIRKWOOD(88F6281),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT }, 680 { KIRKWOOD(88F6281),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 681 { KIRKWOOD(88F6281),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 682 { KIRKWOOD(88F6281),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 683 { KIRKWOOD(88F6281),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 684 { KIRKWOOD(88F6281),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 685 686 { KIRKWOOD(88F6282),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 687 { KIRKWOOD(88F6282),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 688 { KIRKWOOD(88F6282),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 689 { KIRKWOOD(88F6282),"mvsocts", 0, KIRKWOOD_TS_BASE, IRQ_DEFAULT }, 690 { KIRKWOOD(88F6282),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 691 { KIRKWOOD(88F6282),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 692 { KIRKWOOD(88F6282),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 693 { KIRKWOOD(88F6282),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 694 { KIRKWOOD(88F6282),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 695 { KIRKWOOD(88F6282),"gttwsi", 1, KIRKWOOD_TWSI1_BASE,KIRKWOOD_IRQ_TWSI1 }, 696 { KIRKWOOD(88F6282),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 697 { KIRKWOOD(88F6282),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 698 { KIRKWOOD(88F6282),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 699 { KIRKWOOD(88F6282),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 700 { KIRKWOOD(88F6282),"mvpex", 1, KIRKWOOD_PEX1_BASE,KIRKWOOD_IRQ_PEX1INT }, 701 { KIRKWOOD(88F6282),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 702 { KIRKWOOD(88F6282),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 703 #endif 704 705 #if defined(MV78XX0) 706 { MV78XX0(MV78100), "mvsoctmr",0, MVSOC_TMR_BASE, MV78XX0_IRQ_TIMER0 }, 707 { MV78XX0(MV78100), "mvsocgpp",0, MVSOC_GPP_BASE, MV78XX0_IRQ_GPIO0_7 }, 708 { MV78XX0(MV78100), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0 }, 709 { MV78XX0(MV78100), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1 }, 710 { MV78XX0(MV78100), "com", 2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 }, 711 { MV78XX0(MV78100), "com", 3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 }, 712 { MV78XX0(MV78100), "gttwsi", 0, MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI0 }, 713 { MV78XX0(MV78100), "gttwsi", 1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 }, 714 { MV78XX0(MV78100), "mvgbec", 0, MV78XX0_GBE0_BASE,IRQ_DEFAULT }, 715 { MV78XX0(MV78100), "mvgbec", 1, MV78XX0_GBE1_BASE,IRQ_DEFAULT }, 716 { MV78XX0(MV78100), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA }, 717 718 { MV78XX0(MV78200), "mvsoctmr",0, MVSOC_TMR_BASE, MV78XX0_IRQ_TIMER0 }, 719 { MV78XX0(MV78200), "mvsocgpp",0, MVSOC_GPP_BASE, MV78XX0_IRQ_GPIO0_7 }, 720 { MV78XX0(MV78200), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0 }, 721 { MV78XX0(MV78200), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1 }, 722 { MV78XX0(MV78200), "com", 2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 }, 723 { MV78XX0(MV78200), "com", 3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 }, 724 { MV78XX0(MV78200), "gttwsi", 0, MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI0 }, 725 { MV78XX0(MV78200), "gttwsi", 1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 }, 726 { MV78XX0(MV78200), "mvgbec", 0, MV78XX0_GBE0_BASE,IRQ_DEFAULT }, 727 { MV78XX0(MV78200), "mvgbec", 1, MV78XX0_GBE1_BASE,IRQ_DEFAULT }, 728 { MV78XX0(MV78200), "mvgbec", 2, MV78XX0_GBE2_BASE,IRQ_DEFAULT }, 729 { MV78XX0(MV78200), "mvgbec", 3, MV78XX0_GBE3_BASE,IRQ_DEFAULT }, 730 { MV78XX0(MV78200), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA }, 731 #endif 732 733 #if defined(DOVE) 734 #define DOVE_IRQ_TMR (64 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 735 736 { DOVE(88AP510), "mvsoctmr",0, MVSOC_TMR_BASE, DOVE_IRQ_TMR }, 737 { DOVE(88AP510), "mvsocpmu",0, DOVE_PMU_BASE, DOVE_IRQ_PMU }, 738 { DOVE(88AP510), "com", 0, MVSOC_COM0_BASE, DOVE_IRQ_UART0 }, 739 { DOVE(88AP510), "com", 1, MVSOC_COM1_BASE, DOVE_IRQ_UART1 }, 740 { DOVE(88AP510), "com", 2, DOVE_COM2_BASE, DOVE_IRQ_UART2 }, 741 { DOVE(88AP510), "com", 3, DOVE_COM3_BASE, DOVE_IRQ_UART3 }, 742 { DOVE(88AP510), "gttwsi", 0, MVSOC_TWSI_BASE, DOVE_IRQ_TWSI }, 743 { DOVE(88AP510), "mvspi", 0, DOVE_SPI0_BASE, DOVE_IRQ_SPI0 }, 744 { DOVE(88AP510), "mvspi", 1, DOVE_SPI1_BASE, DOVE_IRQ_SPI1 }, 745 { DOVE(88AP510), "mvcesa", 0, DOVE_CESA_BASE, DOVE_IRQ_SECURITYINT }, 746 { DOVE(88AP510), "ehci", 0, DOVE_USB0_BASE, DOVE_IRQ_USB0CNT }, 747 { DOVE(88AP510), "ehci", 1, DOVE_USB1_BASE, DOVE_IRQ_USB1CNT }, 748 { DOVE(88AP510), "gtidmac", 0, DOVE_XORE_BASE, IRQ_DEFAULT }, 749 { DOVE(88AP510), "mvgbec", 0, DOVE_GBE_BASE, IRQ_DEFAULT }, 750 { DOVE(88AP510), "mvpex", 0, MVSOC_PEX_BASE, DOVE_IRQ_PEX0_INT }, 751 { DOVE(88AP510), "mvpex", 1, DOVE_PEX1_BASE, DOVE_IRQ_PEX1_INT }, 752 { DOVE(88AP510), "sdhc", 0, DOVE_SDHC0_BASE, DOVE_IRQ_SD0 }, 753 { DOVE(88AP510), "sdhc", 1, DOVE_SDHC1_BASE, DOVE_IRQ_SD1 }, 754 { DOVE(88AP510), "mvsata", 0, DOVE_SATAHC_BASE, DOVE_IRQ_SATAINT }, 755 // { DOVE(88AP510), "mvsocgpp",0, MVSOC_GPP_BASE, IRQ_DEFAULT }, 756 { DOVE(88AP510), "mvsocrtc",0, DOVE_RTC_BASE, IRQ_DEFAULT }, 757 #endif 758 759 #if defined(ARMADAXP) 760 { ARMADAXP(MV78130), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 761 { ARMADAXP(MV78130), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 762 { ARMADAXP(MV78130), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 763 { ARMADAXP(MV78130), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 764 { ARMADAXP(MV78130), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 765 { ARMADAXP(MV78130), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 766 { ARMADAXP(MV78130), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 767 { ARMADAXP(MV78130), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 768 { ARMADAXP(MV78130), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 769 { ARMADAXP(MV78130), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 770 { ARMADAXP(MV78130), "mvsocts",0, ARMADAXP_TS_BASE, ARMADAXP_IRQ_PMU }, 771 { ARMADAXP(MV78130), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 772 { ARMADAXP(MV78130), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 773 { ARMADAXP(MV78130), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 774 { ARMADAXP(MV78130), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 775 { ARMADAXP(MV78130), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 776 { ARMADAXP(MV78130), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 777 { ARMADAXP(MV78130), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 778 { ARMADAXP(MV78130), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 779 { ARMADAXP(MV78130), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 780 { ARMADAXP(MV78130), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 781 { ARMADAXP(MV78130), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 782 #if NMVXPE > 0 783 { ARMADAXP(MV78130), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 784 { ARMADAXP(MV78130), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 785 { ARMADAXP(MV78130), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 786 #else 787 { ARMADAXP(MV78130), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 788 { ARMADAXP(MV78130), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 789 #endif 790 #if NMVXPSEC > 0 791 { ARMADAXP(MV78130), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 792 { ARMADAXP(MV78130), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 }, 793 #else 794 { ARMADAXP(MV78130), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 795 { ARMADAXP(MV78130), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 796 #endif 797 798 { ARMADAXP(MV78160), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 799 { ARMADAXP(MV78160), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 800 { ARMADAXP(MV78160), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 801 { ARMADAXP(MV78160), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 802 { ARMADAXP(MV78160), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 803 { ARMADAXP(MV78160), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 804 { ARMADAXP(MV78160), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 805 { ARMADAXP(MV78160), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 806 { ARMADAXP(MV78160), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 807 { ARMADAXP(MV78160), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 808 { ARMADAXP(MV78160), "mvsocts",0, ARMADAXP_TS_BASE, ARMADAXP_IRQ_PMU }, 809 { ARMADAXP(MV78160), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 810 { ARMADAXP(MV78160), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 811 { ARMADAXP(MV78160), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 812 { ARMADAXP(MV78160), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 813 { ARMADAXP(MV78160), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 814 { ARMADAXP(MV78160), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 815 { ARMADAXP(MV78160), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 816 { ARMADAXP(MV78160), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 817 { ARMADAXP(MV78160), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 818 { ARMADAXP(MV78160), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 819 { ARMADAXP(MV78160), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 820 #if NMVXPE > 0 821 { ARMADAXP(MV78160), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 822 { ARMADAXP(MV78160), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 823 { ARMADAXP(MV78160), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 824 { ARMADAXP(MV78160), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 825 { ARMADAXP(MV78160), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX }, 826 #else 827 { ARMADAXP(MV78160), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 828 { ARMADAXP(MV78160), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 829 { ARMADAXP(MV78160), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 830 { ARMADAXP(MV78160), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 831 #endif 832 #if NMVXPSEC > 0 833 { ARMADAXP(MV78160), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 834 { ARMADAXP(MV78160), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 }, 835 #else 836 { ARMADAXP(MV78160), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 837 { ARMADAXP(MV78160), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 838 #endif 839 840 { ARMADAXP(MV78230), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 841 { ARMADAXP(MV78230), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 842 { ARMADAXP(MV78230), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 843 { ARMADAXP(MV78230), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 844 { ARMADAXP(MV78230), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 845 { ARMADAXP(MV78230), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 846 { ARMADAXP(MV78230), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 847 { ARMADAXP(MV78230), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 848 { ARMADAXP(MV78230), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 849 { ARMADAXP(MV78230), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 850 { ARMADAXP(MV78230), "mvsocts",0, ARMADAXP_TS_BASE, ARMADAXP_IRQ_PMU }, 851 { ARMADAXP(MV78230), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 852 { ARMADAXP(MV78230), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 853 { ARMADAXP(MV78230), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 854 { ARMADAXP(MV78230), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 855 { ARMADAXP(MV78230), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 856 { ARMADAXP(MV78230), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 857 { ARMADAXP(MV78230), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 858 { ARMADAXP(MV78230), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 859 { ARMADAXP(MV78230), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 860 { ARMADAXP(MV78230), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 861 { ARMADAXP(MV78230), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 862 #if NMVXPE > 0 863 { ARMADAXP(MV78230), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 864 { ARMADAXP(MV78230), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 865 { ARMADAXP(MV78230), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 866 { ARMADAXP(MV78230), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 867 #else 868 { ARMADAXP(MV78230), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 869 { ARMADAXP(MV78230), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 870 { ARMADAXP(MV78230), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 871 #endif 872 #if NMVXPSEC > 0 873 { ARMADAXP(MV78230), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 874 { ARMADAXP(MV78230), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 }, 875 #else 876 { ARMADAXP(MV78230), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 877 { ARMADAXP(MV78230), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 878 #endif 879 880 { ARMADAXP(MV78260), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 881 { ARMADAXP(MV78260), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 882 { ARMADAXP(MV78260), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 883 { ARMADAXP(MV78260), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 884 { ARMADAXP(MV78260), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 885 { ARMADAXP(MV78260), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 886 { ARMADAXP(MV78260), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 887 { ARMADAXP(MV78260), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 888 { ARMADAXP(MV78260), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 889 { ARMADAXP(MV78260), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 890 { ARMADAXP(MV78260), "mvsocts",0, ARMADAXP_TS_BASE, ARMADAXP_IRQ_PMU }, 891 { ARMADAXP(MV78260), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 892 { ARMADAXP(MV78260), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 893 { ARMADAXP(MV78260), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 894 { ARMADAXP(MV78260), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 895 { ARMADAXP(MV78260), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 896 { ARMADAXP(MV78260), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 897 { ARMADAXP(MV78260), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 898 { ARMADAXP(MV78260), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 899 { ARMADAXP(MV78260), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 900 { ARMADAXP(MV78260), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 901 { ARMADAXP(MV78260), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 902 #if NMVXPE > 0 903 { ARMADAXP(MV78260), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 904 { ARMADAXP(MV78260), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 905 { ARMADAXP(MV78260), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 906 { ARMADAXP(MV78260), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 907 { ARMADAXP(MV78260), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX }, 908 #else 909 { ARMADAXP(MV78260), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 910 { ARMADAXP(MV78260), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 911 { ARMADAXP(MV78260), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 912 { ARMADAXP(MV78260), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 913 #endif 914 #if NMVXPSEC > 0 915 { ARMADAXP(MV78260), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 916 { ARMADAXP(MV78260), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 }, 917 #else 918 { ARMADAXP(MV78260), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 919 { ARMADAXP(MV78260), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 920 #endif 921 922 { ARMADAXP(MV78460), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 923 { ARMADAXP(MV78460), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 924 { ARMADAXP(MV78460), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 925 { ARMADAXP(MV78460), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 926 { ARMADAXP(MV78460), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 927 { ARMADAXP(MV78460), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 928 { ARMADAXP(MV78460), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 929 { ARMADAXP(MV78460), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 930 { ARMADAXP(MV78460), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 931 { ARMADAXP(MV78460), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 932 { ARMADAXP(MV78460), "mvsocts",0, ARMADAXP_TS_BASE, ARMADAXP_IRQ_PMU }, 933 { ARMADAXP(MV78460), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 934 { ARMADAXP(MV78460), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 935 { ARMADAXP(MV78460), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 936 { ARMADAXP(MV78460), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 937 { ARMADAXP(MV78460), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 938 { ARMADAXP(MV78460), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 939 { ARMADAXP(MV78460), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 940 { ARMADAXP(MV78460), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 941 { ARMADAXP(MV78460), "mvpex", 5, ARMADAXP_PEX3_BASE,ARMADAXP_IRQ_PEX3 }, 942 { ARMADAXP(MV78460), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 943 { ARMADAXP(MV78460), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 944 { ARMADAXP(MV78460), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 945 #if NMVXPE > 0 946 { ARMADAXP(MV78460), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 947 { ARMADAXP(MV78460), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 948 { ARMADAXP(MV78460), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 949 { ARMADAXP(MV78460), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 950 { ARMADAXP(MV78460), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX }, 951 #else 952 { ARMADAXP(MV78460), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 953 { ARMADAXP(MV78460), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 954 { ARMADAXP(MV78460), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 955 { ARMADAXP(MV78460), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 956 #endif 957 #if NMVXPSEC > 0 958 { ARMADAXP(MV78460), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 959 { ARMADAXP(MV78460), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 }, 960 #else 961 { ARMADAXP(MV78460), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 962 { ARMADAXP(MV78460), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 963 #endif 964 965 { ARMADA370(MV6710), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 966 { ARMADA370(MV6710), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 967 { ARMADA370(MV6710), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 968 { ARMADA370(MV6710), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 969 { ARMADA370(MV6710), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 970 { ARMADA370(MV6710), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 971 { ARMADA370(MV6710), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 972 { ARMADA370(MV6710), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 973 { ARMADA370(MV6710), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 974 { ARMADA370(MV6710), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 975 { ARMADA370(MV6710), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 976 { ARMADA370(MV6710), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 977 { ARMADA370(MV6710), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 978 { ARMADA370(MV6710), "mvspi", 1, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 979 { ARMADA370(MV6710), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 980 #if NMVXPE > 0 981 { ARMADA370(MV6710), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 982 { ARMADA370(MV6710), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 983 { ARMADA370(MV6710), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 984 #else 985 { ARMADA370(MV6710), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 986 { ARMADA370(MV6710), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 987 #endif 988 #if NMVXPSEC > 0 989 { ARMADA370(MV6710), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 990 #else 991 { ARMADA370(MV6710), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 992 #endif 993 #endif 994 }; 995 996 997 CFATTACH_DECL_NEW(mvsoc, sizeof(struct mvsoc_softc), 998 mvsoc_match, mvsoc_attach, NULL, NULL); 999 1000 /* ARGSUSED */ 1001 static int 1002 mvsoc_match(device_t parent, struct cfdata *match, void *aux) 1003 { 1004 1005 return 1; 1006 } 1007 1008 /* ARGSUSED */ 1009 static void 1010 mvsoc_attach(device_t parent, device_t self, void *aux) 1011 { 1012 struct mvsoc_softc *sc = device_private(self); 1013 struct marvell_attach_args mva; 1014 enum marvell_tags *tags; 1015 uint16_t model; 1016 uint8_t rev; 1017 int i; 1018 1019 sc->sc_dev = self; 1020 sc->sc_iot = &mvsoc_bs_tag; 1021 sc->sc_addr = vtophys(regbase); 1022 sc->sc_dmat = &mvsoc_bus_dma_tag; 1023 if (bus_space_map(sc->sc_iot, sc->sc_addr, 0x100000, 0, &sc->sc_ioh) != 1024 0) { 1025 aprint_error_dev(self, "can't map registers\n"); 1026 return; 1027 } 1028 1029 model = mvsoc_model(); 1030 rev = mvsoc_rev(); 1031 for (i = 0; i < __arraycount(nametbl); i++) 1032 if (nametbl[i].model == model && nametbl[i].rev == rev) 1033 break; 1034 if (i >= __arraycount(nametbl)) 1035 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 1036 1037 aprint_normal(": Marvell %s %s%s %s\n", 1038 nametbl[i].modelstr, 1039 nametbl[i].revstr != NULL ? "Rev. " : "", 1040 nametbl[i].revstr != NULL ? nametbl[i].revstr : "", 1041 nametbl[i].typestr); 1042 aprint_normal("%s: CPU Clock %d.%03d MHz" 1043 " SysClock %d.%03d MHz TClock %d.%03d MHz\n", 1044 device_xname(self), 1045 mvPclk / 1000000, (mvPclk / 1000) % 1000, 1046 mvSysclk / 1000000, (mvSysclk / 1000) % 1000, 1047 mvTclk / 1000000, (mvTclk / 1000) % 1000); 1048 aprint_naive("\n"); 1049 1050 mvsoc_intr_init(); 1051 1052 for (i = 0; i < __arraycount(tagstbl); i++) 1053 if (tagstbl[i].model == model && tagstbl[i].rev == rev) 1054 break; 1055 if (i >= __arraycount(tagstbl)) 1056 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 1057 tags = tagstbl[i].tags; 1058 1059 if (boothowto & (AB_VERBOSE | AB_DEBUG)) 1060 mvsoc_target_dump(sc); 1061 1062 for (i = 0; i < __arraycount(mvsoc_periphs); i++) { 1063 if (mvsoc_periphs[i].model != model) 1064 continue; 1065 1066 mva.mva_name = mvsoc_periphs[i].name; 1067 mva.mva_model = model; 1068 mva.mva_revision = rev; 1069 mva.mva_iot = sc->sc_iot; 1070 mva.mva_ioh = sc->sc_ioh; 1071 mva.mva_unit = mvsoc_periphs[i].unit; 1072 mva.mva_addr = sc->sc_addr; 1073 mva.mva_offset = mvsoc_periphs[i].offset; 1074 mva.mva_size = 0; 1075 mva.mva_dmat = sc->sc_dmat; 1076 mva.mva_irq = mvsoc_periphs[i].irq; 1077 mva.mva_tags = tags; 1078 1079 /* Skip clock disabled devices */ 1080 if (mvsoc_clkgating != NULL && mvsoc_clkgating(&mva)) { 1081 aprint_normal_dev(self, "%s%d clock disabled\n", 1082 mvsoc_periphs[i].name, mvsoc_periphs[i].unit); 1083 continue; 1084 } 1085 1086 config_found_sm_loc(sc->sc_dev, "mvsoc", NULL, &mva, 1087 mvsoc_print, mvsoc_search); 1088 } 1089 } 1090 1091 static int 1092 mvsoc_print(void *aux, const char *pnp) 1093 { 1094 struct marvell_attach_args *mva = aux; 1095 1096 if (pnp) 1097 aprint_normal("%s at %s unit %d", 1098 mva->mva_name, pnp, mva->mva_unit); 1099 else { 1100 if (mva->mva_unit != MVA_UNIT_DEFAULT) 1101 aprint_normal(" unit %d", mva->mva_unit); 1102 if (mva->mva_offset != MVA_OFFSET_DEFAULT) { 1103 aprint_normal(" offset 0x%04lx", mva->mva_offset); 1104 if (mva->mva_size > 0) 1105 aprint_normal("-0x%04lx", 1106 mva->mva_offset + mva->mva_size - 1); 1107 } 1108 if (mva->mva_irq != MVA_IRQ_DEFAULT) 1109 aprint_normal(" irq %d", mva->mva_irq); 1110 } 1111 1112 return UNCONF; 1113 } 1114 1115 /* ARGSUSED */ 1116 static int 1117 mvsoc_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 1118 { 1119 1120 return config_match(parent, cf, aux); 1121 } 1122 1123 /* ARGSUSED */ 1124 int 1125 marvell_winparams_by_tag(device_t dev, int tag, int *target, int *attribute, 1126 uint64_t *base, uint32_t *size) 1127 { 1128 uint32_t base32; 1129 int rv; 1130 1131 rv = mvsoc_target(tag, target, attribute, &base32, size); 1132 *base = base32; 1133 if (rv == -1) 1134 return -1; 1135 return 0; 1136 } 1137 1138 1139 /* 1140 * These functions is called before bus_space is initialized. 1141 */ 1142 1143 void 1144 mvsoc_bootstrap(bus_addr_t iobase) 1145 { 1146 1147 regbase = iobase; 1148 dsc_base = iobase + MVSOC_DSC_BASE; 1149 mlmb_base = iobase + MVSOC_MLMB_BASE; 1150 pex_base = iobase + MVSOC_PEX_BASE; 1151 #ifdef MVSOC_CONSOLE_EARLY 1152 com_base = iobase + MVSOC_COM0_BASE; 1153 cn_tab = &mvsoc_earlycons; 1154 printf("Hello\n"); 1155 #endif 1156 } 1157 1158 /* 1159 * We can read register of PCI configurations from (MVSOC_PEX_BASE + 0). 1160 */ 1161 uint16_t 1162 mvsoc_model(void) 1163 { 1164 /* 1165 * We read product-id from vendor/device register of PCI-Express. 1166 */ 1167 uint32_t reg; 1168 uint16_t model; 1169 1170 KASSERT(regbase != 0xffffffff); 1171 1172 reg = *(volatile uint32_t *)(pex_base + PCI_ID_REG); 1173 model = PCI_PRODUCT(reg); 1174 1175 #if defined(ORION) 1176 if (model == PCI_PRODUCT_MARVELL_88F5182) { 1177 reg = *(volatile uint32_t *)(regbase + ORION_PMI_BASE + 1178 ORION_PMI_SAMPLE_AT_RESET); 1179 if ((reg & ORION_PMISMPL_TCLK_MASK) == 0) 1180 model = PCI_PRODUCT_MARVELL_88F5082; 1181 } 1182 #endif 1183 #if defined(KIRKWOOD) 1184 if (model == PCI_PRODUCT_MARVELL_88F6281) { 1185 reg = *(volatile uint32_t *)(regbase + KIRKWOOD_MISC_BASE + 1186 KIRKWOOD_MISC_DEVICEID); 1187 if (reg == 1) /* 88F6192 is 1 */ 1188 model = MARVELL_KIRKWOOD_88F6192; 1189 } 1190 #endif 1191 1192 return model; 1193 } 1194 1195 uint8_t 1196 mvsoc_rev(void) 1197 { 1198 uint32_t reg; 1199 uint8_t rev; 1200 1201 KASSERT(regbase != 0xffffffff); 1202 1203 reg = *(volatile uint32_t *)(pex_base + PCI_CLASS_REG); 1204 rev = PCI_REVISION(reg); 1205 1206 return rev; 1207 } 1208 1209 1210 int 1211 mvsoc_target(int tag, uint32_t *target, uint32_t *attr, uint32_t *base, 1212 uint32_t *size) 1213 { 1214 int i; 1215 1216 KASSERT(regbase != 0xffffffff); 1217 1218 if (tag == MVSOC_TAG_INTERNALREG) { 1219 if (target != NULL) 1220 *target = 0; 1221 if (attr != NULL) 1222 *attr = 0; 1223 if (base != NULL) 1224 *base = read_mlmbreg(MVSOC_MLMB_IRBAR) & 1225 MVSOC_MLMB_IRBAR_BASE_MASK; 1226 if (size != NULL) 1227 *size = 0; 1228 1229 return 0; 1230 } 1231 1232 /* sanity check */ 1233 for (i = 0; i < __arraycount(mvsoc_tags); i++) 1234 if (mvsoc_tags[i].tag == tag) 1235 break; 1236 if (i >= __arraycount(mvsoc_tags)) 1237 return -1; 1238 1239 if (target != NULL) 1240 *target = mvsoc_tags[i].target; 1241 if (attr != NULL) 1242 *attr = mvsoc_tags[i].attr; 1243 1244 if (mvsoc_tags[i].target == MVSOC_UNITID_DDR) { 1245 if (tag == MARVELL_TAG_SDRAM_CS0 || 1246 tag == MARVELL_TAG_SDRAM_CS1 || 1247 tag == MARVELL_TAG_SDRAM_CS2 || 1248 tag == MARVELL_TAG_SDRAM_CS3) 1249 return mvsoc_target_ddr(mvsoc_tags[i].attr, base, size); 1250 else if (tag == MARVELL_TAG_AXI_CS0 || 1251 tag == MARVELL_TAG_AXI_CS1) 1252 return mvsoc_target_axi(tag, base, size); 1253 else 1254 return mvsoc_target_ddr3(mvsoc_tags[i].attr, base, 1255 size); 1256 } else 1257 return mvsoc_target_peripheral(mvsoc_tags[i].target, 1258 mvsoc_tags[i].attr, base, size); 1259 } 1260 1261 static int 1262 mvsoc_target_ddr(uint32_t attr, uint32_t *base, uint32_t *size) 1263 { 1264 uint32_t baseaddrreg, sizereg; 1265 int cs; 1266 1267 /* 1268 * Read DDR SDRAM Controller Address Decode Registers 1269 */ 1270 1271 switch (attr) { 1272 case MARVELL_ATTR_SDRAM_CS0: 1273 cs = 0; 1274 break; 1275 case MARVELL_ATTR_SDRAM_CS1: 1276 cs = 1; 1277 break; 1278 case MARVELL_ATTR_SDRAM_CS2: 1279 cs = 2; 1280 break; 1281 case MARVELL_ATTR_SDRAM_CS3: 1282 cs = 3; 1283 break; 1284 default: 1285 aprint_error("unknwon ATTR: 0x%x", attr); 1286 return -1; 1287 } 1288 sizereg = *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSSR(cs)); 1289 if (sizereg & MVSOC_DSC_CSSR_WINEN) { 1290 baseaddrreg = 1291 *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSBAR(cs)); 1292 1293 if (base != NULL) 1294 *base = baseaddrreg & MVSOC_DSC_CSBAR_BASE_MASK; 1295 if (size != NULL) 1296 *size = (sizereg & MVSOC_DSC_CSSR_SIZE_MASK) + 1297 (~MVSOC_DSC_CSSR_SIZE_MASK + 1); 1298 } else { 1299 if (base != NULL) 1300 *base = 0; 1301 if (size != NULL) 1302 *size = 0; 1303 } 1304 return 0; 1305 } 1306 1307 static int 1308 mvsoc_target_ddr3(uint32_t attr, uint32_t *base, uint32_t *size) 1309 { 1310 uint32_t baseaddrreg, sizereg; 1311 int cs, i; 1312 1313 /* 1314 * Read DDR3 SDRAM Address Decoding Registers 1315 */ 1316 1317 switch (attr) { 1318 case MARVELL_ATTR_SDRAM_CS0: 1319 cs = 0; 1320 break; 1321 case MARVELL_ATTR_SDRAM_CS1: 1322 cs = 1; 1323 break; 1324 case MARVELL_ATTR_SDRAM_CS2: 1325 cs = 2; 1326 break; 1327 case MARVELL_ATTR_SDRAM_CS3: 1328 cs = 3; 1329 break; 1330 default: 1331 aprint_error("unknwon ATTR: 0x%x", attr); 1332 return -1; 1333 } 1334 for (i = 0; i < MVSOC_MLMB_NWIN; i++) { 1335 sizereg = read_mlmbreg(MVSOC_MLMB_WINCR(i)); 1336 if ((sizereg & MVSOC_MLMB_WINCR_EN) && 1337 MVSOC_MLMB_WINCR_WINCS(sizereg) == cs) 1338 break; 1339 } 1340 if (i == MVSOC_MLMB_NWIN) { 1341 if (base != NULL) 1342 *base = 0; 1343 if (size != NULL) 1344 *size = 0; 1345 return 0; 1346 } 1347 1348 baseaddrreg = read_mlmbreg(MVSOC_MLMB_WINBAR(i)); 1349 if (base != NULL) 1350 *base = baseaddrreg & MVSOC_MLMB_WINBAR_BASE_MASK; 1351 if (size != NULL) 1352 *size = (sizereg & MVSOC_MLMB_WINCR_SIZE_MASK) + 1353 (~MVSOC_MLMB_WINCR_SIZE_MASK + 1); 1354 return 0; 1355 } 1356 1357 static int 1358 mvsoc_target_axi(int tag, uint32_t *base, uint32_t *size) 1359 { 1360 uint32_t val; 1361 int cs; 1362 1363 /* 1364 * Read MMAP1 Chip Select N the other side of AXI DDR Registers 1365 */ 1366 1367 switch (tag) { 1368 case MARVELL_TAG_AXI_CS0: 1369 cs = 0; 1370 break; 1371 case MARVELL_TAG_AXI_CS1: 1372 cs = 1; 1373 break; 1374 default: 1375 aprint_error("unknwon TAG: 0x%x", tag); 1376 return -1; 1377 } 1378 val = *(volatile uint32_t *)(regbase + MVSOC_AXI_MMAP1(cs)); 1379 if (val & MVSOC_AXI_MMAP1_VALID) { 1380 if (base != NULL) 1381 *base = MVSOC_AXI_MMAP1_STARTADDRESS(val); 1382 if (size != NULL) 1383 *size = MVSOC_AXI_MMAP1_AREALENGTH(val); 1384 } else { 1385 if (base != NULL) 1386 *base = 0; 1387 if (size != NULL) 1388 *size = 0; 1389 } 1390 return 0; 1391 } 1392 1393 static int 1394 mvsoc_target_peripheral(uint32_t target, uint32_t attr, uint32_t *base, 1395 uint32_t *size) 1396 { 1397 uint32_t basereg, ctrlreg, ta, tamask; 1398 int i; 1399 1400 /* 1401 * Read CPU Address Map Registers 1402 */ 1403 1404 ta = MVSOC_MLMB_WCR_TARGET(target) | MVSOC_MLMB_WCR_ATTR(attr); 1405 tamask = MVSOC_MLMB_WCR_TARGET(MVSOC_UNITID_MASK) | 1406 MVSOC_MLMB_WCR_ATTR(MARVELL_ATTR_MASK); 1407 1408 if (base != NULL) 1409 *base = 0; 1410 if (size != NULL) 1411 *size = 0; 1412 1413 for (i = 0; i < nwindow; i++) { 1414 ctrlreg = read_mlmbreg(MVSOC_MLMB_WCR(i)); 1415 if ((ctrlreg & tamask) != ta) 1416 continue; 1417 if (ctrlreg & MVSOC_MLMB_WCR_WINEN) { 1418 basereg = read_mlmbreg(MVSOC_MLMB_WBR(i)); 1419 1420 if (base != NULL) 1421 *base = basereg & MVSOC_MLMB_WBR_BASE_MASK; 1422 if (size != NULL) 1423 *size = (ctrlreg & 1424 MVSOC_MLMB_WCR_SIZE_MASK) + 1425 (~MVSOC_MLMB_WCR_SIZE_MASK + 1); 1426 } 1427 break; 1428 } 1429 return i; 1430 } 1431 1432 int 1433 mvsoc_target_dump(struct mvsoc_softc *sc) 1434 { 1435 uint32_t reg, base, size, target, attr, enable; 1436 int i, n; 1437 1438 for (i = 0, n = 0; i < nwindow; i++) { 1439 reg = read_mlmbreg(MVSOC_MLMB_WCR(i)); 1440 enable = reg & MVSOC_MLMB_WCR_WINEN; 1441 target = MVSOC_MLMB_WCR_GET_TARGET(reg); 1442 attr = MVSOC_MLMB_WCR_GET_ATTR(reg); 1443 size = MVSOC_MLMB_WCR_GET_SIZE(reg); 1444 1445 reg = read_mlmbreg(MVSOC_MLMB_WBR(i)); 1446 base = MVSOC_MLMB_WBR_GET_BASE(reg); 1447 1448 if (!enable) 1449 continue; 1450 1451 aprint_verbose_dev(sc->sc_dev, 1452 "Mbus window %2d: Base 0x%08x Size 0x%08x ", i, base, size); 1453 #ifdef ARMADAXP 1454 armadaxp_attr_dump(sc, target, attr); 1455 #else 1456 mvsoc_attr_dump(sc, target, attr); 1457 #endif 1458 printf("\n"); 1459 n++; 1460 } 1461 1462 return n; 1463 } 1464 1465 int 1466 mvsoc_attr_dump(struct mvsoc_softc *sc, uint32_t target, uint32_t attr) 1467 { 1468 aprint_verbose_dev(sc->sc_dev, "target 0x%x(attr 0x%x)", target, attr); 1469 return 0; 1470 } 1471
Indexes created Thu Oct 23 22:10:10 GMT 2025