mvsoc.c revision 1.27
1 /* $NetBSD: mvsoc.c,v 1.27 2017/01/09 14:15:20 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2013, 2014, 2016 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.27 2017/01/09 14:15:20 kiyohara Exp $"); 30 31 #include "opt_cputypes.h" 32 #include "opt_mvsoc.h" 33 #ifdef ARMADAXP 34 #include "mvxpe.h" 35 #include "mvxpsec.h" 36 #endif 37 38 #include <sys/param.h> 39 #include <sys/boot_flag.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/device.h> 43 #include <sys/errno.h> 44 45 #include <dev/pci/pcidevs.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/marvell/marvellreg.h> 48 #include <dev/marvell/marvellvar.h> 49 50 #include <arm/marvell/mvsocreg.h> 51 #include <arm/marvell/mvsocvar.h> 52 #include <arm/marvell/orionreg.h> 53 #include <arm/marvell/kirkwoodreg.h> 54 #include <arm/marvell/mv78xx0reg.h> 55 #include <arm/marvell/dovereg.h> 56 #include <arm/marvell/armadaxpvar.h> 57 #include <arm/marvell/armadaxpreg.h> 58 59 #include <uvm/uvm.h> 60 61 #include "locators.h" 62 63 #ifdef MVSOC_CONSOLE_EARLY 64 #include <dev/ic/ns16550reg.h> 65 #include <dev/ic/comreg.h> 66 #include <dev/cons.h> 67 #endif 68 69 static int mvsoc_match(device_t, struct cfdata *, void *); 70 static void mvsoc_attach(device_t, device_t, void *); 71 72 static int mvsoc_print(void *, const char *); 73 static int mvsoc_search(device_t, cfdata_t, const int *, void *); 74 75 static int mvsoc_target_ddr(uint32_t, uint32_t *, uint32_t *); 76 static int mvsoc_target_ddr3(uint32_t, uint32_t *, uint32_t *); 77 static int mvsoc_target_axi(int, uint32_t *, uint32_t *); 78 static int mvsoc_target_peripheral(uint32_t, uint32_t, uint32_t *, uint32_t *); 79 80 uint32_t mvPclk, mvSysclk, mvTclk = 0; 81 int nwindow = 0, nremap = 0; 82 static vaddr_t regbase = 0xffffffff, dsc_base, pex_base; 83 vaddr_t mlmb_base; 84 85 void (*mvsoc_intr_init)(void); 86 int (*mvsoc_clkgating)(struct marvell_attach_args *); 87 88 89 #ifdef MVSOC_CONSOLE_EARLY 90 static vaddr_t com_base; 91 92 static inline uint32_t 93 uart_read(bus_size_t o) 94 { 95 return *(volatile uint32_t *)(com_base + (o << 2)); 96 } 97 98 static inline void 99 uart_write(bus_size_t o, uint32_t v) 100 { 101 *(volatile uint32_t *)(com_base + (o << 2)) = v; 102 } 103 104 static int 105 mvsoc_cngetc(dev_t dv) 106 { 107 if ((uart_read(com_lsr) & LSR_RXRDY) == 0) 108 return -1; 109 110 return uart_read(com_data) & 0xff; 111 } 112 113 static void 114 mvsoc_cnputc(dev_t dv, int c) 115 { 116 int timo = 150000; 117 118 while ((uart_read(com_lsr) & LSR_TXRDY) == 0 && --timo > 0) 119 ; 120 121 uart_write(com_data, c); 122 123 timo = 150000; 124 while ((uart_read(com_lsr) & LSR_TSRE) == 0 && --timo > 0) 125 ; 126 } 127 128 static struct consdev mvsoc_earlycons = { 129 .cn_putc = mvsoc_cnputc, 130 .cn_getc = mvsoc_cngetc, 131 .cn_pollc = nullcnpollc, 132 }; 133 #endif 134 135 136 /* attributes */ 137 static struct { 138 int tag; 139 uint32_t attr; 140 uint32_t target; 141 } mvsoc_tags[] = { 142 { MARVELL_TAG_SDRAM_CS0, 143 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 144 { MARVELL_TAG_SDRAM_CS1, 145 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 146 { MARVELL_TAG_SDRAM_CS2, 147 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 148 { MARVELL_TAG_SDRAM_CS3, 149 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 150 151 { MARVELL_TAG_AXI_CS0, 152 MARVELL_ATTR_AXI_DDR, MVSOC_UNITID_DDR }, 153 { MARVELL_TAG_AXI_CS1, 154 MARVELL_ATTR_AXI_DDR, MVSOC_UNITID_DDR }, 155 156 { MARVELL_TAG_DDR3_CS0, 157 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 158 { MARVELL_TAG_DDR3_CS1, 159 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 160 { MARVELL_TAG_DDR3_CS2, 161 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 162 { MARVELL_TAG_DDR3_CS3, 163 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 164 165 #if defined(ORION) 166 { ORION_TAG_DEVICE_CS0, 167 ORION_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 168 { ORION_TAG_DEVICE_CS1, 169 ORION_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 170 { ORION_TAG_DEVICE_CS2, 171 ORION_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 172 { ORION_TAG_DEVICE_BOOTCS, 173 ORION_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 174 { ORION_TAG_FLASH_CS, 175 ORION_ATTR_FLASH_CS, MVSOC_UNITID_DEVBUS }, 176 { ORION_TAG_PEX0_MEM, 177 ORION_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 178 { ORION_TAG_PEX0_IO, 179 ORION_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 180 { ORION_TAG_PEX1_MEM, 181 ORION_ATTR_PEX_MEM, ORION_UNITID_PEX1 }, 182 { ORION_TAG_PEX1_IO, 183 ORION_ATTR_PEX_IO, ORION_UNITID_PEX1 }, 184 { ORION_TAG_PCI_MEM, 185 ORION_ATTR_PCI_MEM, ORION_UNITID_PCI }, 186 { ORION_TAG_PCI_IO, 187 ORION_ATTR_PCI_IO, ORION_UNITID_PCI }, 188 { ORION_TAG_CRYPT, 189 ORION_ATTR_CRYPT, ORION_UNITID_CRYPT }, 190 #endif 191 192 #if defined(KIRKWOOD) 193 { KIRKWOOD_TAG_NAND, 194 KIRKWOOD_ATTR_NAND, MVSOC_UNITID_DEVBUS }, 195 { KIRKWOOD_TAG_SPI, 196 KIRKWOOD_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 197 { KIRKWOOD_TAG_BOOTROM, 198 KIRKWOOD_ATTR_BOOTROM, MVSOC_UNITID_DEVBUS }, 199 { KIRKWOOD_TAG_PEX_MEM, 200 KIRKWOOD_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 201 { KIRKWOOD_TAG_PEX_IO, 202 KIRKWOOD_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 203 { KIRKWOOD_TAG_PEX1_MEM, 204 KIRKWOOD_ATTR_PEX1_MEM, MVSOC_UNITID_PEX }, 205 { KIRKWOOD_TAG_PEX1_IO, 206 KIRKWOOD_ATTR_PEX1_IO, MVSOC_UNITID_PEX }, 207 { KIRKWOOD_TAG_CRYPT, 208 KIRKWOOD_ATTR_CRYPT, KIRKWOOD_UNITID_CRYPT }, 209 #endif 210 211 #if defined(MV78XX0) 212 { MV78XX0_TAG_DEVICE_CS0, 213 MV78XX0_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 214 { MV78XX0_TAG_DEVICE_CS1, 215 MV78XX0_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 216 { MV78XX0_TAG_DEVICE_CS2, 217 MV78XX0_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 218 { MV78XX0_TAG_DEVICE_CS3, 219 MV78XX0_ATTR_DEVICE_CS3, MVSOC_UNITID_DEVBUS }, 220 { MV78XX0_TAG_DEVICE_BOOTCS, 221 MV78XX0_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 222 { MV78XX0_TAG_SPI, 223 MV78XX0_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 224 { MV78XX0_TAG_PEX0_MEM, 225 MV78XX0_ATTR_PEX_0_MEM, MVSOC_UNITID_PEX }, 226 { MV78XX0_TAG_PEX01_MEM, 227 MV78XX0_ATTR_PEX_1_MEM, MVSOC_UNITID_PEX }, 228 { MV78XX0_TAG_PEX02_MEM, 229 MV78XX0_ATTR_PEX_2_MEM, MVSOC_UNITID_PEX }, 230 { MV78XX0_TAG_PEX03_MEM, 231 MV78XX0_ATTR_PEX_3_MEM, MVSOC_UNITID_PEX }, 232 { MV78XX0_TAG_PEX0_IO, 233 MV78XX0_ATTR_PEX_0_IO, MVSOC_UNITID_PEX }, 234 { MV78XX0_TAG_PEX01_IO, 235 MV78XX0_ATTR_PEX_1_IO, MVSOC_UNITID_PEX }, 236 { MV78XX0_TAG_PEX02_IO, 237 MV78XX0_ATTR_PEX_2_IO, MVSOC_UNITID_PEX }, 238 { MV78XX0_TAG_PEX03_IO, 239 MV78XX0_ATTR_PEX_3_IO, MVSOC_UNITID_PEX }, 240 { MV78XX0_TAG_PEX1_MEM, 241 MV78XX0_ATTR_PEX_0_MEM, MV78XX0_UNITID_PEX1 }, 242 { MV78XX0_TAG_PEX11_MEM, 243 MV78XX0_ATTR_PEX_1_MEM, MV78XX0_UNITID_PEX1 }, 244 { MV78XX0_TAG_PEX12_MEM, 245 MV78XX0_ATTR_PEX_2_MEM, MV78XX0_UNITID_PEX1 }, 246 { MV78XX0_TAG_PEX13_MEM, 247 MV78XX0_ATTR_PEX_3_MEM, MV78XX0_UNITID_PEX1 }, 248 { MV78XX0_TAG_PEX1_IO, 249 MV78XX0_ATTR_PEX_0_IO, MV78XX0_UNITID_PEX1 }, 250 { MV78XX0_TAG_PEX11_IO, 251 MV78XX0_ATTR_PEX_1_IO, MV78XX0_UNITID_PEX1 }, 252 { MV78XX0_TAG_PEX12_IO, 253 MV78XX0_ATTR_PEX_2_IO, MV78XX0_UNITID_PEX1 }, 254 { MV78XX0_TAG_PEX13_IO, 255 MV78XX0_ATTR_PEX_3_IO, MV78XX0_UNITID_PEX1 }, 256 { MV78XX0_TAG_CRYPT, 257 MV78XX0_ATTR_CRYPT, MV78XX0_UNITID_CRYPT }, 258 #endif 259 260 #if defined(DOVE) 261 { DOVE_TAG_PEX0_MEM, 262 DOVE_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 263 { DOVE_TAG_PEX0_IO, 264 DOVE_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 265 { DOVE_TAG_PEX1_MEM, 266 DOVE_ATTR_PEX_MEM, DOVE_UNITID_PEX1 }, 267 { DOVE_TAG_PEX1_IO, 268 DOVE_ATTR_PEX_IO, DOVE_UNITID_PEX1 }, 269 { DOVE_TAG_CRYPT, 270 DOVE_ATTR_SA, DOVE_UNITID_SA }, 271 { DOVE_TAG_SPI0, 272 DOVE_ATTR_SPI0, MVSOC_UNITID_DEVBUS }, 273 { DOVE_TAG_SPI1, 274 DOVE_ATTR_SPI1, MVSOC_UNITID_DEVBUS }, 275 { DOVE_TAG_BOOTROM, 276 DOVE_ATTR_BOOTROM, MVSOC_UNITID_DEVBUS }, 277 { DOVE_TAG_PMU, 278 DOVE_ATTR_NAND, DOVE_UNITID_NAND }, 279 { DOVE_TAG_PMU, 280 DOVE_ATTR_PMU, DOVE_UNITID_PMU }, 281 #endif 282 283 #if defined(ARMADAXP) 284 { ARMADAXP_TAG_PEX00_MEM, 285 ARMADAXP_ATTR_PEXx0_MEM, ARMADAXP_UNITID_PEX0 }, 286 { ARMADAXP_TAG_PEX00_IO, 287 ARMADAXP_ATTR_PEXx0_IO, ARMADAXP_UNITID_PEX0 }, 288 { ARMADAXP_TAG_PEX01_MEM, 289 ARMADAXP_ATTR_PEXx1_MEM, ARMADAXP_UNITID_PEX0 }, 290 { ARMADAXP_TAG_PEX01_IO, 291 ARMADAXP_ATTR_PEXx1_IO, ARMADAXP_UNITID_PEX0 }, 292 { ARMADAXP_TAG_PEX02_MEM, 293 ARMADAXP_ATTR_PEXx2_MEM, ARMADAXP_UNITID_PEX0 }, 294 { ARMADAXP_TAG_PEX02_IO, 295 ARMADAXP_ATTR_PEXx2_IO, ARMADAXP_UNITID_PEX0 }, 296 { ARMADAXP_TAG_PEX03_MEM, 297 ARMADAXP_ATTR_PEXx3_MEM, ARMADAXP_UNITID_PEX0 }, 298 { ARMADAXP_TAG_PEX03_IO, 299 ARMADAXP_ATTR_PEXx3_IO, ARMADAXP_UNITID_PEX0 }, 300 { ARMADAXP_TAG_PEX2_MEM, 301 ARMADAXP_ATTR_PEX2_MEM, ARMADAXP_UNITID_PEX2 }, 302 { ARMADAXP_TAG_PEX2_IO, 303 ARMADAXP_ATTR_PEX2_IO, ARMADAXP_UNITID_PEX2 }, 304 { ARMADAXP_TAG_PEX3_MEM, 305 ARMADAXP_ATTR_PEX3_MEM, ARMADAXP_UNITID_PEX3 }, 306 { ARMADAXP_TAG_PEX3_IO, 307 ARMADAXP_ATTR_PEX3_IO, ARMADAXP_UNITID_PEX3 }, 308 { ARMADAXP_TAG_CRYPT0, 309 ARMADAXP_ATTR_CRYPT0_NOSWAP, ARMADAXP_UNITID_CRYPT }, 310 { ARMADAXP_TAG_CRYPT1, 311 ARMADAXP_ATTR_CRYPT1_NOSWAP, ARMADAXP_UNITID_CRYPT }, 312 #endif 313 }; 314 315 #if defined(ORION) 316 #define ORION_1(m) MARVELL_ORION_1_ ## m 317 #define ORION_2(m) MARVELL_ORION_2_ ## m 318 #endif 319 #if defined(KIRKWOOD) 320 #undef KIRKWOOD 321 #define KIRKWOOD(m) MARVELL_KIRKWOOD_ ## m 322 #endif 323 #if defined(MV78XX0) 324 #undef MV78XX0 325 #define MV78XX0(m) MARVELL_MV78XX0_ ## m 326 #endif 327 #if defined(DOVE) 328 #undef DOVE 329 #define DOVE(m) MARVELL_DOVE_ ## m 330 #endif 331 #if defined(ARMADAXP) 332 #undef ARMADAXP 333 #define ARMADAXP(m) MARVELL_ARMADAXP_ ## m 334 #define ARMADA370(m) MARVELL_ARMADA370_ ## m 335 #endif 336 static struct { 337 uint16_t model; 338 uint8_t rev; 339 const char *modelstr; 340 const char *revstr; 341 const char *typestr; 342 } nametbl[] = { 343 #if defined(ORION) 344 { ORION_1(88F1181), 0, "MV88F1181", NULL, "Orion1" }, 345 { ORION_1(88F5082), 2, "MV88F5082", "A2", "Orion1" }, 346 { ORION_1(88F5180N), 3, "MV88F5180N","B1", "Orion1" }, 347 { ORION_1(88F5181), 0, "MV88F5181", "A0", "Orion1" }, 348 { ORION_1(88F5181), 1, "MV88F5181", "A1", "Orion1" }, 349 { ORION_1(88F5181), 2, "MV88F5181", "B0", "Orion1" }, 350 { ORION_1(88F5181), 3, "MV88F5181", "B1", "Orion1" }, 351 { ORION_1(88F5181), 8, "MV88F5181L","A0", "Orion1" }, 352 { ORION_1(88F5181), 9, "MV88F5181L","A1", "Orion1" }, 353 { ORION_1(88F5182), 0, "MV88F5182", "A0", "Orion1" }, 354 { ORION_1(88F5182), 1, "MV88F5182", "A1", "Orion1" }, 355 { ORION_1(88F5182), 2, "MV88F5182", "A2", "Orion1" }, 356 { ORION_1(88F6082), 0, "MV88F6082", "A0", "Orion1" }, 357 { ORION_1(88F6082), 1, "MV88F6082", "A1", "Orion1" }, 358 { ORION_1(88F6183), 0, "MV88F6183", "A0", "Orion1" }, 359 { ORION_1(88F6183), 1, "MV88F6183", "Z0", "Orion1" }, 360 { ORION_1(88W8660), 0, "MV88W8660", "A0", "Orion1" }, 361 { ORION_1(88W8660), 1, "MV88W8660", "A1", "Orion1" }, 362 363 { ORION_2(88F1281), 0, "MV88F1281", "A0", "Orion2" }, 364 { ORION_2(88F5281), 0, "MV88F5281", "A0", "Orion2" }, 365 { ORION_2(88F5281), 1, "MV88F5281", "B0", "Orion2" }, 366 { ORION_2(88F5281), 2, "MV88F5281", "C0", "Orion2" }, 367 { ORION_2(88F5281), 3, "MV88F5281", "C1", "Orion2" }, 368 { ORION_2(88F5281), 4, "MV88F5281", "D0", "Orion2" }, 369 #endif 370 371 #if defined(KIRKWOOD) 372 { KIRKWOOD(88F6180), 2, "88F6180", "A0", "Kirkwood" }, 373 { KIRKWOOD(88F6180), 3, "88F6180", "A1", "Kirkwood" }, 374 { KIRKWOOD(88F6192), 0, "88F619x", "Z0", "Kirkwood" }, 375 { KIRKWOOD(88F6192), 2, "88F619x", "A0", "Kirkwood" }, 376 { KIRKWOOD(88F6192), 3, "88F619x", "A1", "Kirkwood" }, 377 { KIRKWOOD(88F6281), 0, "88F6281", "Z0", "Kirkwood" }, 378 { KIRKWOOD(88F6281), 2, "88F6281", "A0", "Kirkwood" }, 379 { KIRKWOOD(88F6281), 3, "88F6281", "A1", "Kirkwood" }, 380 { KIRKWOOD(88F6282), 0, "88F6282", "A0", "Kirkwood" }, 381 { KIRKWOOD(88F6282), 1, "88F6282", "A1", "Kirkwood" }, 382 #endif 383 384 #if defined(MV78XX0) 385 { MV78XX0(MV78100), 1, "MV78100", "A0", "Discovery Innovation" }, 386 { MV78XX0(MV78100), 2, "MV78100", "A1", "Discovery Innovation" }, 387 { MV78XX0(MV78200), 1, "MV78200", "A0", "Discovery Innovation" }, 388 #endif 389 390 #if defined(DOVE) 391 { DOVE(88AP510), 0, "88AP510", "Z0", "Dove" }, 392 { DOVE(88AP510), 1, "88AP510", "Z1", "Dove" }, 393 { DOVE(88AP510), 2, "88AP510", "Y0", "Dove" }, 394 { DOVE(88AP510), 3, "88AP510", "Y1", "Dove" }, 395 { DOVE(88AP510), 4, "88AP510", "X0", "Dove" }, 396 { DOVE(88AP510), 6, "88AP510", "A0", "Dove" }, 397 { DOVE(88AP510), 7, "88AP510", "A1", "Dove" }, 398 #endif 399 400 #if defined(ARMADAXP) 401 { ARMADAXP(MV78130), 1, "MV78130", "A0", "Armada XP" }, 402 { ARMADAXP(MV78160), 1, "MV78160", "A0", "Armada XP" }, 403 { ARMADAXP(MV78230), 1, "MV78260", "A0", "Armada XP" }, 404 { ARMADAXP(MV78260), 1, "MV78260", "A0", "Armada XP" }, 405 { ARMADAXP(MV78260), 2, "MV78260", "B0", "Armada XP" }, 406 { ARMADAXP(MV78460), 1, "MV78460", "A0", "Armada XP" }, 407 { ARMADAXP(MV78460), 2, "MV78460", "B0", "Armada XP" }, 408 409 { ARMADA370(MV6707), 0, "MV6707", "A0", "Armada 370" }, 410 { ARMADA370(MV6707), 1, "MV6707", "A1", "Armada 370" }, 411 { ARMADA370(MV6710), 0, "MV6710", "A0", "Armada 370" }, 412 { ARMADA370(MV6710), 1, "MV6710", "A1", "Armada 370" }, 413 { ARMADA370(MV6W11), 0, "MV6W11", "A0", "Armada 370" }, 414 { ARMADA370(MV6W11), 1, "MV6W11", "A1", "Armada 370" }, 415 #endif 416 }; 417 418 enum marvell_tags ddr_tags[] = { 419 MARVELL_TAG_SDRAM_CS0, 420 MARVELL_TAG_SDRAM_CS1, 421 MARVELL_TAG_SDRAM_CS2, 422 MARVELL_TAG_SDRAM_CS3, 423 424 MARVELL_TAG_UNDEFINED 425 }; 426 enum marvell_tags ddr3_tags[] = { 427 MARVELL_TAG_DDR3_CS0, 428 MARVELL_TAG_DDR3_CS1, 429 MARVELL_TAG_DDR3_CS2, 430 MARVELL_TAG_DDR3_CS3, 431 432 MARVELL_TAG_UNDEFINED 433 }; 434 enum marvell_tags axi_tags[] = { 435 MARVELL_TAG_AXI_CS0, 436 MARVELL_TAG_AXI_CS1, 437 438 MARVELL_TAG_UNDEFINED 439 }; 440 static struct { 441 uint16_t model; 442 uint8_t rev; 443 enum marvell_tags *tags; 444 } tagstbl[] = { 445 #if defined(ORION) 446 { ORION_1(88F1181), 0, ddr_tags }, 447 { ORION_1(88F5082), 2, ddr_tags }, 448 { ORION_1(88F5180N), 3, ddr_tags }, 449 { ORION_1(88F5181), 0, ddr_tags }, 450 { ORION_1(88F5181), 1, ddr_tags }, 451 { ORION_1(88F5181), 2, ddr_tags }, 452 { ORION_1(88F5181), 3, ddr_tags }, 453 { ORION_1(88F5181), 8, ddr_tags }, 454 { ORION_1(88F5181), 9, ddr_tags }, 455 { ORION_1(88F5182), 0, ddr_tags }, 456 { ORION_1(88F5182), 1, ddr_tags }, 457 { ORION_1(88F5182), 2, ddr_tags }, 458 { ORION_1(88F6082), 0, ddr_tags }, 459 { ORION_1(88F6082), 1, ddr_tags }, 460 { ORION_1(88F6183), 0, ddr_tags }, 461 { ORION_1(88F6183), 1, ddr_tags }, 462 { ORION_1(88W8660), 0, ddr_tags }, 463 { ORION_1(88W8660), 1, ddr_tags }, 464 465 { ORION_2(88F1281), 0, ddr_tags }, 466 { ORION_2(88F5281), 0, ddr_tags }, 467 { ORION_2(88F5281), 1, ddr_tags }, 468 { ORION_2(88F5281), 2, ddr_tags }, 469 { ORION_2(88F5281), 3, ddr_tags }, 470 { ORION_2(88F5281), 4, ddr_tags }, 471 #endif 472 473 #if defined(KIRKWOOD) 474 { KIRKWOOD(88F6180), 2, ddr_tags }, 475 { KIRKWOOD(88F6180), 3, ddr_tags }, 476 { KIRKWOOD(88F6192), 0, ddr_tags }, 477 { KIRKWOOD(88F6192), 2, ddr_tags }, 478 { KIRKWOOD(88F6192), 3, ddr_tags }, 479 { KIRKWOOD(88F6281), 0, ddr_tags }, 480 { KIRKWOOD(88F6281), 2, ddr_tags }, 481 { KIRKWOOD(88F6281), 3, ddr_tags }, 482 { KIRKWOOD(88F6282), 0, ddr_tags }, 483 { KIRKWOOD(88F6282), 1, ddr_tags }, 484 #endif 485 486 #if defined(MV78XX0) 487 { MV78XX0(MV78100), 1, ddr_tags }, 488 { MV78XX0(MV78100), 2, ddr_tags }, 489 { MV78XX0(MV78200), 1, ddr_tags }, 490 #endif 491 492 #if defined(DOVE) 493 { DOVE(88AP510), 0, axi_tags }, 494 { DOVE(88AP510), 1, axi_tags }, 495 { DOVE(88AP510), 2, axi_tags }, 496 { DOVE(88AP510), 3, axi_tags }, 497 { DOVE(88AP510), 4, axi_tags }, 498 { DOVE(88AP510), 5, axi_tags }, 499 { DOVE(88AP510), 6, axi_tags }, 500 { DOVE(88AP510), 7, axi_tags }, 501 #endif 502 503 #if defined(ARMADAXP) 504 { ARMADAXP(MV78130), 1, ddr3_tags }, 505 { ARMADAXP(MV78160), 1, ddr3_tags }, 506 { ARMADAXP(MV78230), 1, ddr3_tags }, 507 { ARMADAXP(MV78260), 1, ddr3_tags }, 508 { ARMADAXP(MV78260), 2, ddr3_tags }, 509 { ARMADAXP(MV78460), 1, ddr3_tags }, 510 { ARMADAXP(MV78460), 2, ddr3_tags }, 511 512 { ARMADA370(MV6707), 0, ddr3_tags }, 513 { ARMADA370(MV6707), 1, ddr3_tags }, 514 { ARMADA370(MV6710), 0, ddr3_tags }, 515 { ARMADA370(MV6710), 1, ddr3_tags }, 516 { ARMADA370(MV6W11), 0, ddr3_tags }, 517 { ARMADA370(MV6W11), 1, ddr3_tags }, 518 #endif 519 }; 520 521 522 #define OFFSET_DEFAULT MVA_OFFSET_DEFAULT 523 #define IRQ_DEFAULT MVA_IRQ_DEFAULT 524 static const struct mvsoc_periph { 525 int model; 526 const char *name; 527 int unit; 528 bus_size_t offset; 529 int irq; 530 } mvsoc_periphs[] = { 531 #if defined(ORION) 532 #define ORION_IRQ_TMR (32 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 533 534 { ORION_1(88F1181), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 535 { ORION_1(88F1181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 536 { ORION_1(88F1181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 537 { ORION_1(88F1181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 538 { ORION_1(88F1181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 539 { ORION_1(88F1181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 540 { ORION_1(88F1181), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 541 542 { ORION_1(88F5082), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 543 { ORION_1(88F5082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 544 { ORION_1(88F5082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 545 { ORION_1(88F5082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 546 { ORION_1(88F5082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 547 { ORION_1(88F5082), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 548 { ORION_1(88F5082), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 549 { ORION_1(88F5082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 550 { ORION_1(88F5082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 551 { ORION_1(88F5082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 552 { ORION_1(88F5082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 553 { ORION_1(88F5082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 554 555 { ORION_1(88F5180N),"mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 556 { ORION_1(88F5180N),"mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 557 { ORION_1(88F5180N),"com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 558 { ORION_1(88F5180N),"com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 559 { ORION_1(88F5180N),"ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 560 { ORION_1(88F5180N),"gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 561 { ORION_1(88F5180N),"gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 562 { ORION_1(88F5180N),"gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 563 { ORION_1(88F5180N),"mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 564 { ORION_1(88F5180N),"mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 565 566 { ORION_1(88F5181), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 567 { ORION_1(88F5181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 568 { ORION_1(88F5181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 569 { ORION_1(88F5181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 570 { ORION_1(88F5181), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 571 { ORION_1(88F5181), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 572 { ORION_1(88F5181), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 573 { ORION_1(88F5181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 574 { ORION_1(88F5181), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 575 { ORION_1(88F5181), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 576 { ORION_1(88F5181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 577 578 { ORION_1(88F5182), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 579 { ORION_1(88F5182), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 580 { ORION_1(88F5182), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 581 { ORION_1(88F5182), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 582 { ORION_1(88F5182), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 583 { ORION_1(88F5182), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 584 { ORION_1(88F5182), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 585 { ORION_1(88F5182), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 586 { ORION_1(88F5182), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 587 { ORION_1(88F5182), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 588 { ORION_1(88F5182), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 589 { ORION_1(88F5182), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 590 591 { ORION_1(88F6082), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 592 { ORION_1(88F6082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 593 { ORION_1(88F6082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 594 { ORION_1(88F6082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 595 { ORION_1(88F6082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 596 { ORION_1(88F6082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 597 { ORION_1(88F6082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 598 { ORION_1(88F6082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 599 { ORION_1(88F6082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 600 { ORION_1(88F6082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 601 602 { ORION_1(88F6183), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 603 { ORION_1(88F6183), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 604 { ORION_1(88F6183), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 605 { ORION_1(88F6183), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 606 607 { ORION_1(88W8660), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 608 { ORION_1(88W8660), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 609 { ORION_1(88W8660), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 610 { ORION_1(88W8660), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 611 { ORION_1(88W8660), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 612 { ORION_1(88W8660), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 613 { ORION_1(88W8660), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 614 { ORION_1(88W8660), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 615 { ORION_1(88W8660), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 616 { ORION_1(88W8660), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 617 618 { ORION_2(88F1281), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 619 { ORION_2(88F1281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 620 { ORION_2(88F1281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 621 { ORION_2(88F1281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 622 { ORION_2(88F1281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 623 { ORION_2(88F1281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 624 { ORION_2(88F1281), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 625 626 { ORION_2(88F5281), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 627 { ORION_2(88F5281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 628 { ORION_2(88F5281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 629 { ORION_2(88F5281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 630 { ORION_2(88F5281), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 631 { ORION_2(88F5281), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 632 { ORION_2(88F5281), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 633 { ORION_2(88F5281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 634 { ORION_2(88F5281), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 635 { ORION_2(88F5281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 636 #endif 637 638 #if defined(KIRKWOOD) 639 #define KIRKWOOD_IRQ_TMR (64 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 640 641 { KIRKWOOD(88F6180),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 642 { KIRKWOOD(88F6180),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 643 { KIRKWOOD(88F6180),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 644 { KIRKWOOD(88F6180),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 645 { KIRKWOOD(88F6180),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 646 { KIRKWOOD(88F6180),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 647 { KIRKWOOD(88F6180),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 648 { KIRKWOOD(88F6180),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 649 { KIRKWOOD(88F6180),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 650 { KIRKWOOD(88F6180),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 651 { KIRKWOOD(88F6180),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 652 { KIRKWOOD(88F6180),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 653 654 { KIRKWOOD(88F6192),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 655 { KIRKWOOD(88F6192),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 656 { KIRKWOOD(88F6192),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 657 { KIRKWOOD(88F6192),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 658 { KIRKWOOD(88F6192),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 659 { KIRKWOOD(88F6192),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 660 { KIRKWOOD(88F6192),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 661 { KIRKWOOD(88F6192),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 662 { KIRKWOOD(88F6192),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 663 { KIRKWOOD(88F6192),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 664 { KIRKWOOD(88F6192),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 665 { KIRKWOOD(88F6192),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 666 { KIRKWOOD(88F6192),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 667 { KIRKWOOD(88F6192),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 668 669 { KIRKWOOD(88F6281),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 670 { KIRKWOOD(88F6281),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 671 { KIRKWOOD(88F6281),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 672 { KIRKWOOD(88F6281),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 673 { KIRKWOOD(88F6281),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 674 { KIRKWOOD(88F6281),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 675 { KIRKWOOD(88F6281),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 676 { KIRKWOOD(88F6281),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 677 { KIRKWOOD(88F6281),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT }, 678 { KIRKWOOD(88F6281),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 679 { KIRKWOOD(88F6281),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 680 { KIRKWOOD(88F6281),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 681 { KIRKWOOD(88F6281),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 682 { KIRKWOOD(88F6281),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 683 684 { KIRKWOOD(88F6282),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 685 { KIRKWOOD(88F6282),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 686 { KIRKWOOD(88F6282),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 687 { KIRKWOOD(88F6282),"mvsocts", 0, KIRKWOOD_TS_BASE, IRQ_DEFAULT }, 688 { KIRKWOOD(88F6282),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 689 { KIRKWOOD(88F6282),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 690 { KIRKWOOD(88F6282),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 691 { KIRKWOOD(88F6282),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 692 { KIRKWOOD(88F6282),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 693 { KIRKWOOD(88F6282),"gttwsi", 1, KIRKWOOD_TWSI1_BASE,KIRKWOOD_IRQ_TWSI1 }, 694 { KIRKWOOD(88F6282),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 695 { KIRKWOOD(88F6282),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 696 { KIRKWOOD(88F6282),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 697 { KIRKWOOD(88F6282),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 698 { KIRKWOOD(88F6282),"mvpex", 1, KIRKWOOD_PEX1_BASE,KIRKWOOD_IRQ_PEX1INT }, 699 { KIRKWOOD(88F6282),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 700 { KIRKWOOD(88F6282),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 701 #endif 702 703 #if defined(MV78XX0) 704 { MV78XX0(MV78100), "mvsoctmr",0, MVSOC_TMR_BASE, MV78XX0_IRQ_TIMER0 }, 705 { MV78XX0(MV78100), "mvsocgpp",0, MVSOC_GPP_BASE, MV78XX0_IRQ_GPIO0_7 }, 706 { MV78XX0(MV78100), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0 }, 707 { MV78XX0(MV78100), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1 }, 708 { MV78XX0(MV78100), "com", 2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 }, 709 { MV78XX0(MV78100), "com", 3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 }, 710 { MV78XX0(MV78100), "gttwsi", 0, MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI0 }, 711 { MV78XX0(MV78100), "gttwsi", 1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 }, 712 { MV78XX0(MV78100), "mvgbec", 0, MV78XX0_GBE0_BASE,IRQ_DEFAULT }, 713 { MV78XX0(MV78100), "mvgbec", 1, MV78XX0_GBE1_BASE,IRQ_DEFAULT }, 714 { MV78XX0(MV78100), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA }, 715 716 { MV78XX0(MV78200), "mvsoctmr",0, MVSOC_TMR_BASE, MV78XX0_IRQ_TIMER0 }, 717 { MV78XX0(MV78200), "mvsocgpp",0, MVSOC_GPP_BASE, MV78XX0_IRQ_GPIO0_7 }, 718 { MV78XX0(MV78200), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0 }, 719 { MV78XX0(MV78200), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1 }, 720 { MV78XX0(MV78200), "com", 2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 }, 721 { MV78XX0(MV78200), "com", 3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 }, 722 { MV78XX0(MV78200), "gttwsi", 0, MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI0 }, 723 { MV78XX0(MV78200), "gttwsi", 1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 }, 724 { MV78XX0(MV78200), "mvgbec", 0, MV78XX0_GBE0_BASE,IRQ_DEFAULT }, 725 { MV78XX0(MV78200), "mvgbec", 1, MV78XX0_GBE1_BASE,IRQ_DEFAULT }, 726 { MV78XX0(MV78200), "mvgbec", 2, MV78XX0_GBE2_BASE,IRQ_DEFAULT }, 727 { MV78XX0(MV78200), "mvgbec", 3, MV78XX0_GBE3_BASE,IRQ_DEFAULT }, 728 { MV78XX0(MV78200), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA }, 729 #endif 730 731 #if defined(DOVE) 732 #define DOVE_IRQ_TMR (64 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 733 734 { DOVE(88AP510), "mvsoctmr",0, MVSOC_TMR_BASE, DOVE_IRQ_TMR }, 735 { DOVE(88AP510), "mvsocpmu",0, DOVE_PMU_BASE, DOVE_IRQ_PMU }, 736 { DOVE(88AP510), "com", 0, MVSOC_COM0_BASE, DOVE_IRQ_UART0 }, 737 { DOVE(88AP510), "com", 1, MVSOC_COM1_BASE, DOVE_IRQ_UART1 }, 738 { DOVE(88AP510), "com", 2, DOVE_COM2_BASE, DOVE_IRQ_UART2 }, 739 { DOVE(88AP510), "com", 3, DOVE_COM3_BASE, DOVE_IRQ_UART3 }, 740 { DOVE(88AP510), "gttwsi", 0, MVSOC_TWSI_BASE, DOVE_IRQ_TWSI }, 741 { DOVE(88AP510), "mvspi", 0, DOVE_SPI0_BASE, DOVE_IRQ_SPI0 }, 742 { DOVE(88AP510), "mvspi", 1, DOVE_SPI1_BASE, DOVE_IRQ_SPI1 }, 743 { DOVE(88AP510), "mvcesa", 0, DOVE_CESA_BASE, DOVE_IRQ_SECURITYINT }, 744 { DOVE(88AP510), "ehci", 0, DOVE_USB0_BASE, DOVE_IRQ_USB0CNT }, 745 { DOVE(88AP510), "ehci", 1, DOVE_USB1_BASE, DOVE_IRQ_USB1CNT }, 746 { DOVE(88AP510), "gtidmac", 0, DOVE_XORE_BASE, IRQ_DEFAULT }, 747 { DOVE(88AP510), "mvgbec", 0, DOVE_GBE_BASE, IRQ_DEFAULT }, 748 { DOVE(88AP510), "mvpex", 0, MVSOC_PEX_BASE, DOVE_IRQ_PEX0_INT }, 749 { DOVE(88AP510), "mvpex", 1, DOVE_PEX1_BASE, DOVE_IRQ_PEX1_INT }, 750 { DOVE(88AP510), "sdhc", 0, DOVE_SDHC0_BASE, DOVE_IRQ_SD0 }, 751 { DOVE(88AP510), "sdhc", 1, DOVE_SDHC1_BASE, DOVE_IRQ_SD1 }, 752 { DOVE(88AP510), "mvsata", 0, DOVE_SATAHC_BASE, DOVE_IRQ_SATAINT }, 753 // { DOVE(88AP510), "mvsocgpp",0, MVSOC_GPP_BASE, IRQ_DEFAULT }, 754 { DOVE(88AP510), "mvsocrtc",0, DOVE_RTC_BASE, IRQ_DEFAULT }, 755 #endif 756 757 #if defined(ARMADAXP) 758 { ARMADAXP(MV78130), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 759 { ARMADAXP(MV78130), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 760 { ARMADAXP(MV78130), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 761 { ARMADAXP(MV78130), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 762 { ARMADAXP(MV78130), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 763 { ARMADAXP(MV78130), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 764 { ARMADAXP(MV78130), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 765 { ARMADAXP(MV78130), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 766 { ARMADAXP(MV78130), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 767 { ARMADAXP(MV78130), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 768 { ARMADAXP(MV78130), "mvsocts",0, ARMADAXP_TS_BASE, ARMADAXP_IRQ_PMU }, 769 { ARMADAXP(MV78130), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 770 { ARMADAXP(MV78130), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 771 { ARMADAXP(MV78130), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 772 { ARMADAXP(MV78130), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 773 { ARMADAXP(MV78130), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 774 { ARMADAXP(MV78130), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 775 { ARMADAXP(MV78130), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 776 { ARMADAXP(MV78130), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 777 { ARMADAXP(MV78130), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 778 { ARMADAXP(MV78130), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 779 { ARMADAXP(MV78130), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 780 #if NMVXPE > 0 781 { ARMADAXP(MV78130), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 782 { ARMADAXP(MV78130), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 783 { ARMADAXP(MV78130), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 784 #else 785 { ARMADAXP(MV78130), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 786 { ARMADAXP(MV78130), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 787 #endif 788 #if NMVXPSEC > 0 789 { ARMADAXP(MV78130), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 790 { ARMADAXP(MV78130), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 }, 791 #else 792 { ARMADAXP(MV78130), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 793 { ARMADAXP(MV78130), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 794 #endif 795 796 { ARMADAXP(MV78160), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 797 { ARMADAXP(MV78160), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 798 { ARMADAXP(MV78160), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 799 { ARMADAXP(MV78160), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 800 { ARMADAXP(MV78160), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 801 { ARMADAXP(MV78160), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 802 { ARMADAXP(MV78160), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 803 { ARMADAXP(MV78160), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 804 { ARMADAXP(MV78160), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 805 { ARMADAXP(MV78160), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 806 { ARMADAXP(MV78160), "mvsocts",0, ARMADAXP_TS_BASE, ARMADAXP_IRQ_PMU }, 807 { ARMADAXP(MV78160), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 808 { ARMADAXP(MV78160), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 809 { ARMADAXP(MV78160), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 810 { ARMADAXP(MV78160), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 811 { ARMADAXP(MV78160), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 812 { ARMADAXP(MV78160), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 813 { ARMADAXP(MV78160), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 814 { ARMADAXP(MV78160), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 815 { ARMADAXP(MV78160), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 816 { ARMADAXP(MV78160), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 817 { ARMADAXP(MV78160), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 818 #if NMVXPE > 0 819 { ARMADAXP(MV78160), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 820 { ARMADAXP(MV78160), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 821 { ARMADAXP(MV78160), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 822 { ARMADAXP(MV78160), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 823 { ARMADAXP(MV78160), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX }, 824 #else 825 { ARMADAXP(MV78160), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 826 { ARMADAXP(MV78160), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 827 { ARMADAXP(MV78160), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 828 { ARMADAXP(MV78160), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 829 #endif 830 #if NMVXPSEC > 0 831 { ARMADAXP(MV78160), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 832 { ARMADAXP(MV78160), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 }, 833 #else 834 { ARMADAXP(MV78160), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 835 { ARMADAXP(MV78160), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 836 #endif 837 838 { ARMADAXP(MV78230), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 839 { ARMADAXP(MV78230), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 840 { ARMADAXP(MV78230), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 841 { ARMADAXP(MV78230), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 842 { ARMADAXP(MV78230), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 843 { ARMADAXP(MV78230), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 844 { ARMADAXP(MV78230), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 845 { ARMADAXP(MV78230), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 846 { ARMADAXP(MV78230), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 847 { ARMADAXP(MV78230), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 848 { ARMADAXP(MV78230), "mvsocts",0, ARMADAXP_TS_BASE, ARMADAXP_IRQ_PMU }, 849 { ARMADAXP(MV78230), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 850 { ARMADAXP(MV78230), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 851 { ARMADAXP(MV78230), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 852 { ARMADAXP(MV78230), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 853 { ARMADAXP(MV78230), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 854 { ARMADAXP(MV78230), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 855 { ARMADAXP(MV78230), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 856 { ARMADAXP(MV78230), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 857 { ARMADAXP(MV78230), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 858 { ARMADAXP(MV78230), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 859 { ARMADAXP(MV78230), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 860 #if NMVXPE > 0 861 { ARMADAXP(MV78230), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 862 { ARMADAXP(MV78230), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 863 { ARMADAXP(MV78230), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 864 { ARMADAXP(MV78230), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 865 #else 866 { ARMADAXP(MV78230), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 867 { ARMADAXP(MV78230), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 868 { ARMADAXP(MV78230), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 869 #endif 870 #if NMVXPSEC > 0 871 { ARMADAXP(MV78230), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 872 { ARMADAXP(MV78230), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 }, 873 #else 874 { ARMADAXP(MV78230), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 875 { ARMADAXP(MV78230), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 876 #endif 877 878 { ARMADAXP(MV78260), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 879 { ARMADAXP(MV78260), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 880 { ARMADAXP(MV78260), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 881 { ARMADAXP(MV78260), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 882 { ARMADAXP(MV78260), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 883 { ARMADAXP(MV78260), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 884 { ARMADAXP(MV78260), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 885 { ARMADAXP(MV78260), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 886 { ARMADAXP(MV78260), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 887 { ARMADAXP(MV78260), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 888 { ARMADAXP(MV78260), "mvsocts",0, ARMADAXP_TS_BASE, ARMADAXP_IRQ_PMU }, 889 { ARMADAXP(MV78260), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 890 { ARMADAXP(MV78260), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 891 { ARMADAXP(MV78260), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 892 { ARMADAXP(MV78260), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 893 { ARMADAXP(MV78260), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 894 { ARMADAXP(MV78260), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 895 { ARMADAXP(MV78260), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 896 { ARMADAXP(MV78260), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 897 { ARMADAXP(MV78260), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 898 { ARMADAXP(MV78260), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 899 { ARMADAXP(MV78260), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 900 #if NMVXPE > 0 901 { ARMADAXP(MV78260), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 902 { ARMADAXP(MV78260), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 903 { ARMADAXP(MV78260), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 904 { ARMADAXP(MV78260), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 905 { ARMADAXP(MV78260), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX }, 906 #else 907 { ARMADAXP(MV78260), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 908 { ARMADAXP(MV78260), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 909 { ARMADAXP(MV78260), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 910 { ARMADAXP(MV78260), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 911 #endif 912 #if NMVXPSEC > 0 913 { ARMADAXP(MV78260), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 914 { ARMADAXP(MV78260), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 }, 915 #else 916 { ARMADAXP(MV78260), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 917 { ARMADAXP(MV78260), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 918 #endif 919 920 { ARMADAXP(MV78460), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 921 { ARMADAXP(MV78460), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 922 { ARMADAXP(MV78460), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 923 { ARMADAXP(MV78460), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 924 { ARMADAXP(MV78460), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 925 { ARMADAXP(MV78460), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 926 { ARMADAXP(MV78460), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 927 { ARMADAXP(MV78460), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 928 { ARMADAXP(MV78460), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 929 { ARMADAXP(MV78460), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 930 { ARMADAXP(MV78460), "mvsocts",0, ARMADAXP_TS_BASE, ARMADAXP_IRQ_PMU }, 931 { ARMADAXP(MV78460), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 932 { ARMADAXP(MV78460), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 933 { ARMADAXP(MV78460), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 934 { ARMADAXP(MV78460), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 935 { ARMADAXP(MV78460), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 936 { ARMADAXP(MV78460), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 937 { ARMADAXP(MV78460), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 938 { ARMADAXP(MV78460), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 939 { ARMADAXP(MV78460), "mvpex", 5, ARMADAXP_PEX3_BASE,ARMADAXP_IRQ_PEX3 }, 940 { ARMADAXP(MV78460), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 941 { ARMADAXP(MV78460), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 942 { ARMADAXP(MV78460), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 943 #if NMVXPE > 0 944 { ARMADAXP(MV78460), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 945 { ARMADAXP(MV78460), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 946 { ARMADAXP(MV78460), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 947 { ARMADAXP(MV78460), "mvxpe", 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX }, 948 { ARMADAXP(MV78460), "mvxpe", 3, ARMADAXP_GBE3_BASE,ARMADAXP_IRQ_GBE3_TH_RXTX }, 949 #else 950 { ARMADAXP(MV78460), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 951 { ARMADAXP(MV78460), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 952 { ARMADAXP(MV78460), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 953 { ARMADAXP(MV78460), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 954 #endif 955 #if NMVXPSEC > 0 956 { ARMADAXP(MV78460), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 957 { ARMADAXP(MV78460), "mvxpsec", 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 }, 958 #else 959 { ARMADAXP(MV78460), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 960 { ARMADAXP(MV78460), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 961 #endif 962 963 { ARMADA370(MV6710), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 964 { ARMADA370(MV6710), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 965 { ARMADA370(MV6710), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 966 { ARMADA370(MV6710), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 967 { ARMADA370(MV6710), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 968 { ARMADA370(MV6710), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 969 { ARMADA370(MV6710), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 970 { ARMADA370(MV6710), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 971 { ARMADA370(MV6710), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 972 { ARMADA370(MV6710), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 973 { ARMADA370(MV6710), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 974 { ARMADA370(MV6710), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 975 { ARMADA370(MV6710), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 976 { ARMADA370(MV6710), "mvspi", 1, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 977 { ARMADA370(MV6710), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 978 #if NMVXPE > 0 979 { ARMADA370(MV6710), "mvxpbm", 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT }, 980 { ARMADA370(MV6710), "mvxpe", 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX }, 981 { ARMADA370(MV6710), "mvxpe", 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX }, 982 #else 983 { ARMADA370(MV6710), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 984 { ARMADA370(MV6710), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 985 #endif 986 #if NMVXPSEC > 0 987 { ARMADA370(MV6710), "mvxpsec", 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 }, 988 #else 989 { ARMADA370(MV6710), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 990 #endif 991 #endif 992 }; 993 994 995 CFATTACH_DECL_NEW(mvsoc, sizeof(struct mvsoc_softc), 996 mvsoc_match, mvsoc_attach, NULL, NULL); 997 998 /* ARGSUSED */ 999 static int 1000 mvsoc_match(device_t parent, struct cfdata *match, void *aux) 1001 { 1002 1003 return 1; 1004 } 1005 1006 /* ARGSUSED */ 1007 static void 1008 mvsoc_attach(device_t parent, device_t self, void *aux) 1009 { 1010 struct mvsoc_softc *sc = device_private(self); 1011 struct marvell_attach_args mva; 1012 enum marvell_tags *tags; 1013 uint16_t model; 1014 uint8_t rev; 1015 int i; 1016 1017 sc->sc_dev = self; 1018 sc->sc_iot = &mvsoc_bs_tag; 1019 sc->sc_addr = vtophys(regbase); 1020 sc->sc_dmat = &mvsoc_bus_dma_tag; 1021 if (bus_space_map(sc->sc_iot, sc->sc_addr, 0x100000, 0, &sc->sc_ioh) != 1022 0) { 1023 aprint_error_dev(self, "can't map registers\n"); 1024 return; 1025 } 1026 1027 model = mvsoc_model(); 1028 rev = mvsoc_rev(); 1029 for (i = 0; i < __arraycount(nametbl); i++) 1030 if (nametbl[i].model == model && nametbl[i].rev == rev) 1031 break; 1032 if (i >= __arraycount(nametbl)) 1033 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 1034 1035 aprint_normal(": Marvell %s %s%s %s\n", 1036 nametbl[i].modelstr, 1037 nametbl[i].revstr != NULL ? "Rev. " : "", 1038 nametbl[i].revstr != NULL ? nametbl[i].revstr : "", 1039 nametbl[i].typestr); 1040 aprint_normal("%s: CPU Clock %d.%03d MHz" 1041 " SysClock %d.%03d MHz TClock %d.%03d MHz\n", 1042 device_xname(self), 1043 mvPclk / 1000000, (mvPclk / 1000) % 1000, 1044 mvSysclk / 1000000, (mvSysclk / 1000) % 1000, 1045 mvTclk / 1000000, (mvTclk / 1000) % 1000); 1046 aprint_naive("\n"); 1047 1048 mvsoc_intr_init(); 1049 1050 for (i = 0; i < __arraycount(tagstbl); i++) 1051 if (tagstbl[i].model == model && tagstbl[i].rev == rev) 1052 break; 1053 if (i >= __arraycount(tagstbl)) 1054 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 1055 tags = tagstbl[i].tags; 1056 1057 if (boothowto & (AB_VERBOSE | AB_DEBUG)) 1058 mvsoc_target_dump(sc); 1059 1060 for (i = 0; i < __arraycount(mvsoc_periphs); i++) { 1061 if (mvsoc_periphs[i].model != model) 1062 continue; 1063 1064 mva.mva_name = mvsoc_periphs[i].name; 1065 mva.mva_model = model; 1066 mva.mva_revision = rev; 1067 mva.mva_iot = sc->sc_iot; 1068 mva.mva_ioh = sc->sc_ioh; 1069 mva.mva_unit = mvsoc_periphs[i].unit; 1070 mva.mva_addr = sc->sc_addr; 1071 mva.mva_offset = mvsoc_periphs[i].offset; 1072 mva.mva_size = 0; 1073 mva.mva_dmat = sc->sc_dmat; 1074 mva.mva_irq = mvsoc_periphs[i].irq; 1075 mva.mva_tags = tags; 1076 1077 /* Skip clock disabled devices */ 1078 if (mvsoc_clkgating != NULL && mvsoc_clkgating(&mva)) { 1079 aprint_normal_dev(self, "%s%d clock disabled\n", 1080 mvsoc_periphs[i].name, mvsoc_periphs[i].unit); 1081 continue; 1082 } 1083 1084 config_found_sm_loc(sc->sc_dev, "mvsoc", NULL, &mva, 1085 mvsoc_print, mvsoc_search); 1086 } 1087 } 1088 1089 static int 1090 mvsoc_print(void *aux, const char *pnp) 1091 { 1092 struct marvell_attach_args *mva = aux; 1093 1094 if (pnp) 1095 aprint_normal("%s at %s unit %d", 1096 mva->mva_name, pnp, mva->mva_unit); 1097 else { 1098 if (mva->mva_unit != MVA_UNIT_DEFAULT) 1099 aprint_normal(" unit %d", mva->mva_unit); 1100 if (mva->mva_offset != MVA_OFFSET_DEFAULT) { 1101 aprint_normal(" offset 0x%04lx", mva->mva_offset); 1102 if (mva->mva_size > 0) 1103 aprint_normal("-0x%04lx", 1104 mva->mva_offset + mva->mva_size - 1); 1105 } 1106 if (mva->mva_irq != MVA_IRQ_DEFAULT) 1107 aprint_normal(" irq %d", mva->mva_irq); 1108 } 1109 1110 return UNCONF; 1111 } 1112 1113 /* ARGSUSED */ 1114 static int 1115 mvsoc_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 1116 { 1117 1118 return config_match(parent, cf, aux); 1119 } 1120 1121 /* ARGSUSED */ 1122 int 1123 marvell_winparams_by_tag(device_t dev, int tag, int *target, int *attribute, 1124 uint64_t *base, uint32_t *size) 1125 { 1126 uint32_t base32; 1127 int rv; 1128 1129 rv = mvsoc_target(tag, target, attribute, &base32, size); 1130 *base = base32; 1131 if (rv == -1) 1132 return -1; 1133 return 0; 1134 } 1135 1136 1137 /* 1138 * These functions is called before bus_space is initialized. 1139 */ 1140 1141 void 1142 mvsoc_bootstrap(bus_addr_t iobase) 1143 { 1144 1145 regbase = iobase; 1146 dsc_base = iobase + MVSOC_DSC_BASE; 1147 mlmb_base = iobase + MVSOC_MLMB_BASE; 1148 pex_base = iobase + MVSOC_PEX_BASE; 1149 #ifdef MVSOC_CONSOLE_EARLY 1150 com_base = iobase + MVSOC_COM0_BASE; 1151 cn_tab = &mvsoc_earlycons; 1152 printf("Hello\n"); 1153 #endif 1154 } 1155 1156 /* 1157 * We can read register of PCI configurations from (MVSOC_PEX_BASE + 0). 1158 */ 1159 uint16_t 1160 mvsoc_model(void) 1161 { 1162 /* 1163 * We read product-id from vendor/device register of PCI-Express. 1164 */ 1165 uint32_t reg; 1166 uint16_t model; 1167 1168 KASSERT(regbase != 0xffffffff); 1169 1170 reg = *(volatile uint32_t *)(pex_base + PCI_ID_REG); 1171 model = PCI_PRODUCT(reg); 1172 1173 #if defined(ORION) 1174 if (model == PCI_PRODUCT_MARVELL_88F5182) { 1175 reg = *(volatile uint32_t *)(regbase + ORION_PMI_BASE + 1176 ORION_PMI_SAMPLE_AT_RESET); 1177 if ((reg & ORION_PMISMPL_TCLK_MASK) == 0) 1178 model = PCI_PRODUCT_MARVELL_88F5082; 1179 } 1180 #endif 1181 #if defined(KIRKWOOD) 1182 if (model == PCI_PRODUCT_MARVELL_88F6281) { 1183 reg = *(volatile uint32_t *)(regbase + KIRKWOOD_MISC_BASE + 1184 KIRKWOOD_MISC_DEVICEID); 1185 if (reg == 1) /* 88F6192 is 1 */ 1186 model = MARVELL_KIRKWOOD_88F6192; 1187 } 1188 #endif 1189 1190 return model; 1191 } 1192 1193 uint8_t 1194 mvsoc_rev(void) 1195 { 1196 uint32_t reg; 1197 uint8_t rev; 1198 1199 KASSERT(regbase != 0xffffffff); 1200 1201 reg = *(volatile uint32_t *)(pex_base + PCI_CLASS_REG); 1202 rev = PCI_REVISION(reg); 1203 1204 return rev; 1205 } 1206 1207 1208 int 1209 mvsoc_target(int tag, uint32_t *target, uint32_t *attr, uint32_t *base, 1210 uint32_t *size) 1211 { 1212 int i; 1213 1214 KASSERT(regbase != 0xffffffff); 1215 1216 if (tag == MVSOC_TAG_INTERNALREG) { 1217 if (target != NULL) 1218 *target = 0; 1219 if (attr != NULL) 1220 *attr = 0; 1221 if (base != NULL) 1222 *base = read_mlmbreg(MVSOC_MLMB_IRBAR) & 1223 MVSOC_MLMB_IRBAR_BASE_MASK; 1224 if (size != NULL) 1225 *size = 0; 1226 1227 return 0; 1228 } 1229 1230 /* sanity check */ 1231 for (i = 0; i < __arraycount(mvsoc_tags); i++) 1232 if (mvsoc_tags[i].tag == tag) 1233 break; 1234 if (i >= __arraycount(mvsoc_tags)) 1235 return -1; 1236 1237 if (target != NULL) 1238 *target = mvsoc_tags[i].target; 1239 if (attr != NULL) 1240 *attr = mvsoc_tags[i].attr; 1241 1242 if (mvsoc_tags[i].target == MVSOC_UNITID_DDR) { 1243 if (tag == MARVELL_TAG_SDRAM_CS0 || 1244 tag == MARVELL_TAG_SDRAM_CS1 || 1245 tag == MARVELL_TAG_SDRAM_CS2 || 1246 tag == MARVELL_TAG_SDRAM_CS3) 1247 return mvsoc_target_ddr(mvsoc_tags[i].attr, base, size); 1248 else if (tag == MARVELL_TAG_AXI_CS0 || 1249 tag == MARVELL_TAG_AXI_CS1) 1250 return mvsoc_target_axi(tag, base, size); 1251 else 1252 return mvsoc_target_ddr3(mvsoc_tags[i].attr, base, 1253 size); 1254 } else 1255 return mvsoc_target_peripheral(mvsoc_tags[i].target, 1256 mvsoc_tags[i].attr, base, size); 1257 } 1258 1259 static int 1260 mvsoc_target_ddr(uint32_t attr, uint32_t *base, uint32_t *size) 1261 { 1262 uint32_t baseaddrreg, sizereg; 1263 int cs; 1264 1265 /* 1266 * Read DDR SDRAM Controller Address Decode Registers 1267 */ 1268 1269 switch (attr) { 1270 case MARVELL_ATTR_SDRAM_CS0: 1271 cs = 0; 1272 break; 1273 case MARVELL_ATTR_SDRAM_CS1: 1274 cs = 1; 1275 break; 1276 case MARVELL_ATTR_SDRAM_CS2: 1277 cs = 2; 1278 break; 1279 case MARVELL_ATTR_SDRAM_CS3: 1280 cs = 3; 1281 break; 1282 default: 1283 aprint_error("unknwon ATTR: 0x%x", attr); 1284 return -1; 1285 } 1286 sizereg = *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSSR(cs)); 1287 if (sizereg & MVSOC_DSC_CSSR_WINEN) { 1288 baseaddrreg = 1289 *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSBAR(cs)); 1290 1291 if (base != NULL) 1292 *base = baseaddrreg & MVSOC_DSC_CSBAR_BASE_MASK; 1293 if (size != NULL) 1294 *size = (sizereg & MVSOC_DSC_CSSR_SIZE_MASK) + 1295 (~MVSOC_DSC_CSSR_SIZE_MASK + 1); 1296 } else { 1297 if (base != NULL) 1298 *base = 0; 1299 if (size != NULL) 1300 *size = 0; 1301 } 1302 return 0; 1303 } 1304 1305 static int 1306 mvsoc_target_ddr3(uint32_t attr, uint32_t *base, uint32_t *size) 1307 { 1308 uint32_t baseaddrreg, sizereg; 1309 int cs, i; 1310 1311 /* 1312 * Read DDR3 SDRAM Address Decoding Registers 1313 */ 1314 1315 switch (attr) { 1316 case MARVELL_ATTR_SDRAM_CS0: 1317 cs = 0; 1318 break; 1319 case MARVELL_ATTR_SDRAM_CS1: 1320 cs = 1; 1321 break; 1322 case MARVELL_ATTR_SDRAM_CS2: 1323 cs = 2; 1324 break; 1325 case MARVELL_ATTR_SDRAM_CS3: 1326 cs = 3; 1327 break; 1328 default: 1329 aprint_error("unknwon ATTR: 0x%x", attr); 1330 return -1; 1331 } 1332 for (i = 0; i < MVSOC_MLMB_NWIN; i++) { 1333 sizereg = read_mlmbreg(MVSOC_MLMB_WINCR(i)); 1334 if ((sizereg & MVSOC_MLMB_WINCR_EN) && 1335 MVSOC_MLMB_WINCR_WINCS(sizereg) == cs) 1336 break; 1337 } 1338 if (i == MVSOC_MLMB_NWIN) { 1339 if (base != NULL) 1340 *base = 0; 1341 if (size != NULL) 1342 *size = 0; 1343 return 0; 1344 } 1345 1346 baseaddrreg = read_mlmbreg(MVSOC_MLMB_WINBAR(i)); 1347 if (base != NULL) 1348 *base = baseaddrreg & MVSOC_MLMB_WINBAR_BASE_MASK; 1349 if (size != NULL) 1350 *size = (sizereg & MVSOC_MLMB_WINCR_SIZE_MASK) + 1351 (~MVSOC_MLMB_WINCR_SIZE_MASK + 1); 1352 return 0; 1353 } 1354 1355 static int 1356 mvsoc_target_axi(int tag, uint32_t *base, uint32_t *size) 1357 { 1358 uint32_t val; 1359 int cs; 1360 1361 /* 1362 * Read MMAP1 Chip Select N the other side of AXI DDR Registers 1363 */ 1364 1365 switch (tag) { 1366 case MARVELL_TAG_AXI_CS0: 1367 cs = 0; 1368 break; 1369 case MARVELL_TAG_AXI_CS1: 1370 cs = 1; 1371 break; 1372 default: 1373 aprint_error("unknwon TAG: 0x%x", tag); 1374 return -1; 1375 } 1376 val = *(volatile uint32_t *)(regbase + MVSOC_AXI_MMAP1(cs)); 1377 if (val & MVSOC_AXI_MMAP1_VALID) { 1378 if (base != NULL) 1379 *base = MVSOC_AXI_MMAP1_STARTADDRESS(val); 1380 if (size != NULL) 1381 *size = MVSOC_AXI_MMAP1_AREALENGTH(val); 1382 } else { 1383 if (base != NULL) 1384 *base = 0; 1385 if (size != NULL) 1386 *size = 0; 1387 } 1388 return 0; 1389 } 1390 1391 static int 1392 mvsoc_target_peripheral(uint32_t target, uint32_t attr, uint32_t *base, 1393 uint32_t *size) 1394 { 1395 uint32_t basereg, ctrlreg, ta, tamask; 1396 int i; 1397 1398 /* 1399 * Read CPU Address Map Registers 1400 */ 1401 1402 ta = MVSOC_MLMB_WCR_TARGET(target) | MVSOC_MLMB_WCR_ATTR(attr); 1403 tamask = MVSOC_MLMB_WCR_TARGET(MVSOC_UNITID_MASK) | 1404 MVSOC_MLMB_WCR_ATTR(MARVELL_ATTR_MASK); 1405 1406 if (base != NULL) 1407 *base = 0; 1408 if (size != NULL) 1409 *size = 0; 1410 1411 for (i = 0; i < nwindow; i++) { 1412 ctrlreg = read_mlmbreg(MVSOC_MLMB_WCR(i)); 1413 if ((ctrlreg & tamask) != ta) 1414 continue; 1415 if (ctrlreg & MVSOC_MLMB_WCR_WINEN) { 1416 basereg = read_mlmbreg(MVSOC_MLMB_WBR(i)); 1417 1418 if (base != NULL) 1419 *base = basereg & MVSOC_MLMB_WBR_BASE_MASK; 1420 if (size != NULL) 1421 *size = (ctrlreg & 1422 MVSOC_MLMB_WCR_SIZE_MASK) + 1423 (~MVSOC_MLMB_WCR_SIZE_MASK + 1); 1424 } 1425 break; 1426 } 1427 return i; 1428 } 1429 1430 int 1431 mvsoc_target_dump(struct mvsoc_softc *sc) 1432 { 1433 uint32_t reg, base, size, target, attr, enable; 1434 int i, n; 1435 1436 for (i = 0, n = 0; i < nwindow; i++) { 1437 reg = read_mlmbreg(MVSOC_MLMB_WCR(i)); 1438 enable = reg & MVSOC_MLMB_WCR_WINEN; 1439 target = MVSOC_MLMB_WCR_GET_TARGET(reg); 1440 attr = MVSOC_MLMB_WCR_GET_ATTR(reg); 1441 size = MVSOC_MLMB_WCR_GET_SIZE(reg); 1442 1443 reg = read_mlmbreg(MVSOC_MLMB_WBR(i)); 1444 base = MVSOC_MLMB_WBR_GET_BASE(reg); 1445 1446 if (!enable) 1447 continue; 1448 1449 aprint_verbose_dev(sc->sc_dev, 1450 "Mbus window %2d: Base 0x%08x Size 0x%08x ", i, base, size); 1451 #ifdef ARMADAXP 1452 armadaxp_attr_dump(sc, target, attr); 1453 #else 1454 mvsoc_attr_dump(sc, target, attr); 1455 #endif 1456 printf("\n"); 1457 n++; 1458 } 1459 1460 return n; 1461 } 1462 1463 int 1464 mvsoc_attr_dump(struct mvsoc_softc *sc, uint32_t target, uint32_t attr) 1465 { 1466 aprint_verbose_dev(sc->sc_dev, "target 0x%x(attr 0x%x)", target, attr); 1467 return 0; 1468 } 1469
Indexes created Thu Oct 23 22:10:10 GMT 2025