mvsoc.c revision 1.3
1 /* $NetBSD: mvsoc.c,v 1.3 2011/07/30 04:34:17 jakllsch Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.3 2011/07/30 04:34:17 jakllsch Exp $"); 30 31 #include "opt_cputypes.h" 32 #include "opt_mvsoc.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pcireg.h> 41 #include <dev/marvell/marvellreg.h> 42 #include <dev/marvell/marvellvar.h> 43 44 #include <arm/marvell/mvsocreg.h> 45 #include <arm/marvell/mvsocvar.h> 46 #include <arm/marvell/orionreg.h> 47 #include <arm/marvell/kirkwoodreg.h> 48 49 #include "locators.h" 50 51 52 static int mvsoc_match(device_t, struct cfdata *, void *); 53 static void mvsoc_attach(device_t, device_t, void *); 54 55 static int mvsoc_print(void *, const char *); 56 static int mvsoc_search(device_t, cfdata_t, const int *, void *); 57 58 uint32_t mvPclk, mvSysclk, mvTclk = 0; 59 int nwindow = 0, nremap = 0; 60 static vaddr_t regbase = 0xffffffff, dsc_base, pex_base; 61 vaddr_t mlmb_base; 62 63 void (*mvsoc_intr_init)(void); 64 65 66 /* attributes */ 67 static struct { 68 int tag; 69 uint32_t attr; 70 uint32_t target; 71 } mvsoc_tags[] = { 72 { MARVELL_TAG_SDRAM_CS0, 73 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 74 { MARVELL_TAG_SDRAM_CS1, 75 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 76 { MARVELL_TAG_SDRAM_CS2, 77 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 78 { MARVELL_TAG_SDRAM_CS3, 79 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 80 81 #if defined(ORION) 82 { ORION_TAG_DEVICE_CS0, 83 ORION_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 84 { ORION_TAG_DEVICE_CS1, 85 ORION_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 86 { ORION_TAG_DEVICE_CS2, 87 ORION_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 88 { ORION_TAG_DEVICE_BOOTCS, 89 ORION_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 90 { ORION_TAG_FLASH_CS, 91 ORION_ATTR_FLASH_CS, MVSOC_UNITID_DEVBUS }, 92 { ORION_TAG_PEX0_MEM, 93 ORION_ATTR_PEX_MEM, ORION_UNITID_PEX }, 94 { ORION_TAG_PEX0_IO, 95 ORION_ATTR_PEX_IO, ORION_UNITID_PEX }, 96 { ORION_TAG_PEX1_MEM, 97 ORION_ATTR_PEX_MEM, ORION_UNITID_PEX1 }, 98 { ORION_TAG_PEX1_IO, 99 ORION_ATTR_PEX_IO, ORION_UNITID_PEX1 }, 100 { ORION_TAG_PCI_MEM, 101 ORION_ATTR_PCI_MEM, ORION_UNITID_PCI }, 102 { ORION_TAG_PCI_IO, 103 ORION_ATTR_PCI_IO, ORION_UNITID_PCI }, 104 { ORION_TAG_CRYPT, 105 ORION_ATTR_CRYPT, ORION_UNITID_CRYPT }, 106 #endif 107 108 #if defined(KIRKWOOD) 109 { KIRKWOOD_TAG_NAND, 110 KIRKWOOD_ATTR_NAND, MVSOC_UNITID_DEVBUS }, 111 { KIRKWOOD_TAG_SPI, 112 KIRKWOOD_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 113 { KIRKWOOD_TAG_BOOTROM, 114 KIRKWOOD_ATTR_BOOTROM, MVSOC_UNITID_DEVBUS }, 115 { KIRKWOOD_TAG_PEX_MEM, 116 KIRKWOOD_ATTR_PEX_MEM, KIRKWOOD_UNITID_PEX }, 117 { KIRKWOOD_TAG_PEX_IO, 118 KIRKWOOD_ATTR_PEX_IO, KIRKWOOD_UNITID_PEX }, 119 { KIRKWOOD_TAG_CRYPT, 120 KIRKWOOD_ATTR_CRYPT, KIRKWOOD_UNITID_CRYPT }, 121 #endif 122 }; 123 124 #if defined(ORION) 125 #define ORION_1(m) MARVELL_ORION_1_ ## m 126 #define ORION_2(m) MARVELL_ORION_2_ ## m 127 #endif 128 #if defined(KIRKWOOD) 129 #undef KIRKWOOD 130 #define KIRKWOOD(m) MARVELL_KIRKWOOD_ ## m 131 #endif 132 #if defined(MV78XX0) 133 #undef MV78XX0 134 #define MV78XX0(m) MARVELL_MV78XX0_ ## m 135 #endif 136 static struct { 137 uint16_t model; 138 uint8_t rev; 139 const char *modelstr; 140 const char *revstr; 141 const char *typestr; 142 } nametbl[] = { 143 #if defined(ORION) 144 { ORION_1(88F1181), 0, "MV88F1181", NULL, "Orion1" }, 145 { ORION_1(88F5082), 2, "MV88F5082", "A2", "Orion1" }, 146 { ORION_1(88F5180N), 3, "MV88F5180N","B1", "Orion1" }, 147 { ORION_1(88F5181), 0, "MV88F5181", "A0", "Orion1" }, 148 { ORION_1(88F5181), 1, "MV88F5181", "A1", "Orion1" }, 149 { ORION_1(88F5181), 2, "MV88F5181", "B0", "Orion1" }, 150 { ORION_1(88F5181), 3, "MV88F5181", "B1", "Orion1" }, 151 { ORION_1(88F5181), 8, "MV88F5181L","A0", "Orion1" }, 152 { ORION_1(88F5181), 9, "MV88F5181L","A1", "Orion1" }, 153 { ORION_1(88F5182), 0, "MV88F5182", "A0", "Orion1" }, 154 { ORION_1(88F5182), 1, "MV88F5182", "A1", "Orion1" }, 155 { ORION_1(88F5182), 2, "MV88F5182", "A2", "Orion1" }, 156 { ORION_1(88F6082), 0, "MV88F6082", "A0", "Orion1" }, 157 { ORION_1(88F6082), 1, "MV88F6082", "A1", "Orion1" }, 158 { ORION_1(88F6183), 0, "MV88F6183", "A0", "Orion1" }, 159 { ORION_1(88F6183), 1, "MV88F6183", "Z0", "Orion1" }, 160 { ORION_1(88W8660), 0, "MV88W8660", "A0", "Orion1" }, 161 { ORION_1(88W8660), 1, "MV88W8660", "A1", "Orion1" }, 162 163 { ORION_2(88F1281), 0, "MV88F1281", "A0", "Orion2" }, 164 { ORION_2(88F5281), 0, "MV88F5281", "A0", "Orion2" }, 165 { ORION_2(88F5281), 1, "MV88F5281", "B0", "Orion2" }, 166 { ORION_2(88F5281), 2, "MV88F5281", "C0", "Orion2" }, 167 { ORION_2(88F5281), 3, "MV88F5281", "C1", "Orion2" }, 168 { ORION_2(88F5281), 4, "MV88F5281", "D0", "Orion2" }, 169 #endif 170 171 #if defined(KIRKWOOD) 172 { KIRKWOOD(88F6180), 2, "88F6180", "A0", "Kirkwood" }, 173 { KIRKWOOD(88F6192), 0, "88F619x", "Z0", "Kirkwood" }, 174 { KIRKWOOD(88F6192), 2, "88F619x", "A0", "Kirkwood" }, 175 { KIRKWOOD(88F6281), 0, "88F6281", "Z0", "Kirkwood" }, 176 { KIRKWOOD(88F6281), 2, "88F6281", "A0", "Kirkwood" }, 177 { KIRKWOOD(88F6281), 3, "88F6281", "A1", "Kirkwood" }, 178 #endif 179 180 #if defined(MV78XX0) 181 { MV78XX0(MV78100), 1, "MV78100", "A0", "Discovery Innovation" }, 182 { MV78XX0(MV78100), 2, "MV78100", "A1", "Discovery Innovation" }, 183 { MV78XX0(MV78200), 1, "MV78200", "A0", "Discovery Innovation" }, 184 #endif 185 }; 186 187 #define OFFSET_DEFAULT MVA_OFFSET_DEFAULT 188 #define IRQ_DEFAULT MVA_IRQ_DEFAULT 189 static const struct mvsoc_periph { 190 int model; 191 const char *name; 192 int unit; 193 bus_size_t offset; 194 int irq; 195 } mvsoc_periphs[] = { 196 #if defined(ORION) 197 { ORION_1(88F1181), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 198 { ORION_1(88F1181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 199 { ORION_1(88F1181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 200 { ORION_1(88F1181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 201 { ORION_1(88F1181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 202 { ORION_1(88F1181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 203 { ORION_1(88F1181), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 204 205 { ORION_1(88F5082), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 206 { ORION_1(88F5082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 207 { ORION_1(88F5082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 208 { ORION_1(88F5082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 209 { ORION_1(88F5082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 210 { ORION_1(88F5082), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 211 // { ORION_1(88F5082), "gtidmac", 0, ORION_IDMAC_BASE, 0 }, 212 { ORION_1(88F5082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 213 { ORION_1(88F5082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 214 { ORION_1(88F5082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 215 { ORION_1(88F5082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 216 { ORION_1(88F5082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 217 218 { ORION_1(88F5180N),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 219 { ORION_1(88F5180N),"mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 220 { ORION_1(88F5180N),"com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 221 { ORION_1(88F5180N),"com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 222 { ORION_1(88F5180N),"ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 223 // { ORION_1(88F5180N),"gtidmac", 0, ORION_IDMAC_BASE, 0 }, 224 { ORION_1(88F5180N),"gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 225 { ORION_1(88F5180N),"gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 226 { ORION_1(88F5180N),"mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 227 { ORION_1(88F5180N),"mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 228 229 { ORION_1(88F5181), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 230 { ORION_1(88F5181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 231 { ORION_1(88F5181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 232 { ORION_1(88F5181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 233 { ORION_1(88F5181), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 234 // { ORION_1(88F5181), "gtidmac", 0, ORION_IDMAC_BASE, 0 }, 235 { ORION_1(88F5181), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 236 { ORION_1(88F5181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 237 { ORION_1(88F5181), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 238 { ORION_1(88F5181), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 239 { ORION_1(88F5181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 240 241 { ORION_1(88F5182), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 242 { ORION_1(88F5182), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 243 { ORION_1(88F5182), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 244 { ORION_1(88F5182), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 245 { ORION_1(88F5182), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 246 { ORION_1(88F5182), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 247 { ORION_1(88F5182), "gtidmac", 0, ORION_IDMAC_BASE, ORION_IRQ_IDMA0 }, 248 { ORION_1(88F5182), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 249 { ORION_1(88F5182), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 250 { ORION_1(88F5182), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 251 { ORION_1(88F5182), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 252 { ORION_1(88F5182), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 253 254 { ORION_1(88F6082), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 255 { ORION_1(88F6082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 256 { ORION_1(88F6082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 257 { ORION_1(88F6082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 258 { ORION_1(88F6082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 259 { ORION_1(88F6082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 260 { ORION_1(88F6082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 261 { ORION_1(88F6082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 262 { ORION_1(88F6082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 263 { ORION_1(88F6082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 264 265 { ORION_1(88F6183), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 266 { ORION_1(88F6183), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 267 { ORION_1(88F6183), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 268 { ORION_1(88F6183), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 269 270 { ORION_1(88W8660), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 271 { ORION_1(88W8660), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 272 { ORION_1(88W8660), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 273 { ORION_1(88W8660), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 274 { ORION_1(88W8660), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 275 // { ORION_1(88W8660), "gtidmac", 0, ORION_IDMAC_BASE, 0 }, 276 { ORION_1(88W8660), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 277 { ORION_1(88W8660), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 278 { ORION_1(88W8660), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 279 { ORION_1(88W8660), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 280 281 { ORION_2(88F1281), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 282 { ORION_2(88F1281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 283 { ORION_2(88F1281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 284 { ORION_2(88F1281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 285 { ORION_2(88F1281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 286 { ORION_2(88F1281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 287 { ORION_2(88F1281), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 288 289 { ORION_2(88F5281), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 290 { ORION_2(88F5281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 291 { ORION_2(88F5281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 292 { ORION_2(88F5281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 293 { ORION_2(88F5281), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 294 // { ORION_2(88F5281), "gtidmac", 0, ORION_IDMAC_BASE, 0 }, 295 { ORION_2(88F5281), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 296 { ORION_2(88F5281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 297 { ORION_2(88F5281), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 298 { ORION_2(88F5281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 299 #endif 300 301 #if defined(KIRKWOOD) 302 { KIRKWOOD(88F6180),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 303 { KIRKWOOD(88F6180),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 304 { KIRKWOOD(88F6180),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 305 { KIRKWOOD(88F6180),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 306 { KIRKWOOD(88F6180),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 307 { KIRKWOOD(88F6180),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 308 // { KIRKWOOD(88F6180),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,? }, 309 { KIRKWOOD(88F6180),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 310 { KIRKWOOD(88F6180),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 311 { KIRKWOOD(88F6180),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 312 { KIRKWOOD(88F6180),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 313 { KIRKWOOD(88F6180),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 314 315 { KIRKWOOD(88F6192),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 316 { KIRKWOOD(88F6192),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 317 { KIRKWOOD(88F6192),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 318 { KIRKWOOD(88F6192),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 319 { KIRKWOOD(88F6192),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 320 { KIRKWOOD(88F6192),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 321 // { KIRKWOOD(88F6192),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,? }, 322 { KIRKWOOD(88F6192),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 323 { KIRKWOOD(88F6192),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 324 { KIRKWOOD(88F6192),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 325 { KIRKWOOD(88F6192),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 326 { KIRKWOOD(88F6192),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 327 { KIRKWOOD(88F6192),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 328 { KIRKWOOD(88F6192),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 329 330 { KIRKWOOD(88F6281),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 331 { KIRKWOOD(88F6281),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 332 { KIRKWOOD(88F6281),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 333 { KIRKWOOD(88F6281),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 334 { KIRKWOOD(88F6281),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 335 { KIRKWOOD(88F6281),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 336 // { KIRKWOOD(88F6281),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,? }, 337 { KIRKWOOD(88F6281),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 338 { KIRKWOOD(88F6281),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 339 { KIRKWOOD(88F6281),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 340 { KIRKWOOD(88F6281),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 341 { KIRKWOOD(88F6281),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 342 { KIRKWOOD(88F6281),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 343 { KIRKWOOD(88F6281),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 344 #endif 345 346 #if defined(MV78XX0) 347 { MV78XX0(MV78100), "mvsoctmr",0,MVSOC_TMR_BASE, IRQ_DEFAULT }, 348 { MV78XX0(MV78100), "mvsocgpp",0,MVSOC_GPP_BASE, MV78XX0_IRQ_GPIOLO7_0 }, 349 { MV78XX0(MV78100), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0INT }, 350 { MV78XX0(MV78100), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1INT }, 351 { MV78XX0(MV78100), "gttwsi",0,MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI }, 352 : 353 354 { MV78XX0(MV78200), "mvsoctmr",0,MVSOC_TMR_BASE, IRQ_DEFAULT }, 355 { MV78XX0(MV78200), "mvsocgpp",0,MVSOC_GPP_BASE, MV78XX0_IRQ_GPIOLO7_0 }, 356 { MV78XX0(MV78200), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0INT }, 357 { MV78XX0(MV78200), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1INT }, 358 { MV78XX0(MV78200), "gttwsi",0,MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI }, 359 : 360 #endif 361 }; 362 363 364 CFATTACH_DECL_NEW(mvsoc, sizeof(struct mvsoc_softc), 365 mvsoc_match, mvsoc_attach, NULL, NULL); 366 367 /* ARGSUSED */ 368 static int 369 mvsoc_match(device_t parent, struct cfdata *match, void *aux) 370 { 371 372 return 1; 373 } 374 375 /* ARGSUSED */ 376 static void 377 mvsoc_attach(device_t parent, device_t self, void *aux) 378 { 379 struct mvsoc_softc *sc = device_private(self); 380 struct marvell_attach_args mva; 381 uint16_t model; 382 uint8_t rev; 383 int i; 384 385 sc->sc_dev = self; 386 sc->sc_iot = &mvsoc_bs_tag; 387 sc->sc_addr = regbase; 388 sc->sc_dmat = &mvsoc_bus_dma_tag; 389 if (bus_space_map(sc->sc_iot, sc->sc_addr, 0x100000, 0, &sc->sc_ioh) != 390 0) { 391 aprint_error_dev(self, "can't map registers\n"); 392 return; 393 } 394 395 model = mvsoc_model(); 396 rev = mvsoc_rev(); 397 for (i = 0; i < __arraycount(nametbl); i++) 398 if (nametbl[i].model == model && nametbl[i].rev == rev) 399 break; 400 if (i >= __arraycount(nametbl)) 401 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 402 403 aprint_normal(": Marvell %s %s%s %s\n", 404 nametbl[i].modelstr, 405 nametbl[i].revstr != NULL ? "Rev. " : "", 406 nametbl[i].revstr != NULL ? nametbl[i].revstr : "", 407 nametbl[i].typestr); 408 aprint_normal("%s: CPU Clock %d.%03d MHz" 409 " SysClock %d.%03d MHz TClock %d.%03d MHz\n", 410 device_xname(self), 411 mvPclk / 1000000, (mvPclk / 1000) % 1000, 412 mvSysclk / 1000000, (mvSysclk / 1000) % 1000, 413 mvTclk / 1000000, (mvTclk / 1000) % 1000); 414 aprint_naive("\n"); 415 416 mvsoc_intr_init(); 417 418 for (i = 0; i < __arraycount(mvsoc_periphs); i++) { 419 if (mvsoc_periphs[i].model != model) 420 continue; 421 422 mva.mva_name = mvsoc_periphs[i].name; 423 mva.mva_model = model; 424 mva.mva_revision = rev; 425 mva.mva_iot = sc->sc_iot; 426 mva.mva_ioh = sc->sc_ioh; 427 mva.mva_unit = mvsoc_periphs[i].unit; 428 mva.mva_addr = sc->sc_addr; 429 mva.mva_offset = mvsoc_periphs[i].offset; 430 mva.mva_size = 0; 431 mva.mva_dmat = sc->sc_dmat; 432 mva.mva_irq = mvsoc_periphs[i].irq; 433 434 config_found_sm_loc(sc->sc_dev, "mvsoc", NULL, &mva, 435 mvsoc_print, mvsoc_search); 436 } 437 } 438 439 static int 440 mvsoc_print(void *aux, const char *pnp) 441 { 442 struct marvell_attach_args *mva = aux; 443 444 if (pnp) 445 aprint_normal("%s at %s unit %d", 446 mva->mva_name, pnp, mva->mva_unit); 447 else { 448 if (mva->mva_unit != MVA_UNIT_DEFAULT) 449 aprint_normal(" unit %d", mva->mva_unit); 450 if (mva->mva_offset != MVA_OFFSET_DEFAULT) { 451 aprint_normal(" offset 0x%04lx", mva->mva_offset); 452 if (mva->mva_size > 0) 453 aprint_normal("-0x%04lx", 454 mva->mva_offset + mva->mva_size - 1); 455 } 456 if (mva->mva_irq != MVA_IRQ_DEFAULT) 457 aprint_normal(" irq %d", mva->mva_irq); 458 } 459 460 return UNCONF; 461 } 462 463 /* ARGSUSED */ 464 static int 465 mvsoc_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 466 { 467 468 return config_match(parent, cf, aux); 469 } 470 471 /* ARGSUSED */ 472 int 473 marvell_winparams_by_tag(device_t dev, int tag, int *target, int *attribute, 474 uint64_t *base, uint32_t *size) 475 { 476 uint32_t base32; 477 int rv; 478 479 rv = mvsoc_target(tag, target, attribute, &base32, size); 480 *base = base32; 481 if (rv == -1) 482 return -1; 483 return 0; 484 } 485 486 487 /* 488 * These functions is called before bus_space is initialized. 489 */ 490 491 void 492 mvsoc_bootstrap(bus_addr_t iobase) 493 { 494 495 regbase = iobase; 496 dsc_base = iobase + MVSOC_DSC_BASE; 497 mlmb_base = iobase + MVSOC_MLMB_BASE; 498 pex_base = iobase + MVSOC_PEX_BASE; 499 } 500 501 /* 502 * We can read register of PCI configurations from (MVSOC_PEX_BASE + 0). 503 */ 504 uint16_t 505 mvsoc_model() 506 { 507 /* 508 * We read product-id from vendor/device register of PCI-Express. 509 */ 510 uint32_t reg; 511 uint16_t model; 512 513 KASSERT(regbase != 0xffffffff); 514 515 reg = *(volatile uint32_t *)(pex_base + PCI_ID_REG); 516 model = PCI_PRODUCT(reg); 517 518 #if defined(ORION) 519 if (model == PCI_PRODUCT_MARVELL_88F5182) { 520 reg = *(volatile uint32_t *)(regbase + ORION_PMI_BASE + 521 ORION_PMI_SAMPLE_AT_RESET); 522 if ((reg & ORION_PMISMPL_TCLK_MASK) == 0) 523 model = PCI_PRODUCT_MARVELL_88F5082; 524 } 525 #endif 526 527 return model; 528 } 529 530 uint8_t 531 mvsoc_rev() 532 { 533 uint32_t reg; 534 uint8_t rev; 535 536 KASSERT(regbase != 0xffffffff); 537 538 reg = *(volatile uint32_t *)(pex_base + PCI_CLASS_REG); 539 rev = PCI_REVISION(reg); 540 541 return rev; 542 } 543 544 545 int 546 mvsoc_target(int tag, uint32_t *target, uint32_t *attr, uint32_t *base, 547 uint32_t *size) 548 { 549 int i; 550 551 KASSERT(regbase != 0xffffffff); 552 553 if (tag == MVSOC_TAG_INTERNALREG) { 554 if (target != NULL) 555 *target = 0; 556 if (attr != NULL) 557 *attr = 0; 558 if (base != NULL) 559 *base = read_mlmbreg(MVSOC_MLMB_IRBAR) & 560 MVSOC_MLMB_IRBAR_BASE_MASK; 561 if (size != NULL) 562 *size = 0; 563 564 return 0; 565 } 566 567 /* sanity check */ 568 for (i = 0; i < __arraycount(mvsoc_tags); i++) 569 if (mvsoc_tags[i].tag == tag) 570 break; 571 if (i >= __arraycount(mvsoc_tags)) 572 return -1; 573 574 if (target != NULL) 575 *target = mvsoc_tags[i].target; 576 if (attr != NULL) 577 *attr = mvsoc_tags[i].attr; 578 579 if (mvsoc_tags[i].target == MVSOC_UNITID_DDR) { 580 /* 581 * Read DDR SDRAM Controller Address Decode Registers 582 */ 583 uint32_t baseaddrreg, sizereg; 584 int cs = 0; 585 586 switch (mvsoc_tags[i].attr) { 587 case MARVELL_ATTR_SDRAM_CS0: 588 cs = 0; 589 break; 590 case MARVELL_ATTR_SDRAM_CS1: 591 cs = 1; 592 break; 593 case MARVELL_ATTR_SDRAM_CS2: 594 cs = 2; 595 break; 596 case MARVELL_ATTR_SDRAM_CS3: 597 cs = 3; 598 break; 599 } 600 sizereg = *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSSR(cs)); 601 if (sizereg & MVSOC_DSC_CSSR_WINEN) { 602 baseaddrreg = *(volatile uint32_t *)(dsc_base + 603 MVSOC_DSC_CSBAR(cs)); 604 605 if (base != NULL) 606 *base = baseaddrreg & MVSOC_DSC_CSBAR_BASE_MASK; 607 if (size != NULL) 608 *size = (sizereg & MVSOC_DSC_CSSR_SIZE_MASK) + 609 (~MVSOC_DSC_CSSR_SIZE_MASK + 1); 610 } else { 611 if (base != NULL) 612 *base = 0; 613 if (size != NULL) 614 *size = 0; 615 } 616 return 0; 617 } else { 618 /* 619 * Read CPU Address Map Registers 620 */ 621 uint32_t basereg, ctrlreg, ta, tamask; 622 623 ta = MVSOC_MLMB_WCR_TARGET(mvsoc_tags[i].target) | 624 MVSOC_MLMB_WCR_ATTR(mvsoc_tags[i].attr); 625 tamask = MVSOC_MLMB_WCR_TARGET(MVSOC_UNITID_MASK) | 626 MVSOC_MLMB_WCR_ATTR(MARVELL_ATTR_MASK); 627 628 if (base != NULL) 629 *base = 0; 630 if (size != NULL) 631 *size = 0; 632 633 for (i = 0; i < nwindow; i++) { 634 ctrlreg = read_mlmbreg(MVSOC_MLMB_WCR(i)); 635 if ((ctrlreg & tamask) != ta) 636 continue; 637 if (ctrlreg & MVSOC_MLMB_WCR_WINEN) { 638 basereg = read_mlmbreg(MVSOC_MLMB_WBR(i)); 639 640 if (base != NULL) 641 *base = 642 basereg & MVSOC_MLMB_WBR_BASE_MASK; 643 if (size != NULL) 644 *size = (ctrlreg & 645 MVSOC_MLMB_WCR_SIZE_MASK) + 646 (~MVSOC_MLMB_WCR_SIZE_MASK + 1); 647 } 648 break; 649 } 650 return i; 651 } 652 } 653
Indexes created Thu Oct 23 22:10:10 GMT 2025