mvsoc.c revision 1.5.2.1
1 /* $NetBSD: mvsoc.c,v 1.5.2.1 2012/12/11 04:44:02 riz Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.5.2.1 2012/12/11 04:44:02 riz Exp $"); 30 31 #include "opt_cputypes.h" 32 #include "opt_mvsoc.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pcireg.h> 41 #include <dev/marvell/marvellreg.h> 42 #include <dev/marvell/marvellvar.h> 43 44 #include <arm/marvell/mvsocreg.h> 45 #include <arm/marvell/mvsocvar.h> 46 #include <arm/marvell/orionreg.h> 47 #include <arm/marvell/kirkwoodreg.h> 48 49 #include "locators.h" 50 51 52 static int mvsoc_match(device_t, struct cfdata *, void *); 53 static void mvsoc_attach(device_t, device_t, void *); 54 55 static int mvsoc_print(void *, const char *); 56 static int mvsoc_search(device_t, cfdata_t, const int *, void *); 57 58 uint32_t mvPclk, mvSysclk, mvTclk = 0; 59 int nwindow = 0, nremap = 0; 60 static vaddr_t regbase = 0xffffffff, dsc_base, pex_base; 61 vaddr_t mlmb_base; 62 63 void (*mvsoc_intr_init)(void); 64 65 66 /* attributes */ 67 static struct { 68 int tag; 69 uint32_t attr; 70 uint32_t target; 71 } mvsoc_tags[] = { 72 { MARVELL_TAG_SDRAM_CS0, 73 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 74 { MARVELL_TAG_SDRAM_CS1, 75 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 76 { MARVELL_TAG_SDRAM_CS2, 77 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 78 { MARVELL_TAG_SDRAM_CS3, 79 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 80 81 #if defined(ORION) 82 { ORION_TAG_DEVICE_CS0, 83 ORION_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 84 { ORION_TAG_DEVICE_CS1, 85 ORION_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 86 { ORION_TAG_DEVICE_CS2, 87 ORION_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 88 { ORION_TAG_DEVICE_BOOTCS, 89 ORION_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 90 { ORION_TAG_FLASH_CS, 91 ORION_ATTR_FLASH_CS, MVSOC_UNITID_DEVBUS }, 92 { ORION_TAG_PEX0_MEM, 93 ORION_ATTR_PEX_MEM, ORION_UNITID_PEX }, 94 { ORION_TAG_PEX0_IO, 95 ORION_ATTR_PEX_IO, ORION_UNITID_PEX }, 96 { ORION_TAG_PEX1_MEM, 97 ORION_ATTR_PEX_MEM, ORION_UNITID_PEX1 }, 98 { ORION_TAG_PEX1_IO, 99 ORION_ATTR_PEX_IO, ORION_UNITID_PEX1 }, 100 { ORION_TAG_PCI_MEM, 101 ORION_ATTR_PCI_MEM, ORION_UNITID_PCI }, 102 { ORION_TAG_PCI_IO, 103 ORION_ATTR_PCI_IO, ORION_UNITID_PCI }, 104 { ORION_TAG_CRYPT, 105 ORION_ATTR_CRYPT, ORION_UNITID_CRYPT }, 106 #endif 107 108 #if defined(KIRKWOOD) 109 { KIRKWOOD_TAG_NAND, 110 KIRKWOOD_ATTR_NAND, MVSOC_UNITID_DEVBUS }, 111 { KIRKWOOD_TAG_SPI, 112 KIRKWOOD_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 113 { KIRKWOOD_TAG_BOOTROM, 114 KIRKWOOD_ATTR_BOOTROM, MVSOC_UNITID_DEVBUS }, 115 { KIRKWOOD_TAG_PEX_MEM, 116 KIRKWOOD_ATTR_PEX_MEM, KIRKWOOD_UNITID_PEX }, 117 { KIRKWOOD_TAG_PEX_IO, 118 KIRKWOOD_ATTR_PEX_IO, KIRKWOOD_UNITID_PEX }, 119 { KIRKWOOD_TAG_CRYPT, 120 KIRKWOOD_ATTR_CRYPT, KIRKWOOD_UNITID_CRYPT }, 121 #endif 122 }; 123 124 #if defined(ORION) 125 #define ORION_1(m) MARVELL_ORION_1_ ## m 126 #define ORION_2(m) MARVELL_ORION_2_ ## m 127 #endif 128 #if defined(KIRKWOOD) 129 #undef KIRKWOOD 130 #define KIRKWOOD(m) MARVELL_KIRKWOOD_ ## m 131 #endif 132 #if defined(MV78XX0) 133 #undef MV78XX0 134 #define MV78XX0(m) MARVELL_MV78XX0_ ## m 135 #endif 136 static struct { 137 uint16_t model; 138 uint8_t rev; 139 const char *modelstr; 140 const char *revstr; 141 const char *typestr; 142 } nametbl[] = { 143 #if defined(ORION) 144 { ORION_1(88F1181), 0, "MV88F1181", NULL, "Orion1" }, 145 { ORION_1(88F5082), 2, "MV88F5082", "A2", "Orion1" }, 146 { ORION_1(88F5180N), 3, "MV88F5180N","B1", "Orion1" }, 147 { ORION_1(88F5181), 0, "MV88F5181", "A0", "Orion1" }, 148 { ORION_1(88F5181), 1, "MV88F5181", "A1", "Orion1" }, 149 { ORION_1(88F5181), 2, "MV88F5181", "B0", "Orion1" }, 150 { ORION_1(88F5181), 3, "MV88F5181", "B1", "Orion1" }, 151 { ORION_1(88F5181), 8, "MV88F5181L","A0", "Orion1" }, 152 { ORION_1(88F5181), 9, "MV88F5181L","A1", "Orion1" }, 153 { ORION_1(88F5182), 0, "MV88F5182", "A0", "Orion1" }, 154 { ORION_1(88F5182), 1, "MV88F5182", "A1", "Orion1" }, 155 { ORION_1(88F5182), 2, "MV88F5182", "A2", "Orion1" }, 156 { ORION_1(88F6082), 0, "MV88F6082", "A0", "Orion1" }, 157 { ORION_1(88F6082), 1, "MV88F6082", "A1", "Orion1" }, 158 { ORION_1(88F6183), 0, "MV88F6183", "A0", "Orion1" }, 159 { ORION_1(88F6183), 1, "MV88F6183", "Z0", "Orion1" }, 160 { ORION_1(88W8660), 0, "MV88W8660", "A0", "Orion1" }, 161 { ORION_1(88W8660), 1, "MV88W8660", "A1", "Orion1" }, 162 163 { ORION_2(88F1281), 0, "MV88F1281", "A0", "Orion2" }, 164 { ORION_2(88F5281), 0, "MV88F5281", "A0", "Orion2" }, 165 { ORION_2(88F5281), 1, "MV88F5281", "B0", "Orion2" }, 166 { ORION_2(88F5281), 2, "MV88F5281", "C0", "Orion2" }, 167 { ORION_2(88F5281), 3, "MV88F5281", "C1", "Orion2" }, 168 { ORION_2(88F5281), 4, "MV88F5281", "D0", "Orion2" }, 169 #endif 170 171 #if defined(KIRKWOOD) 172 { KIRKWOOD(88F6180), 2, "88F6180", "A0", "Kirkwood" }, 173 { KIRKWOOD(88F6192), 0, "88F619x", "Z0", "Kirkwood" }, 174 { KIRKWOOD(88F6192), 2, "88F619x", "A0", "Kirkwood" }, 175 { KIRKWOOD(88F6192), 3, "88F619x", "A1", "Kirkwood" }, 176 { KIRKWOOD(88F6281), 0, "88F6281", "Z0", "Kirkwood" }, 177 { KIRKWOOD(88F6281), 2, "88F6281", "A0", "Kirkwood" }, 178 { KIRKWOOD(88F6281), 3, "88F6281", "A1", "Kirkwood" }, 179 #endif 180 181 #if defined(MV78XX0) 182 { MV78XX0(MV78100), 1, "MV78100", "A0", "Discovery Innovation" }, 183 { MV78XX0(MV78100), 2, "MV78100", "A1", "Discovery Innovation" }, 184 { MV78XX0(MV78200), 1, "MV78200", "A0", "Discovery Innovation" }, 185 #endif 186 }; 187 188 #define OFFSET_DEFAULT MVA_OFFSET_DEFAULT 189 #define IRQ_DEFAULT MVA_IRQ_DEFAULT 190 static const struct mvsoc_periph { 191 int model; 192 const char *name; 193 int unit; 194 bus_size_t offset; 195 int irq; 196 uint32_t clkpwr_bit; 197 } mvsoc_periphs[] = { 198 #if defined(ORION) 199 { ORION_1(88F1181), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 200 { ORION_1(88F1181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 201 { ORION_1(88F1181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 202 { ORION_1(88F1181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 203 { ORION_1(88F1181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 204 { ORION_1(88F1181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 205 { ORION_1(88F1181), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 206 207 { ORION_1(88F5082), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 208 { ORION_1(88F5082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 209 { ORION_1(88F5082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 210 { ORION_1(88F5082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 211 { ORION_1(88F5082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 212 { ORION_1(88F5082), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 213 // { ORION_1(88F5082), "gtidmac", 0, ORION_IDMAC_BASE, 0 }, 214 { ORION_1(88F5082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 215 { ORION_1(88F5082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 216 { ORION_1(88F5082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 217 { ORION_1(88F5082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 218 { ORION_1(88F5082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 219 220 { ORION_1(88F5180N),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 221 { ORION_1(88F5180N),"mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 222 { ORION_1(88F5180N),"com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 223 { ORION_1(88F5180N),"com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 224 { ORION_1(88F5180N),"ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 225 // { ORION_1(88F5180N),"gtidmac", 0, ORION_IDMAC_BASE, 0 }, 226 { ORION_1(88F5180N),"gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 227 { ORION_1(88F5180N),"gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 228 { ORION_1(88F5180N),"mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 229 { ORION_1(88F5180N),"mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 230 231 { ORION_1(88F5181), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 232 { ORION_1(88F5181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 233 { ORION_1(88F5181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 234 { ORION_1(88F5181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 235 { ORION_1(88F5181), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 236 // { ORION_1(88F5181), "gtidmac", 0, ORION_IDMAC_BASE, 0 }, 237 { ORION_1(88F5181), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 238 { ORION_1(88F5181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 239 { ORION_1(88F5181), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 240 { ORION_1(88F5181), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 241 { ORION_1(88F5181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 242 243 { ORION_1(88F5182), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 244 { ORION_1(88F5182), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 245 { ORION_1(88F5182), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 246 { ORION_1(88F5182), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 247 { ORION_1(88F5182), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 248 { ORION_1(88F5182), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 249 { ORION_1(88F5182), "gtidmac", 0, ORION_IDMAC_BASE, ORION_IRQ_IDMA0 }, 250 { ORION_1(88F5182), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 251 { ORION_1(88F5182), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 252 { ORION_1(88F5182), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 253 { ORION_1(88F5182), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 254 { ORION_1(88F5182), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 255 256 { ORION_1(88F6082), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 257 { ORION_1(88F6082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 258 { ORION_1(88F6082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 259 { ORION_1(88F6082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 260 { ORION_1(88F6082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 261 { ORION_1(88F6082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 262 { ORION_1(88F6082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 263 { ORION_1(88F6082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 264 { ORION_1(88F6082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 265 { ORION_1(88F6082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 266 267 { ORION_1(88F6183), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 268 { ORION_1(88F6183), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 269 { ORION_1(88F6183), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 270 { ORION_1(88F6183), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 271 272 { ORION_1(88W8660), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 273 { ORION_1(88W8660), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 274 { ORION_1(88W8660), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 275 { ORION_1(88W8660), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 276 { ORION_1(88W8660), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 277 // { ORION_1(88W8660), "gtidmac", 0, ORION_IDMAC_BASE, 0 }, 278 { ORION_1(88W8660), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 279 { ORION_1(88W8660), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 280 { ORION_1(88W8660), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 281 { ORION_1(88W8660), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 282 283 { ORION_2(88F1281), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 284 { ORION_2(88F1281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 285 { ORION_2(88F1281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 286 { ORION_2(88F1281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 287 { ORION_2(88F1281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 288 { ORION_2(88F1281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 289 { ORION_2(88F1281), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 290 291 { ORION_2(88F5281), "mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 292 { ORION_2(88F5281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 293 { ORION_2(88F5281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 294 { ORION_2(88F5281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 295 { ORION_2(88F5281), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 296 // { ORION_2(88F5281), "gtidmac", 0, ORION_IDMAC_BASE, 0 }, 297 { ORION_2(88F5281), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 298 { ORION_2(88F5281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 299 { ORION_2(88F5281), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 300 { ORION_2(88F5281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 301 #endif 302 303 #if defined(KIRKWOOD) 304 { KIRKWOOD(88F6180),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 305 { KIRKWOOD(88F6180),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 306 { KIRKWOOD(88F6180),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 307 { KIRKWOOD(88F6180),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 308 { KIRKWOOD(88F6180),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 309 { KIRKWOOD(88F6180),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 310 // { KIRKWOOD(88F6180),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,? }, 311 { KIRKWOOD(88F6180),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 312 { KIRKWOOD(88F6180),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 313 { KIRKWOOD(88F6180),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 314 { KIRKWOOD(88F6180),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 315 { KIRKWOOD(88F6180),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 316 317 { KIRKWOOD(88F6192),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 318 { KIRKWOOD(88F6192),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 319 { KIRKWOOD(88F6192),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 320 { KIRKWOOD(88F6192),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 321 { KIRKWOOD(88F6192),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 322 { KIRKWOOD(88F6192),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 323 // { KIRKWOOD(88F6192),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,? }, 324 { KIRKWOOD(88F6192),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 325 { KIRKWOOD(88F6192),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 326 { KIRKWOOD(88F6192),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 327 { KIRKWOOD(88F6192),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 328 { KIRKWOOD(88F6192),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 329 { KIRKWOOD(88F6192),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 330 { KIRKWOOD(88F6192),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 331 332 { KIRKWOOD(88F6281),"mvsoctmr",0, MVSOC_TMR_BASE, IRQ_DEFAULT }, 333 { KIRKWOOD(88F6281),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 334 { KIRKWOOD(88F6281),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 335 { KIRKWOOD(88F6281),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 336 { KIRKWOOD(88F6281),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 337 { KIRKWOOD(88F6281),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT, 338 MVSOC_MLMB_CLKGATING_BIT(3) }, 339 // { KIRKWOOD(88F6281),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,? }, 340 { KIRKWOOD(88F6281),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 341 { KIRKWOOD(88F6281),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT, 342 MVSOC_MLMB_CLKGATING_BIT(17) }, 343 { KIRKWOOD(88F6281),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT, 344 MVSOC_MLMB_CLKGATING_BIT(0) }, 345 { KIRKWOOD(88F6281),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT, 346 MVSOC_MLMB_CLKGATING_BIT(19) }, 347 { KIRKWOOD(88F6281),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT, 348 MVSOC_MLMB_CLKGATING_BIT(2) }, 349 { KIRKWOOD(88F6281),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA, 350 MVSOC_MLMB_CLKGATING_BIT(14) | 351 MVSOC_MLMB_CLKGATING_BIT(15) }, 352 { KIRKWOOD(88F6281),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT, 353 MVSOC_MLMB_CLKGATING_BIT(4) }, 354 #endif 355 356 #if defined(MV78XX0) 357 { MV78XX0(MV78100), "mvsoctmr",0,MVSOC_TMR_BASE, IRQ_DEFAULT }, 358 { MV78XX0(MV78100), "mvsocgpp",0,MVSOC_GPP_BASE, MV78XX0_IRQ_GPIOLO7_0 }, 359 { MV78XX0(MV78100), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0INT }, 360 { MV78XX0(MV78100), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1INT }, 361 { MV78XX0(MV78100), "gttwsi",0,MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI }, 362 : 363 364 { MV78XX0(MV78200), "mvsoctmr",0,MVSOC_TMR_BASE, IRQ_DEFAULT }, 365 { MV78XX0(MV78200), "mvsocgpp",0,MVSOC_GPP_BASE, MV78XX0_IRQ_GPIOLO7_0 }, 366 { MV78XX0(MV78200), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0INT }, 367 { MV78XX0(MV78200), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1INT }, 368 { MV78XX0(MV78200), "gttwsi",0,MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI }, 369 : 370 #endif 371 }; 372 373 374 CFATTACH_DECL_NEW(mvsoc, sizeof(struct mvsoc_softc), 375 mvsoc_match, mvsoc_attach, NULL, NULL); 376 377 /* ARGSUSED */ 378 static int 379 mvsoc_match(device_t parent, struct cfdata *match, void *aux) 380 { 381 382 return 1; 383 } 384 385 /* ARGSUSED */ 386 static void 387 mvsoc_attach(device_t parent, device_t self, void *aux) 388 { 389 struct mvsoc_softc *sc = device_private(self); 390 struct marvell_attach_args mva; 391 uint16_t model; 392 uint8_t rev; 393 uint32_t clkpwr, clkpwrbit; 394 int i; 395 396 sc->sc_dev = self; 397 sc->sc_iot = &mvsoc_bs_tag; 398 sc->sc_addr = regbase; 399 sc->sc_dmat = &mvsoc_bus_dma_tag; 400 if (bus_space_map(sc->sc_iot, sc->sc_addr, 0x100000, 0, &sc->sc_ioh) != 401 0) { 402 aprint_error_dev(self, "can't map registers\n"); 403 return; 404 } 405 406 model = mvsoc_model(); 407 rev = mvsoc_rev(); 408 for (i = 0; i < __arraycount(nametbl); i++) 409 if (nametbl[i].model == model && nametbl[i].rev == rev) 410 break; 411 if (i >= __arraycount(nametbl)) 412 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 413 414 aprint_normal(": Marvell %s %s%s %s\n", 415 nametbl[i].modelstr, 416 nametbl[i].revstr != NULL ? "Rev. " : "", 417 nametbl[i].revstr != NULL ? nametbl[i].revstr : "", 418 nametbl[i].typestr); 419 aprint_normal("%s: CPU Clock %d.%03d MHz" 420 " SysClock %d.%03d MHz TClock %d.%03d MHz\n", 421 device_xname(self), 422 mvPclk / 1000000, (mvPclk / 1000) % 1000, 423 mvSysclk / 1000000, (mvSysclk / 1000) % 1000, 424 mvTclk / 1000000, (mvTclk / 1000) % 1000); 425 aprint_naive("\n"); 426 427 mvsoc_intr_init(); 428 429 for (i = 0; i < __arraycount(mvsoc_periphs); i++) { 430 if (mvsoc_periphs[i].model != model) 431 continue; 432 433 /* Skip clock disabled devices */ 434 clkpwrbit = mvsoc_periphs[i].clkpwr_bit; 435 if (clkpwrbit != 0) { 436 clkpwr = read_mlmbreg(MVSOC_MLMB_CLKGATING); 437 438 if ((clkpwr & clkpwrbit) == 0) { 439 aprint_normal("%s: %s%d clock disabled\n", 440 device_xname(self), 441 mvsoc_periphs[i].name, 442 mvsoc_periphs[i].unit); 443 continue; 444 } 445 } 446 447 mva.mva_name = mvsoc_periphs[i].name; 448 mva.mva_model = model; 449 mva.mva_revision = rev; 450 mva.mva_iot = sc->sc_iot; 451 mva.mva_ioh = sc->sc_ioh; 452 mva.mva_unit = mvsoc_periphs[i].unit; 453 mva.mva_addr = sc->sc_addr; 454 mva.mva_offset = mvsoc_periphs[i].offset; 455 mva.mva_size = 0; 456 mva.mva_dmat = sc->sc_dmat; 457 mva.mva_irq = mvsoc_periphs[i].irq; 458 459 config_found_sm_loc(sc->sc_dev, "mvsoc", NULL, &mva, 460 mvsoc_print, mvsoc_search); 461 } 462 } 463 464 static int 465 mvsoc_print(void *aux, const char *pnp) 466 { 467 struct marvell_attach_args *mva = aux; 468 469 if (pnp) 470 aprint_normal("%s at %s unit %d", 471 mva->mva_name, pnp, mva->mva_unit); 472 else { 473 if (mva->mva_unit != MVA_UNIT_DEFAULT) 474 aprint_normal(" unit %d", mva->mva_unit); 475 if (mva->mva_offset != MVA_OFFSET_DEFAULT) { 476 aprint_normal(" offset 0x%04lx", mva->mva_offset); 477 if (mva->mva_size > 0) 478 aprint_normal("-0x%04lx", 479 mva->mva_offset + mva->mva_size - 1); 480 } 481 if (mva->mva_irq != MVA_IRQ_DEFAULT) 482 aprint_normal(" irq %d", mva->mva_irq); 483 } 484 485 return UNCONF; 486 } 487 488 /* ARGSUSED */ 489 static int 490 mvsoc_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 491 { 492 493 return config_match(parent, cf, aux); 494 } 495 496 /* ARGSUSED */ 497 int 498 marvell_winparams_by_tag(device_t dev, int tag, int *target, int *attribute, 499 uint64_t *base, uint32_t *size) 500 { 501 uint32_t base32; 502 int rv; 503 504 rv = mvsoc_target(tag, target, attribute, &base32, size); 505 *base = base32; 506 if (rv == -1) 507 return -1; 508 return 0; 509 } 510 511 512 /* 513 * These functions is called before bus_space is initialized. 514 */ 515 516 void 517 mvsoc_bootstrap(bus_addr_t iobase) 518 { 519 520 regbase = iobase; 521 dsc_base = iobase + MVSOC_DSC_BASE; 522 mlmb_base = iobase + MVSOC_MLMB_BASE; 523 pex_base = iobase + MVSOC_PEX_BASE; 524 } 525 526 /* 527 * We can read register of PCI configurations from (MVSOC_PEX_BASE + 0). 528 */ 529 uint16_t 530 mvsoc_model(void) 531 { 532 /* 533 * We read product-id from vendor/device register of PCI-Express. 534 */ 535 uint32_t reg; 536 uint16_t model; 537 538 KASSERT(regbase != 0xffffffff); 539 540 reg = *(volatile uint32_t *)(pex_base + PCI_ID_REG); 541 model = PCI_PRODUCT(reg); 542 543 #if defined(ORION) 544 if (model == PCI_PRODUCT_MARVELL_88F5182) { 545 reg = *(volatile uint32_t *)(regbase + ORION_PMI_BASE + 546 ORION_PMI_SAMPLE_AT_RESET); 547 if ((reg & ORION_PMISMPL_TCLK_MASK) == 0) 548 model = PCI_PRODUCT_MARVELL_88F5082; 549 } 550 #endif 551 552 return model; 553 } 554 555 uint8_t 556 mvsoc_rev(void) 557 { 558 uint32_t reg; 559 uint8_t rev; 560 561 KASSERT(regbase != 0xffffffff); 562 563 reg = *(volatile uint32_t *)(pex_base + PCI_CLASS_REG); 564 rev = PCI_REVISION(reg); 565 566 return rev; 567 } 568 569 570 int 571 mvsoc_target(int tag, uint32_t *target, uint32_t *attr, uint32_t *base, 572 uint32_t *size) 573 { 574 int i; 575 576 KASSERT(regbase != 0xffffffff); 577 578 if (tag == MVSOC_TAG_INTERNALREG) { 579 if (target != NULL) 580 *target = 0; 581 if (attr != NULL) 582 *attr = 0; 583 if (base != NULL) 584 *base = read_mlmbreg(MVSOC_MLMB_IRBAR) & 585 MVSOC_MLMB_IRBAR_BASE_MASK; 586 if (size != NULL) 587 *size = 0; 588 589 return 0; 590 } 591 592 /* sanity check */ 593 for (i = 0; i < __arraycount(mvsoc_tags); i++) 594 if (mvsoc_tags[i].tag == tag) 595 break; 596 if (i >= __arraycount(mvsoc_tags)) 597 return -1; 598 599 if (target != NULL) 600 *target = mvsoc_tags[i].target; 601 if (attr != NULL) 602 *attr = mvsoc_tags[i].attr; 603 604 if (mvsoc_tags[i].target == MVSOC_UNITID_DDR) { 605 /* 606 * Read DDR SDRAM Controller Address Decode Registers 607 */ 608 uint32_t baseaddrreg, sizereg; 609 int cs = 0; 610 611 switch (mvsoc_tags[i].attr) { 612 case MARVELL_ATTR_SDRAM_CS0: 613 cs = 0; 614 break; 615 case MARVELL_ATTR_SDRAM_CS1: 616 cs = 1; 617 break; 618 case MARVELL_ATTR_SDRAM_CS2: 619 cs = 2; 620 break; 621 case MARVELL_ATTR_SDRAM_CS3: 622 cs = 3; 623 break; 624 } 625 sizereg = *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSSR(cs)); 626 if (sizereg & MVSOC_DSC_CSSR_WINEN) { 627 baseaddrreg = *(volatile uint32_t *)(dsc_base + 628 MVSOC_DSC_CSBAR(cs)); 629 630 if (base != NULL) 631 *base = baseaddrreg & MVSOC_DSC_CSBAR_BASE_MASK; 632 if (size != NULL) 633 *size = (sizereg & MVSOC_DSC_CSSR_SIZE_MASK) + 634 (~MVSOC_DSC_CSSR_SIZE_MASK + 1); 635 } else { 636 if (base != NULL) 637 *base = 0; 638 if (size != NULL) 639 *size = 0; 640 } 641 return 0; 642 } else { 643 /* 644 * Read CPU Address Map Registers 645 */ 646 uint32_t basereg, ctrlreg, ta, tamask; 647 648 ta = MVSOC_MLMB_WCR_TARGET(mvsoc_tags[i].target) | 649 MVSOC_MLMB_WCR_ATTR(mvsoc_tags[i].attr); 650 tamask = MVSOC_MLMB_WCR_TARGET(MVSOC_UNITID_MASK) | 651 MVSOC_MLMB_WCR_ATTR(MARVELL_ATTR_MASK); 652 653 if (base != NULL) 654 *base = 0; 655 if (size != NULL) 656 *size = 0; 657 658 for (i = 0; i < nwindow; i++) { 659 ctrlreg = read_mlmbreg(MVSOC_MLMB_WCR(i)); 660 if ((ctrlreg & tamask) != ta) 661 continue; 662 if (ctrlreg & MVSOC_MLMB_WCR_WINEN) { 663 basereg = read_mlmbreg(MVSOC_MLMB_WBR(i)); 664 665 if (base != NULL) 666 *base = 667 basereg & MVSOC_MLMB_WBR_BASE_MASK; 668 if (size != NULL) 669 *size = (ctrlreg & 670 MVSOC_MLMB_WCR_SIZE_MASK) + 671 (~MVSOC_MLMB_WCR_SIZE_MASK + 1); 672 } 673 break; 674 } 675 return i; 676 } 677 } 678
Indexes created Thu Oct 23 22:10:10 GMT 2025