mvsoc.c revision 1.9.2.3
1 /* $NetBSD: mvsoc.c,v 1.9.2.3 2014/08/20 00:02:47 tls Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2013, 2014 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.9.2.3 2014/08/20 00:02:47 tls Exp $"); 30 31 #include "opt_cputypes.h" 32 #include "opt_mvsoc.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pcireg.h> 41 #include <dev/marvell/marvellreg.h> 42 #include <dev/marvell/marvellvar.h> 43 44 #include <arm/marvell/mvsocreg.h> 45 #include <arm/marvell/mvsocvar.h> 46 #include <arm/marvell/orionreg.h> 47 #include <arm/marvell/kirkwoodreg.h> 48 #include <arm/marvell/mv78xx0reg.h> 49 #include <arm/marvell/armadaxpreg.h> 50 51 #include <uvm/uvm.h> 52 53 #include "locators.h" 54 55 #ifdef MVSOC_CONSOLE_EARLY 56 #include <dev/ic/ns16550reg.h> 57 #include <dev/ic/comreg.h> 58 #include <dev/cons.h> 59 #endif 60 61 static int mvsoc_match(device_t, struct cfdata *, void *); 62 static void mvsoc_attach(device_t, device_t, void *); 63 64 static int mvsoc_print(void *, const char *); 65 static int mvsoc_search(device_t, cfdata_t, const int *, void *); 66 67 static int mvsoc_target_ddr(uint32_t, uint32_t *, uint32_t *); 68 static int mvsoc_target_ddr3(uint32_t, uint32_t *, uint32_t *); 69 static int mvsoc_target_peripheral(uint32_t, uint32_t, uint32_t *, uint32_t *); 70 71 uint32_t mvPclk, mvSysclk, mvTclk = 0; 72 int nwindow = 0, nremap = 0; 73 static vaddr_t regbase = 0xffffffff, dsc_base, pex_base; 74 vaddr_t mlmb_base; 75 76 void (*mvsoc_intr_init)(void); 77 int (*mvsoc_clkgating)(struct marvell_attach_args *); 78 79 80 #ifdef MVSOC_CONSOLE_EARLY 81 static vaddr_t com_base; 82 83 static inline uint32_t 84 uart_read(bus_size_t o) 85 { 86 return *(volatile uint32_t *)(com_base + (o << 2)); 87 } 88 89 static inline void 90 uart_write(bus_size_t o, uint32_t v) 91 { 92 *(volatile uint32_t *)(com_base + (o << 2)) = v; 93 } 94 95 static int 96 mvsoc_cngetc(dev_t dv) 97 { 98 if ((uart_read(com_lsr) & LSR_RXRDY) == 0) 99 return -1; 100 101 return uart_read(com_data) & 0xff; 102 } 103 104 static void 105 mvsoc_cnputc(dev_t dv, int c) 106 { 107 int timo = 150000; 108 109 while ((uart_read(com_lsr) & LSR_TXRDY) == 0 && --timo > 0) 110 ; 111 112 uart_write(com_data, c); 113 114 timo = 150000; 115 while ((uart_read(com_lsr) & LSR_TSRE) == 0 && --timo > 0) 116 ; 117 } 118 119 static struct consdev mvsoc_earlycons = { 120 .cn_putc = mvsoc_cnputc, 121 .cn_getc = mvsoc_cngetc, 122 .cn_pollc = nullcnpollc, 123 }; 124 #endif 125 126 127 /* attributes */ 128 static struct { 129 int tag; 130 uint32_t attr; 131 uint32_t target; 132 } mvsoc_tags[] = { 133 { MARVELL_TAG_SDRAM_CS0, 134 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 135 { MARVELL_TAG_SDRAM_CS1, 136 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 137 { MARVELL_TAG_SDRAM_CS2, 138 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 139 { MARVELL_TAG_SDRAM_CS3, 140 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 141 142 { MARVELL_TAG_DDR3_CS0, 143 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR }, 144 { MARVELL_TAG_DDR3_CS1, 145 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR }, 146 { MARVELL_TAG_DDR3_CS2, 147 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR }, 148 { MARVELL_TAG_DDR3_CS3, 149 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR }, 150 151 #if defined(ORION) 152 { ORION_TAG_DEVICE_CS0, 153 ORION_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 154 { ORION_TAG_DEVICE_CS1, 155 ORION_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 156 { ORION_TAG_DEVICE_CS2, 157 ORION_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 158 { ORION_TAG_DEVICE_BOOTCS, 159 ORION_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 160 { ORION_TAG_FLASH_CS, 161 ORION_ATTR_FLASH_CS, MVSOC_UNITID_DEVBUS }, 162 { ORION_TAG_PEX0_MEM, 163 ORION_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 164 { ORION_TAG_PEX0_IO, 165 ORION_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 166 { ORION_TAG_PEX1_MEM, 167 ORION_ATTR_PEX_MEM, ORION_UNITID_PEX1 }, 168 { ORION_TAG_PEX1_IO, 169 ORION_ATTR_PEX_IO, ORION_UNITID_PEX1 }, 170 { ORION_TAG_PCI_MEM, 171 ORION_ATTR_PCI_MEM, ORION_UNITID_PCI }, 172 { ORION_TAG_PCI_IO, 173 ORION_ATTR_PCI_IO, ORION_UNITID_PCI }, 174 { ORION_TAG_CRYPT, 175 ORION_ATTR_CRYPT, ORION_UNITID_CRYPT }, 176 #endif 177 178 #if defined(KIRKWOOD) 179 { KIRKWOOD_TAG_NAND, 180 KIRKWOOD_ATTR_NAND, MVSOC_UNITID_DEVBUS }, 181 { KIRKWOOD_TAG_SPI, 182 KIRKWOOD_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 183 { KIRKWOOD_TAG_BOOTROM, 184 KIRKWOOD_ATTR_BOOTROM, MVSOC_UNITID_DEVBUS }, 185 { KIRKWOOD_TAG_PEX_MEM, 186 KIRKWOOD_ATTR_PEX_MEM, MVSOC_UNITID_PEX }, 187 { KIRKWOOD_TAG_PEX_IO, 188 KIRKWOOD_ATTR_PEX_IO, MVSOC_UNITID_PEX }, 189 { KIRKWOOD_TAG_PEX1_MEM, 190 KIRKWOOD_ATTR_PEX1_MEM, MVSOC_UNITID_PEX }, 191 { KIRKWOOD_TAG_PEX1_IO, 192 KIRKWOOD_ATTR_PEX1_IO, MVSOC_UNITID_PEX }, 193 { KIRKWOOD_TAG_CRYPT, 194 KIRKWOOD_ATTR_CRYPT, KIRKWOOD_UNITID_CRYPT }, 195 #endif 196 197 #if defined(MV78XX0) 198 { MV78XX0_TAG_DEVICE_CS0, 199 MV78XX0_ATTR_DEVICE_CS0, MVSOC_UNITID_DEVBUS }, 200 { MV78XX0_TAG_DEVICE_CS1, 201 MV78XX0_ATTR_DEVICE_CS1, MVSOC_UNITID_DEVBUS }, 202 { MV78XX0_TAG_DEVICE_CS2, 203 MV78XX0_ATTR_DEVICE_CS2, MVSOC_UNITID_DEVBUS }, 204 { MV78XX0_TAG_DEVICE_CS3, 205 MV78XX0_ATTR_DEVICE_CS3, MVSOC_UNITID_DEVBUS }, 206 { MV78XX0_TAG_DEVICE_BOOTCS, 207 MV78XX0_ATTR_BOOT_CS, MVSOC_UNITID_DEVBUS }, 208 { MV78XX0_TAG_SPI, 209 MV78XX0_ATTR_SPI, MVSOC_UNITID_DEVBUS }, 210 { MV78XX0_TAG_PEX0_MEM, 211 MV78XX0_ATTR_PEX_0_MEM, MVSOC_UNITID_PEX }, 212 { MV78XX0_TAG_PEX01_MEM, 213 MV78XX0_ATTR_PEX_1_MEM, MVSOC_UNITID_PEX }, 214 { MV78XX0_TAG_PEX02_MEM, 215 MV78XX0_ATTR_PEX_2_MEM, MVSOC_UNITID_PEX }, 216 { MV78XX0_TAG_PEX03_MEM, 217 MV78XX0_ATTR_PEX_3_MEM, MVSOC_UNITID_PEX }, 218 { MV78XX0_TAG_PEX0_IO, 219 MV78XX0_ATTR_PEX_0_IO, MVSOC_UNITID_PEX }, 220 { MV78XX0_TAG_PEX01_IO, 221 MV78XX0_ATTR_PEX_1_IO, MVSOC_UNITID_PEX }, 222 { MV78XX0_TAG_PEX02_IO, 223 MV78XX0_ATTR_PEX_2_IO, MVSOC_UNITID_PEX }, 224 { MV78XX0_TAG_PEX03_IO, 225 MV78XX0_ATTR_PEX_3_IO, MVSOC_UNITID_PEX }, 226 { MV78XX0_TAG_PEX1_MEM, 227 MV78XX0_ATTR_PEX_0_MEM, MV78XX0_UNITID_PEX1 }, 228 { MV78XX0_TAG_PEX11_MEM, 229 MV78XX0_ATTR_PEX_1_MEM, MV78XX0_UNITID_PEX1 }, 230 { MV78XX0_TAG_PEX12_MEM, 231 MV78XX0_ATTR_PEX_2_MEM, MV78XX0_UNITID_PEX1 }, 232 { MV78XX0_TAG_PEX13_MEM, 233 MV78XX0_ATTR_PEX_3_MEM, MV78XX0_UNITID_PEX1 }, 234 { MV78XX0_TAG_PEX1_IO, 235 MV78XX0_ATTR_PEX_0_IO, MV78XX0_UNITID_PEX1 }, 236 { MV78XX0_TAG_PEX11_IO, 237 MV78XX0_ATTR_PEX_1_IO, MV78XX0_UNITID_PEX1 }, 238 { MV78XX0_TAG_PEX12_IO, 239 MV78XX0_ATTR_PEX_2_IO, MV78XX0_UNITID_PEX1 }, 240 { MV78XX0_TAG_PEX13_IO, 241 MV78XX0_ATTR_PEX_3_IO, MV78XX0_UNITID_PEX1 }, 242 { MV78XX0_TAG_CRYPT, 243 MV78XX0_ATTR_CRYPT, MV78XX0_UNITID_CRYPT }, 244 #endif 245 246 #if defined(ARMADAXP) 247 { ARMADAXP_TAG_PEX00_MEM, 248 ARMADAXP_ATTR_PEXx0_MEM, ARMADAXP_UNITID_PEX0 }, 249 { ARMADAXP_TAG_PEX00_IO, 250 ARMADAXP_ATTR_PEXx0_IO, ARMADAXP_UNITID_PEX0 }, 251 { ARMADAXP_TAG_PEX01_MEM, 252 ARMADAXP_ATTR_PEXx1_MEM, ARMADAXP_UNITID_PEX0 }, 253 { ARMADAXP_TAG_PEX01_IO, 254 ARMADAXP_ATTR_PEXx1_IO, ARMADAXP_UNITID_PEX0 }, 255 { ARMADAXP_TAG_PEX02_MEM, 256 ARMADAXP_ATTR_PEXx2_MEM, ARMADAXP_UNITID_PEX0 }, 257 { ARMADAXP_TAG_PEX02_IO, 258 ARMADAXP_ATTR_PEXx2_IO, ARMADAXP_UNITID_PEX0 }, 259 { ARMADAXP_TAG_PEX03_MEM, 260 ARMADAXP_ATTR_PEXx3_MEM, ARMADAXP_UNITID_PEX0 }, 261 { ARMADAXP_TAG_PEX03_IO, 262 ARMADAXP_ATTR_PEXx3_IO, ARMADAXP_UNITID_PEX0 }, 263 { ARMADAXP_TAG_PEX2_MEM, 264 ARMADAXP_ATTR_PEX2_MEM, ARMADAXP_UNITID_PEX2 }, 265 { ARMADAXP_TAG_PEX2_IO, 266 ARMADAXP_ATTR_PEX2_IO, ARMADAXP_UNITID_PEX2 }, 267 { ARMADAXP_TAG_PEX3_MEM, 268 ARMADAXP_ATTR_PEX3_MEM, ARMADAXP_UNITID_PEX3 }, 269 { ARMADAXP_TAG_PEX3_IO, 270 ARMADAXP_ATTR_PEX3_IO, ARMADAXP_UNITID_PEX3 }, 271 #endif 272 }; 273 274 #if defined(ORION) 275 #define ORION_1(m) MARVELL_ORION_1_ ## m 276 #define ORION_2(m) MARVELL_ORION_2_ ## m 277 #endif 278 #if defined(KIRKWOOD) 279 #undef KIRKWOOD 280 #define KIRKWOOD(m) MARVELL_KIRKWOOD_ ## m 281 #endif 282 #if defined(MV78XX0) 283 #undef MV78XX0 284 #define MV78XX0(m) MARVELL_MV78XX0_ ## m 285 #endif 286 #if defined(ARMADAXP) 287 #undef ARMADAXP 288 #define ARMADAXP(m) MARVELL_ARMADAXP_ ## m 289 #define ARMADA370(m) MARVELL_ARMADA370_ ## m 290 #endif 291 static struct { 292 uint16_t model; 293 uint8_t rev; 294 const char *modelstr; 295 const char *revstr; 296 const char *typestr; 297 } nametbl[] = { 298 #if defined(ORION) 299 { ORION_1(88F1181), 0, "MV88F1181", NULL, "Orion1" }, 300 { ORION_1(88F5082), 2, "MV88F5082", "A2", "Orion1" }, 301 { ORION_1(88F5180N), 3, "MV88F5180N","B1", "Orion1" }, 302 { ORION_1(88F5181), 0, "MV88F5181", "A0", "Orion1" }, 303 { ORION_1(88F5181), 1, "MV88F5181", "A1", "Orion1" }, 304 { ORION_1(88F5181), 2, "MV88F5181", "B0", "Orion1" }, 305 { ORION_1(88F5181), 3, "MV88F5181", "B1", "Orion1" }, 306 { ORION_1(88F5181), 8, "MV88F5181L","A0", "Orion1" }, 307 { ORION_1(88F5181), 9, "MV88F5181L","A1", "Orion1" }, 308 { ORION_1(88F5182), 0, "MV88F5182", "A0", "Orion1" }, 309 { ORION_1(88F5182), 1, "MV88F5182", "A1", "Orion1" }, 310 { ORION_1(88F5182), 2, "MV88F5182", "A2", "Orion1" }, 311 { ORION_1(88F6082), 0, "MV88F6082", "A0", "Orion1" }, 312 { ORION_1(88F6082), 1, "MV88F6082", "A1", "Orion1" }, 313 { ORION_1(88F6183), 0, "MV88F6183", "A0", "Orion1" }, 314 { ORION_1(88F6183), 1, "MV88F6183", "Z0", "Orion1" }, 315 { ORION_1(88W8660), 0, "MV88W8660", "A0", "Orion1" }, 316 { ORION_1(88W8660), 1, "MV88W8660", "A1", "Orion1" }, 317 318 { ORION_2(88F1281), 0, "MV88F1281", "A0", "Orion2" }, 319 { ORION_2(88F5281), 0, "MV88F5281", "A0", "Orion2" }, 320 { ORION_2(88F5281), 1, "MV88F5281", "B0", "Orion2" }, 321 { ORION_2(88F5281), 2, "MV88F5281", "C0", "Orion2" }, 322 { ORION_2(88F5281), 3, "MV88F5281", "C1", "Orion2" }, 323 { ORION_2(88F5281), 4, "MV88F5281", "D0", "Orion2" }, 324 #endif 325 326 #if defined(KIRKWOOD) 327 { KIRKWOOD(88F6180), 2, "88F6180", "A0", "Kirkwood" }, 328 { KIRKWOOD(88F6180), 3, "88F6180", "A1", "Kirkwood" }, 329 { KIRKWOOD(88F6192), 0, "88F619x", "Z0", "Kirkwood" }, 330 { KIRKWOOD(88F6192), 2, "88F619x", "A0", "Kirkwood" }, 331 { KIRKWOOD(88F6192), 3, "88F619x", "A1", "Kirkwood" }, 332 { KIRKWOOD(88F6281), 0, "88F6281", "Z0", "Kirkwood" }, 333 { KIRKWOOD(88F6281), 2, "88F6281", "A0", "Kirkwood" }, 334 { KIRKWOOD(88F6281), 3, "88F6281", "A1", "Kirkwood" }, 335 { KIRKWOOD(88F6282), 0, "88F6282", "A0", "Kirkwood" }, 336 { KIRKWOOD(88F6282), 1, "88F6282", "A1", "Kirkwood" }, 337 #endif 338 339 #if defined(MV78XX0) 340 { MV78XX0(MV78100), 1, "MV78100", "A0", "Discovery Innovation" }, 341 { MV78XX0(MV78100), 2, "MV78100", "A1", "Discovery Innovation" }, 342 { MV78XX0(MV78200), 1, "MV78200", "A0", "Discovery Innovation" }, 343 #endif 344 345 #if defined(ARMADAXP) 346 { ARMADAXP(MV78130), 1, "MV78130", "A0", "Armada XP" }, 347 { ARMADAXP(MV78160), 1, "MV78160", "A0", "Armada XP" }, 348 { ARMADAXP(MV78230), 1, "MV78260", "A0", "Armada XP" }, 349 { ARMADAXP(MV78260), 1, "MV78260", "A0", "Armada XP" }, 350 { ARMADAXP(MV78460), 1, "MV78460", "A0", "Armada XP" }, 351 { ARMADAXP(MV78460), 2, "MV78460", "B0", "Armada XP" }, 352 353 { ARMADA370(MV6707), 0, "MV6707", "A0", "Armada 370" }, 354 { ARMADA370(MV6707), 1, "MV6707", "A1", "Armada 370" }, 355 { ARMADA370(MV6710), 0, "MV6710", "A0", "Armada 370" }, 356 { ARMADA370(MV6710), 1, "MV6710", "A1", "Armada 370" }, 357 { ARMADA370(MV6W11), 0, "MV6W11", "A0", "Armada 370" }, 358 { ARMADA370(MV6W11), 1, "MV6W11", "A1", "Armada 370" }, 359 #endif 360 }; 361 362 enum marvell_tags ddr_tags[] = { 363 MARVELL_TAG_SDRAM_CS0, 364 MARVELL_TAG_SDRAM_CS1, 365 MARVELL_TAG_SDRAM_CS2, 366 MARVELL_TAG_SDRAM_CS3, 367 368 MARVELL_TAG_UNDEFINED 369 }; 370 enum marvell_tags ddr3_tags[] = { 371 MARVELL_TAG_DDR3_CS0, 372 MARVELL_TAG_DDR3_CS1, 373 MARVELL_TAG_DDR3_CS2, 374 MARVELL_TAG_DDR3_CS3, 375 376 MARVELL_TAG_UNDEFINED 377 }; 378 static struct { 379 uint16_t model; 380 uint8_t rev; 381 enum marvell_tags *tags; 382 } tagstbl[] = { 383 #if defined(ORION) 384 { ORION_1(88F1181), 0, ddr_tags }, 385 { ORION_1(88F5082), 2, ddr_tags }, 386 { ORION_1(88F5180N), 3, ddr_tags }, 387 { ORION_1(88F5181), 0, ddr_tags }, 388 { ORION_1(88F5181), 1, ddr_tags }, 389 { ORION_1(88F5181), 2, ddr_tags }, 390 { ORION_1(88F5181), 3, ddr_tags }, 391 { ORION_1(88F5181), 8, ddr_tags }, 392 { ORION_1(88F5181), 9, ddr_tags }, 393 { ORION_1(88F5182), 0, ddr_tags }, 394 { ORION_1(88F5182), 1, ddr_tags }, 395 { ORION_1(88F5182), 2, ddr_tags }, 396 { ORION_1(88F6082), 0, ddr_tags }, 397 { ORION_1(88F6082), 1, ddr_tags }, 398 { ORION_1(88F6183), 0, ddr_tags }, 399 { ORION_1(88F6183), 1, ddr_tags }, 400 { ORION_1(88W8660), 0, ddr_tags }, 401 { ORION_1(88W8660), 1, ddr_tags }, 402 403 { ORION_2(88F1281), 0, ddr_tags }, 404 { ORION_2(88F5281), 0, ddr_tags }, 405 { ORION_2(88F5281), 1, ddr_tags }, 406 { ORION_2(88F5281), 2, ddr_tags }, 407 { ORION_2(88F5281), 3, ddr_tags }, 408 { ORION_2(88F5281), 4, ddr_tags }, 409 #endif 410 411 #if defined(KIRKWOOD) 412 { KIRKWOOD(88F6180), 2, ddr_tags }, 413 { KIRKWOOD(88F6180), 3, ddr_tags }, 414 { KIRKWOOD(88F6192), 0, ddr_tags }, 415 { KIRKWOOD(88F6192), 2, ddr_tags }, 416 { KIRKWOOD(88F6192), 3, ddr_tags }, 417 { KIRKWOOD(88F6281), 0, ddr_tags }, 418 { KIRKWOOD(88F6281), 2, ddr_tags }, 419 { KIRKWOOD(88F6281), 3, ddr_tags }, 420 { KIRKWOOD(88F6282), 0, ddr_tags }, 421 { KIRKWOOD(88F6282), 1, ddr_tags }, 422 #endif 423 424 #if defined(MV78XX0) 425 { MV78XX0(MV78100), 1, ddr_tags }, 426 { MV78XX0(MV78100), 2, ddr_tags }, 427 { MV78XX0(MV78200), 1, ddr_tags }, 428 #endif 429 430 #if defined(ARMADAXP) 431 { ARMADAXP(MV78130), 1, ddr3_tags }, 432 { ARMADAXP(MV78160), 1, ddr3_tags }, 433 { ARMADAXP(MV78230), 1, ddr3_tags }, 434 { ARMADAXP(MV78260), 1, ddr3_tags }, 435 { ARMADAXP(MV78460), 1, ddr3_tags }, 436 { ARMADAXP(MV78460), 2, ddr3_tags }, 437 438 { ARMADA370(MV6707), 0, ddr3_tags }, 439 { ARMADA370(MV6707), 1, ddr3_tags }, 440 { ARMADA370(MV6710), 0, ddr3_tags }, 441 { ARMADA370(MV6710), 1, ddr3_tags }, 442 { ARMADA370(MV6W11), 0, ddr3_tags }, 443 { ARMADA370(MV6W11), 1, ddr3_tags }, 444 #endif 445 }; 446 447 448 #define OFFSET_DEFAULT MVA_OFFSET_DEFAULT 449 #define IRQ_DEFAULT MVA_IRQ_DEFAULT 450 static const struct mvsoc_periph { 451 int model; 452 const char *name; 453 int unit; 454 bus_size_t offset; 455 int irq; 456 } mvsoc_periphs[] = { 457 #if defined(ORION) 458 #define ORION_IRQ_TMR (32 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 459 460 { ORION_1(88F1181), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 461 { ORION_1(88F1181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 462 { ORION_1(88F1181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 463 { ORION_1(88F1181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 464 { ORION_1(88F1181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 465 { ORION_1(88F1181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 466 { ORION_1(88F1181), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 467 468 { ORION_1(88F5082), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 469 { ORION_1(88F5082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 470 { ORION_1(88F5082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 471 { ORION_1(88F5082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 472 { ORION_1(88F5082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 473 { ORION_1(88F5082), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 474 { ORION_1(88F5082), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 475 { ORION_1(88F5082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 476 { ORION_1(88F5082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 477 { ORION_1(88F5082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 478 { ORION_1(88F5082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 479 { ORION_1(88F5082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 480 481 { ORION_1(88F5180N),"mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 482 { ORION_1(88F5180N),"mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 483 { ORION_1(88F5180N),"com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 484 { ORION_1(88F5180N),"com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 485 { ORION_1(88F5180N),"ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 486 { ORION_1(88F5180N),"gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 487 { ORION_1(88F5180N),"gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 488 { ORION_1(88F5180N),"gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 489 { ORION_1(88F5180N),"mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 490 { ORION_1(88F5180N),"mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 491 492 { ORION_1(88F5181), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 493 { ORION_1(88F5181), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 494 { ORION_1(88F5181), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 495 { ORION_1(88F5181), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 496 { ORION_1(88F5181), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 497 { ORION_1(88F5181), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 498 { ORION_1(88F5181), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 499 { ORION_1(88F5181), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 500 { ORION_1(88F5181), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 501 { ORION_1(88F5181), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 502 { ORION_1(88F5181), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 503 504 { ORION_1(88F5182), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 505 { ORION_1(88F5182), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 506 { ORION_1(88F5182), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 507 { ORION_1(88F5182), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 508 { ORION_1(88F5182), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 509 { ORION_1(88F5182), "ehci", 1, ORION_USB1_BASE, ORION_IRQ_USBCNT1 }, 510 { ORION_1(88F5182), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 511 { ORION_1(88F5182), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 512 { ORION_1(88F5182), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 513 { ORION_1(88F5182), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 514 { ORION_1(88F5182), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 515 { ORION_1(88F5182), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 516 517 { ORION_1(88F6082), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 518 { ORION_1(88F6082), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 519 { ORION_1(88F6082), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 520 { ORION_1(88F6082), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 521 { ORION_1(88F6082), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 522 { ORION_1(88F6082), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 523 { ORION_1(88F6082), "mvcesa", 0, ORION_CESA_BASE, ORION_IRQ_SECURITYINTR}, 524 { ORION_1(88F6082), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 525 { ORION_1(88F6082), "mvsata", 0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR }, 526 { ORION_1(88F6082), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 527 528 { ORION_1(88F6183), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 529 { ORION_1(88F6183), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 530 { ORION_1(88F6183), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 531 { ORION_1(88F6183), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 532 533 { ORION_1(88W8660), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 534 { ORION_1(88W8660), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 535 { ORION_1(88W8660), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 536 { ORION_1(88W8660), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 537 { ORION_1(88W8660), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 538 { ORION_1(88W8660), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 539 { ORION_1(88W8660), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 540 { ORION_1(88W8660), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 541 { ORION_1(88W8660), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 542 { ORION_1(88W8660), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 543 544 { ORION_2(88F1281), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 545 { ORION_2(88F1281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 546 { ORION_2(88F1281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 547 { ORION_2(88F1281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 548 { ORION_2(88F1281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 549 { ORION_2(88F1281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 550 { ORION_2(88F1281), "mvpex", 1, ORION_PEX1_BASE, ORION_IRQ_PEX1INT }, 551 552 { ORION_2(88F5281), "mvsoctmr",0, MVSOC_TMR_BASE, ORION_IRQ_TMR }, 553 { ORION_2(88F5281), "mvsocgpp",0, MVSOC_GPP_BASE, ORION_IRQ_GPIO7_0 }, 554 { ORION_2(88F5281), "com", 0, MVSOC_COM0_BASE, ORION_IRQ_UART0 }, 555 { ORION_2(88F5281), "com", 1, MVSOC_COM1_BASE, ORION_IRQ_UART1 }, 556 { ORION_2(88F5281), "ehci", 0, ORION_USB0_BASE, ORION_IRQ_USBCNT0 }, 557 { ORION_2(88F5281), "gtidmac", 0, ORION_IDMAC_BASE, IRQ_DEFAULT }, 558 { ORION_2(88F5281), "gtpci", 0, ORION_PCI_BASE, ORION_IRQ_PEX0INT }, 559 { ORION_2(88F5281), "gttwsi", 0, MVSOC_TWSI_BASE, ORION_IRQ_TWSI }, 560 { ORION_2(88F5281), "mvgbec", 0, ORION_GBE_BASE, IRQ_DEFAULT }, 561 { ORION_2(88F5281), "mvpex", 0, MVSOC_PEX_BASE, ORION_IRQ_PEX0INT }, 562 #endif 563 564 #if defined(KIRKWOOD) 565 #define KIRKWOOD_IRQ_TMR (64 + MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ) 566 567 { KIRKWOOD(88F6180),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 568 { KIRKWOOD(88F6180),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 569 { KIRKWOOD(88F6180),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 570 { KIRKWOOD(88F6180),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 571 { KIRKWOOD(88F6180),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 572 { KIRKWOOD(88F6180),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 573 { KIRKWOOD(88F6180),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 574 { KIRKWOOD(88F6180),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 575 { KIRKWOOD(88F6180),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 576 { KIRKWOOD(88F6180),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 577 { KIRKWOOD(88F6180),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 578 { KIRKWOOD(88F6180),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 579 580 { KIRKWOOD(88F6192),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 581 { KIRKWOOD(88F6192),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 582 { KIRKWOOD(88F6192),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 583 { KIRKWOOD(88F6192),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 584 { KIRKWOOD(88F6192),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 585 { KIRKWOOD(88F6192),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 586 { KIRKWOOD(88F6192),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 587 { KIRKWOOD(88F6192),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 588 { KIRKWOOD(88F6192),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 589 { KIRKWOOD(88F6192),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 590 { KIRKWOOD(88F6192),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 591 { KIRKWOOD(88F6192),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 592 { KIRKWOOD(88F6192),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 593 { KIRKWOOD(88F6192),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 594 595 { KIRKWOOD(88F6281),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 596 { KIRKWOOD(88F6281),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 597 { KIRKWOOD(88F6281),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 598 { KIRKWOOD(88F6281),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 599 { KIRKWOOD(88F6281),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 600 { KIRKWOOD(88F6281),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 601 { KIRKWOOD(88F6281),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 602 { KIRKWOOD(88F6281),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 603 { KIRKWOOD(88F6281),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT }, 604 { KIRKWOOD(88F6281),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 605 { KIRKWOOD(88F6281),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 606 { KIRKWOOD(88F6281),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 607 { KIRKWOOD(88F6281),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 608 { KIRKWOOD(88F6281),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 609 610 { KIRKWOOD(88F6282),"mvsoctmr",0, MVSOC_TMR_BASE, KIRKWOOD_IRQ_TMR }, 611 { KIRKWOOD(88F6282),"mvsocgpp",0, MVSOC_GPP_BASE, KIRKWOOD_IRQ_GPIOLO7_0}, 612 { KIRKWOOD(88F6282),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT }, 613 { KIRKWOOD(88F6282),"mvsocts", 0, KIRKWOOD_TS_BASE, IRQ_DEFAULT }, 614 { KIRKWOOD(88F6282),"com", 0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT }, 615 { KIRKWOOD(88F6282),"com", 1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT }, 616 { KIRKWOOD(88F6282),"ehci", 0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT }, 617 { KIRKWOOD(88F6282),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,IRQ_DEFAULT }, 618 { KIRKWOOD(88F6282),"gttwsi", 0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI }, 619 { KIRKWOOD(88F6282),"gttwsi", 1, KIRKWOOD_TWSI1_BASE,KIRKWOOD_IRQ_TWSI1 }, 620 { KIRKWOOD(88F6282),"mvcesa", 0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT}, 621 { KIRKWOOD(88F6282),"mvgbec", 0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT }, 622 { KIRKWOOD(88F6282),"mvgbec", 1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT }, 623 { KIRKWOOD(88F6282),"mvpex", 0, MVSOC_PEX_BASE, KIRKWOOD_IRQ_PEX0INT }, 624 { KIRKWOOD(88F6282),"mvpex", 1, KIRKWOOD_PEX1_BASE,KIRKWOOD_IRQ_PEX1INT }, 625 { KIRKWOOD(88F6282),"mvsata", 0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA }, 626 { KIRKWOOD(88F6282),"mvsdio", 0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT }, 627 #endif 628 629 #if defined(MV78XX0) 630 { MV78XX0(MV78100), "mvsoctmr",0, MVSOC_TMR_BASE, MV78XX0_IRQ_TIMER0 }, 631 { MV78XX0(MV78100), "mvsocgpp",0, MVSOC_GPP_BASE, MV78XX0_IRQ_GPIO0_7 }, 632 { MV78XX0(MV78100), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0 }, 633 { MV78XX0(MV78100), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1 }, 634 { MV78XX0(MV78100), "com", 2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 }, 635 { MV78XX0(MV78100), "com", 3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 }, 636 { MV78XX0(MV78100), "gttwsi", 0, MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI0 }, 637 { MV78XX0(MV78100), "gttwsi", 1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 }, 638 { MV78XX0(MV78100), "mvgbec", 0, MV78XX0_GBE0_BASE,IRQ_DEFAULT }, 639 { MV78XX0(MV78100), "mvgbec", 1, MV78XX0_GBE1_BASE,IRQ_DEFAULT }, 640 { MV78XX0(MV78100), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA }, 641 642 { MV78XX0(MV78200), "mvsoctmr",0, MVSOC_TMR_BASE, MV78XX0_IRQ_TIMER0 }, 643 { MV78XX0(MV78200), "mvsocgpp",0, MVSOC_GPP_BASE, MV78XX0_IRQ_GPIO0_7 }, 644 { MV78XX0(MV78200), "com", 0, MVSOC_COM0_BASE, MV78XX0_IRQ_UART0 }, 645 { MV78XX0(MV78200), "com", 1, MVSOC_COM1_BASE, MV78XX0_IRQ_UART1 }, 646 { MV78XX0(MV78200), "com", 2, MV78XX0_COM2_BASE,MV78XX0_IRQ_UART2 }, 647 { MV78XX0(MV78200), "com", 3, MV78XX0_COM3_BASE,MV78XX0_IRQ_UART3 }, 648 { MV78XX0(MV78200), "gttwsi", 0, MVSOC_TWSI_BASE, MV78XX0_IRQ_TWSI0 }, 649 { MV78XX0(MV78200), "gttwsi", 1, MV78XX0_TWSI1_BASE,MV78XX0_IRQ_TWSI1 }, 650 { MV78XX0(MV78200), "mvgbec", 0, MV78XX0_GBE0_BASE,IRQ_DEFAULT }, 651 { MV78XX0(MV78200), "mvgbec", 1, MV78XX0_GBE1_BASE,IRQ_DEFAULT }, 652 { MV78XX0(MV78200), "mvgbec", 2, MV78XX0_GBE2_BASE,IRQ_DEFAULT }, 653 { MV78XX0(MV78200), "mvgbec", 3, MV78XX0_GBE3_BASE,IRQ_DEFAULT }, 654 { MV78XX0(MV78200), "mvsata", 0, MV78XX0_SATAHC_BASE,MV78XX0_IRQ_SATA }, 655 #endif 656 657 #if defined(ARMADAXP) 658 { ARMADAXP(MV78130), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 659 { ARMADAXP(MV78130), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 660 { ARMADAXP(MV78130), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 661 { ARMADAXP(MV78130), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 662 { ARMADAXP(MV78130), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 663 { ARMADAXP(MV78130), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 664 { ARMADAXP(MV78130), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 665 { ARMADAXP(MV78130), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 666 { ARMADAXP(MV78130), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 667 { ARMADAXP(MV78130), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 668 { ARMADAXP(MV78130), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 669 { ARMADAXP(MV78130), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 670 { ARMADAXP(MV78130), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 671 { ARMADAXP(MV78130), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 672 { ARMADAXP(MV78130), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 673 { ARMADAXP(MV78130), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 674 { ARMADAXP(MV78130), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 675 { ARMADAXP(MV78130), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 676 { ARMADAXP(MV78130), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 677 { ARMADAXP(MV78130), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 678 { ARMADAXP(MV78130), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 679 { ARMADAXP(MV78130), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 680 { ARMADAXP(MV78130), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 681 { ARMADAXP(MV78130), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 682 { ARMADAXP(MV78130), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 683 684 { ARMADAXP(MV78160), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 685 { ARMADAXP(MV78160), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 686 { ARMADAXP(MV78160), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 687 { ARMADAXP(MV78160), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 688 { ARMADAXP(MV78160), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 689 { ARMADAXP(MV78160), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 690 { ARMADAXP(MV78160), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 691 { ARMADAXP(MV78160), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 692 { ARMADAXP(MV78160), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 693 { ARMADAXP(MV78160), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 694 { ARMADAXP(MV78160), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 695 { ARMADAXP(MV78160), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 696 { ARMADAXP(MV78160), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 697 { ARMADAXP(MV78160), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 698 { ARMADAXP(MV78160), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 699 { ARMADAXP(MV78160), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 700 { ARMADAXP(MV78160), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 701 { ARMADAXP(MV78160), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 702 { ARMADAXP(MV78160), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 703 { ARMADAXP(MV78160), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 704 { ARMADAXP(MV78160), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 705 { ARMADAXP(MV78160), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 706 { ARMADAXP(MV78160), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 707 { ARMADAXP(MV78160), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 708 { ARMADAXP(MV78160), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 709 { ARMADAXP(MV78160), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 710 { ARMADAXP(MV78160), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 711 712 { ARMADAXP(MV78230), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 713 { ARMADAXP(MV78230), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 714 { ARMADAXP(MV78230), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 715 { ARMADAXP(MV78230), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 716 { ARMADAXP(MV78230), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 717 { ARMADAXP(MV78230), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 718 { ARMADAXP(MV78230), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 719 { ARMADAXP(MV78230), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 720 { ARMADAXP(MV78230), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 721 { ARMADAXP(MV78230), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 722 { ARMADAXP(MV78230), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 723 { ARMADAXP(MV78230), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 724 { ARMADAXP(MV78230), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 725 { ARMADAXP(MV78230), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 726 { ARMADAXP(MV78230), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 727 { ARMADAXP(MV78230), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 728 { ARMADAXP(MV78230), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 729 { ARMADAXP(MV78230), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 730 { ARMADAXP(MV78230), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 731 { ARMADAXP(MV78230), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 732 { ARMADAXP(MV78230), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 733 { ARMADAXP(MV78230), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 734 { ARMADAXP(MV78230), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 735 { ARMADAXP(MV78230), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 736 { ARMADAXP(MV78230), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 737 { ARMADAXP(MV78230), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 738 739 { ARMADAXP(MV78260), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 740 { ARMADAXP(MV78260), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 741 { ARMADAXP(MV78260), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 742 { ARMADAXP(MV78260), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 743 { ARMADAXP(MV78260), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 744 { ARMADAXP(MV78260), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 745 { ARMADAXP(MV78260), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 746 { ARMADAXP(MV78260), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 747 { ARMADAXP(MV78260), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 748 { ARMADAXP(MV78260), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 749 { ARMADAXP(MV78260), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 750 { ARMADAXP(MV78260), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 751 { ARMADAXP(MV78260), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 752 { ARMADAXP(MV78260), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 753 { ARMADAXP(MV78260), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 754 { ARMADAXP(MV78260), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 755 { ARMADAXP(MV78260), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 756 { ARMADAXP(MV78260), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 757 { ARMADAXP(MV78260), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 758 { ARMADAXP(MV78260), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 759 { ARMADAXP(MV78260), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 760 { ARMADAXP(MV78260), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 761 { ARMADAXP(MV78260), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 762 { ARMADAXP(MV78260), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 763 { ARMADAXP(MV78260), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 764 { ARMADAXP(MV78260), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 765 { ARMADAXP(MV78260), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 766 767 { ARMADAXP(MV78460), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 768 { ARMADAXP(MV78460), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 769 { ARMADAXP(MV78460), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 770 { ARMADAXP(MV78460), "com", 2, ARMADAXP_COM2_BASE,ARMADAXP_IRQ_UART2 }, 771 { ARMADAXP(MV78460), "com", 3, ARMADAXP_COM3_BASE,ARMADAXP_IRQ_UART3 }, 772 { ARMADAXP(MV78460), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 773 { ARMADAXP(MV78460), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 774 { ARMADAXP(MV78460), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 775 { ARMADAXP(MV78460), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 776 { ARMADAXP(MV78460), "gtidmac",1, ARMADAXP_XORE1_BASE,IRQ_DEFAULT }, 777 { ARMADAXP(MV78460), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 778 { ARMADAXP(MV78460), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 779 { ARMADAXP(MV78460), "ehci", 2, ARMADAXP_USB2_BASE,ARMADAXP_IRQ_USB2 }, 780 { ARMADAXP(MV78460), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 781 { ARMADAXP(MV78460), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 782 { ARMADAXP(MV78460), "mvpex", 2, ARMADAXP_PEX02_BASE,ARMADAXP_IRQ_PEX02 }, 783 { ARMADAXP(MV78460), "mvpex", 3, ARMADAXP_PEX03_BASE,ARMADAXP_IRQ_PEX03 }, 784 { ARMADAXP(MV78460), "mvpex", 4, ARMADAXP_PEX2_BASE,ARMADAXP_IRQ_PEX2 }, 785 { ARMADAXP(MV78460), "mvpex", 5, ARMADAXP_PEX3_BASE,ARMADAXP_IRQ_PEX3 }, 786 { ARMADAXP(MV78460), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 787 { ARMADAXP(MV78460), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 788 { ARMADAXP(MV78460), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 789 { ARMADAXP(MV78460), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 790 { ARMADAXP(MV78460), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 791 { ARMADAXP(MV78460), "mvgbec", 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT }, 792 { ARMADAXP(MV78460), "mvgbec", 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT }, 793 { ARMADAXP(MV78460), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 794 { ARMADAXP(MV78460), "mvcesa", 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 }, 795 796 { ARMADA370(MV6710), "mvsoctmr",0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 }, 797 { ARMADA370(MV6710), "com", 0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 }, 798 { ARMADA370(MV6710), "com", 1, MVSOC_COM1_BASE, ARMADAXP_IRQ_UART1 }, 799 { ARMADA370(MV6710), "mvsocrtc",0,ARMADAXP_RTC_BASE,ARMADAXP_IRQ_RTC }, 800 { ARMADA370(MV6710), "gttwsi", 0, MVSOC_TWSI_BASE, ARMADAXP_IRQ_TWSI0 }, 801 { ARMADA370(MV6710), "gttwsi", 1, ARMADAXP_TWSI1_BASE,ARMADAXP_IRQ_TWSI1 }, 802 { ARMADA370(MV6710), "gtidmac",0, ARMADAXP_XORE0_BASE,IRQ_DEFAULT }, 803 { ARMADA370(MV6710), "ehci", 0, ARMADAXP_USB0_BASE,ARMADAXP_IRQ_USB0 }, 804 { ARMADA370(MV6710), "ehci", 1, ARMADAXP_USB1_BASE,ARMADAXP_IRQ_USB1 }, 805 { ARMADA370(MV6710), "mvpex", 0, MVSOC_PEX_BASE, ARMADAXP_IRQ_PEX00 }, 806 { ARMADA370(MV6710), "mvpex", 1, ARMADAXP_PEX01_BASE,ARMADAXP_IRQ_PEX01 }, 807 { ARMADA370(MV6710), "mvsata", 0, ARMADAXP_SATAHC_BASE,ARMADAXP_IRQ_SATA0 }, 808 { ARMADA370(MV6710), "mvspi", 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 809 { ARMADA370(MV6710), "mvspi", 1, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI }, 810 { ARMADA370(MV6710), "mvsdio", 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO }, 811 { ARMADA370(MV6710), "mvgbec", 0, ARMADAXP_GBE0_BASE,IRQ_DEFAULT }, 812 { ARMADA370(MV6710), "mvgbec", 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT }, 813 { ARMADA370(MV6710), "mvcesa", 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 }, 814 #endif 815 }; 816 817 818 CFATTACH_DECL_NEW(mvsoc, sizeof(struct mvsoc_softc), 819 mvsoc_match, mvsoc_attach, NULL, NULL); 820 821 /* ARGSUSED */ 822 static int 823 mvsoc_match(device_t parent, struct cfdata *match, void *aux) 824 { 825 826 return 1; 827 } 828 829 /* ARGSUSED */ 830 static void 831 mvsoc_attach(device_t parent, device_t self, void *aux) 832 { 833 struct mvsoc_softc *sc = device_private(self); 834 struct marvell_attach_args mva; 835 enum marvell_tags *tags; 836 uint16_t model; 837 uint8_t rev; 838 int i; 839 840 sc->sc_dev = self; 841 sc->sc_iot = &mvsoc_bs_tag; 842 sc->sc_addr = vtophys(regbase); 843 sc->sc_dmat = &mvsoc_bus_dma_tag; 844 if (bus_space_map(sc->sc_iot, sc->sc_addr, 0x100000, 0, &sc->sc_ioh) != 845 0) { 846 aprint_error_dev(self, "can't map registers\n"); 847 return; 848 } 849 850 model = mvsoc_model(); 851 rev = mvsoc_rev(); 852 for (i = 0; i < __arraycount(nametbl); i++) 853 if (nametbl[i].model == model && nametbl[i].rev == rev) 854 break; 855 if (i >= __arraycount(nametbl)) 856 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 857 858 aprint_normal(": Marvell %s %s%s %s\n", 859 nametbl[i].modelstr, 860 nametbl[i].revstr != NULL ? "Rev. " : "", 861 nametbl[i].revstr != NULL ? nametbl[i].revstr : "", 862 nametbl[i].typestr); 863 aprint_normal("%s: CPU Clock %d.%03d MHz" 864 " SysClock %d.%03d MHz TClock %d.%03d MHz\n", 865 device_xname(self), 866 mvPclk / 1000000, (mvPclk / 1000) % 1000, 867 mvSysclk / 1000000, (mvSysclk / 1000) % 1000, 868 mvTclk / 1000000, (mvTclk / 1000) % 1000); 869 aprint_naive("\n"); 870 871 mvsoc_intr_init(); 872 873 for (i = 0; i < __arraycount(tagstbl); i++) 874 if (tagstbl[i].model == model && tagstbl[i].rev == rev) 875 break; 876 if (i >= __arraycount(tagstbl)) 877 panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev); 878 tags = tagstbl[i].tags; 879 880 for (i = 0; i < __arraycount(mvsoc_periphs); i++) { 881 if (mvsoc_periphs[i].model != model) 882 continue; 883 884 mva.mva_name = mvsoc_periphs[i].name; 885 mva.mva_model = model; 886 mva.mva_revision = rev; 887 mva.mva_iot = sc->sc_iot; 888 mva.mva_ioh = sc->sc_ioh; 889 mva.mva_unit = mvsoc_periphs[i].unit; 890 mva.mva_addr = sc->sc_addr; 891 mva.mva_offset = mvsoc_periphs[i].offset; 892 mva.mva_size = 0; 893 mva.mva_dmat = sc->sc_dmat; 894 mva.mva_irq = mvsoc_periphs[i].irq; 895 mva.mva_tags = tags; 896 897 /* Skip clock disabled devices */ 898 if (mvsoc_clkgating != NULL && mvsoc_clkgating(&mva)) { 899 aprint_normal_dev(self, "%s%d clock disabled\n", 900 mvsoc_periphs[i].name, mvsoc_periphs[i].unit); 901 continue; 902 } 903 904 config_found_sm_loc(sc->sc_dev, "mvsoc", NULL, &mva, 905 mvsoc_print, mvsoc_search); 906 } 907 } 908 909 static int 910 mvsoc_print(void *aux, const char *pnp) 911 { 912 struct marvell_attach_args *mva = aux; 913 914 if (pnp) 915 aprint_normal("%s at %s unit %d", 916 mva->mva_name, pnp, mva->mva_unit); 917 else { 918 if (mva->mva_unit != MVA_UNIT_DEFAULT) 919 aprint_normal(" unit %d", mva->mva_unit); 920 if (mva->mva_offset != MVA_OFFSET_DEFAULT) { 921 aprint_normal(" offset 0x%04lx", mva->mva_offset); 922 if (mva->mva_size > 0) 923 aprint_normal("-0x%04lx", 924 mva->mva_offset + mva->mva_size - 1); 925 } 926 if (mva->mva_irq != MVA_IRQ_DEFAULT) 927 aprint_normal(" irq %d", mva->mva_irq); 928 } 929 930 return UNCONF; 931 } 932 933 /* ARGSUSED */ 934 static int 935 mvsoc_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 936 { 937 938 return config_match(parent, cf, aux); 939 } 940 941 /* ARGSUSED */ 942 int 943 marvell_winparams_by_tag(device_t dev, int tag, int *target, int *attribute, 944 uint64_t *base, uint32_t *size) 945 { 946 uint32_t base32; 947 int rv; 948 949 rv = mvsoc_target(tag, target, attribute, &base32, size); 950 *base = base32; 951 if (rv == -1) 952 return -1; 953 return 0; 954 } 955 956 957 /* 958 * These functions is called before bus_space is initialized. 959 */ 960 961 void 962 mvsoc_bootstrap(bus_addr_t iobase) 963 { 964 965 regbase = iobase; 966 dsc_base = iobase + MVSOC_DSC_BASE; 967 mlmb_base = iobase + MVSOC_MLMB_BASE; 968 pex_base = iobase + MVSOC_PEX_BASE; 969 #ifdef MVSOC_CONSOLE_EARLY 970 com_base = iobase + MVSOC_COM0_BASE; 971 cn_tab = &mvsoc_earlycons; 972 printf("Hello\n"); 973 #endif 974 } 975 976 /* 977 * We can read register of PCI configurations from (MVSOC_PEX_BASE + 0). 978 */ 979 uint16_t 980 mvsoc_model(void) 981 { 982 /* 983 * We read product-id from vendor/device register of PCI-Express. 984 */ 985 uint32_t reg; 986 uint16_t model; 987 988 KASSERT(regbase != 0xffffffff); 989 990 reg = *(volatile uint32_t *)(pex_base + PCI_ID_REG); 991 model = PCI_PRODUCT(reg); 992 993 #if defined(ORION) 994 if (model == PCI_PRODUCT_MARVELL_88F5182) { 995 reg = *(volatile uint32_t *)(regbase + ORION_PMI_BASE + 996 ORION_PMI_SAMPLE_AT_RESET); 997 if ((reg & ORION_PMISMPL_TCLK_MASK) == 0) 998 model = PCI_PRODUCT_MARVELL_88F5082; 999 } 1000 #endif 1001 #if defined(KIRKWOOD) 1002 if (model == PCI_PRODUCT_MARVELL_88F6281) { 1003 reg = *(volatile uint32_t *)(regbase + KIRKWOOD_MISC_BASE + 1004 KIRKWOOD_MISC_DEVICEID); 1005 if (reg == 1) /* 88F6192 is 1 */ 1006 model = MARVELL_KIRKWOOD_88F6192; 1007 } 1008 #endif 1009 1010 return model; 1011 } 1012 1013 uint8_t 1014 mvsoc_rev(void) 1015 { 1016 uint32_t reg; 1017 uint8_t rev; 1018 1019 KASSERT(regbase != 0xffffffff); 1020 1021 reg = *(volatile uint32_t *)(pex_base + PCI_CLASS_REG); 1022 rev = PCI_REVISION(reg); 1023 1024 return rev; 1025 } 1026 1027 1028 int 1029 mvsoc_target(int tag, uint32_t *target, uint32_t *attr, uint32_t *base, 1030 uint32_t *size) 1031 { 1032 int i; 1033 1034 KASSERT(regbase != 0xffffffff); 1035 1036 if (tag == MVSOC_TAG_INTERNALREG) { 1037 if (target != NULL) 1038 *target = 0; 1039 if (attr != NULL) 1040 *attr = 0; 1041 if (base != NULL) 1042 *base = read_mlmbreg(MVSOC_MLMB_IRBAR) & 1043 MVSOC_MLMB_IRBAR_BASE_MASK; 1044 if (size != NULL) 1045 *size = 0; 1046 1047 return 0; 1048 } 1049 1050 /* sanity check */ 1051 for (i = 0; i < __arraycount(mvsoc_tags); i++) 1052 if (mvsoc_tags[i].tag == tag) 1053 break; 1054 if (i >= __arraycount(mvsoc_tags)) 1055 return -1; 1056 1057 if (target != NULL) 1058 *target = mvsoc_tags[i].target; 1059 if (attr != NULL) 1060 *attr = mvsoc_tags[i].attr; 1061 1062 if (mvsoc_tags[i].target == MVSOC_UNITID_DDR) { 1063 if (tag == MARVELL_TAG_SDRAM_CS0 || 1064 tag == MARVELL_TAG_SDRAM_CS1 || 1065 tag == MARVELL_TAG_SDRAM_CS2 || 1066 tag == MARVELL_TAG_SDRAM_CS3) 1067 return mvsoc_target_ddr(mvsoc_tags[i].attr, base, size); 1068 else 1069 return mvsoc_target_ddr3(mvsoc_tags[i].attr, base, 1070 size); 1071 } else 1072 return mvsoc_target_peripheral(mvsoc_tags[i].target, 1073 mvsoc_tags[i].attr, base, size); 1074 } 1075 1076 static int 1077 mvsoc_target_ddr(uint32_t attr, uint32_t *base, uint32_t *size) 1078 { 1079 uint32_t baseaddrreg, sizereg; 1080 int cs; 1081 1082 /* 1083 * Read DDR SDRAM Controller Address Decode Registers 1084 */ 1085 1086 switch (attr) { 1087 case MARVELL_ATTR_SDRAM_CS0: 1088 cs = 0; 1089 break; 1090 case MARVELL_ATTR_SDRAM_CS1: 1091 cs = 1; 1092 break; 1093 case MARVELL_ATTR_SDRAM_CS2: 1094 cs = 2; 1095 break; 1096 case MARVELL_ATTR_SDRAM_CS3: 1097 cs = 3; 1098 break; 1099 default: 1100 aprint_error("unknwon ATTR: 0x%x", attr); 1101 return -1; 1102 } 1103 sizereg = *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSSR(cs)); 1104 if (sizereg & MVSOC_DSC_CSSR_WINEN) { 1105 baseaddrreg = 1106 *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSBAR(cs)); 1107 1108 if (base != NULL) 1109 *base = baseaddrreg & MVSOC_DSC_CSBAR_BASE_MASK; 1110 if (size != NULL) 1111 *size = (sizereg & MVSOC_DSC_CSSR_SIZE_MASK) + 1112 (~MVSOC_DSC_CSSR_SIZE_MASK + 1); 1113 } else { 1114 if (base != NULL) 1115 *base = 0; 1116 if (size != NULL) 1117 *size = 0; 1118 } 1119 return 0; 1120 } 1121 1122 static int 1123 mvsoc_target_ddr3(uint32_t attr, uint32_t *base, uint32_t *size) 1124 { 1125 uint32_t baseaddrreg, sizereg; 1126 int cs, i; 1127 1128 /* 1129 * Read DDR3 SDRAM Address Decoding Registers 1130 */ 1131 1132 switch (attr) { 1133 case MARVELL_ATTR_SDRAM_CS0: 1134 cs = 0; 1135 break; 1136 case MARVELL_ATTR_SDRAM_CS1: 1137 cs = 1; 1138 break; 1139 case MARVELL_ATTR_SDRAM_CS2: 1140 cs = 2; 1141 break; 1142 case MARVELL_ATTR_SDRAM_CS3: 1143 cs = 3; 1144 break; 1145 default: 1146 aprint_error("unknwon ATTR: 0x%x", attr); 1147 return -1; 1148 } 1149 for (i = 0; i < MVSOC_MLMB_NWIN; i++) { 1150 sizereg = read_mlmbreg(MVSOC_MLMB_WINCR(i)); 1151 if ((sizereg & MVSOC_MLMB_WINCR_EN) && 1152 MVSOC_MLMB_WINCR_WINCS(sizereg) == cs) 1153 break; 1154 } 1155 if (i == MVSOC_MLMB_NWIN) { 1156 if (base != NULL) 1157 *base = 0; 1158 if (size != NULL) 1159 *size = 0; 1160 return 0; 1161 } 1162 1163 baseaddrreg = read_mlmbreg(MVSOC_MLMB_WINBAR(i)); 1164 if (base != NULL) 1165 *base = baseaddrreg & MVSOC_MLMB_WINBAR_BASE_MASK; 1166 if (size != NULL) 1167 *size = (sizereg & MVSOC_MLMB_WINCR_SIZE_MASK) + 1168 (~MVSOC_MLMB_WINCR_SIZE_MASK + 1); 1169 return 0; 1170 } 1171 1172 static int 1173 mvsoc_target_peripheral(uint32_t target, uint32_t attr, uint32_t *base, 1174 uint32_t *size) 1175 { 1176 uint32_t basereg, ctrlreg, ta, tamask; 1177 int i; 1178 1179 /* 1180 * Read CPU Address Map Registers 1181 */ 1182 1183 ta = MVSOC_MLMB_WCR_TARGET(target) | MVSOC_MLMB_WCR_ATTR(attr); 1184 tamask = MVSOC_MLMB_WCR_TARGET(MVSOC_UNITID_MASK) | 1185 MVSOC_MLMB_WCR_ATTR(MARVELL_ATTR_MASK); 1186 1187 if (base != NULL) 1188 *base = 0; 1189 if (size != NULL) 1190 *size = 0; 1191 1192 for (i = 0; i < nwindow; i++) { 1193 ctrlreg = read_mlmbreg(MVSOC_MLMB_WCR(i)); 1194 if ((ctrlreg & tamask) != ta) 1195 continue; 1196 if (ctrlreg & MVSOC_MLMB_WCR_WINEN) { 1197 basereg = read_mlmbreg(MVSOC_MLMB_WBR(i)); 1198 1199 if (base != NULL) 1200 *base = basereg & MVSOC_MLMB_WBR_BASE_MASK; 1201 if (size != NULL) 1202 *size = (ctrlreg & 1203 MVSOC_MLMB_WCR_SIZE_MASK) + 1204 (~MVSOC_MLMB_WCR_SIZE_MASK + 1); 1205 } 1206 break; 1207 } 1208 return i; 1209 } 1210
Indexes created Thu Oct 23 22:10:10 GMT 2025