mvsocgpp.c revision 1.2.2.2
1 1.2.2.2 rmind /* $NetBSD: mvsocgpp.c,v 1.2.2.2 2011/03/05 20:49:37 rmind Exp $ */ 2 1.2.2.2 rmind /* 3 1.2.2.2 rmind * Copyright (c) 2008, 2010 KIYOHARA Takashi 4 1.2.2.2 rmind * All rights reserved. 5 1.2.2.2 rmind * 6 1.2.2.2 rmind * Redistribution and use in source and binary forms, with or without 7 1.2.2.2 rmind * modification, are permitted provided that the following conditions 8 1.2.2.2 rmind * are met: 9 1.2.2.2 rmind * 1. Redistributions of source code must retain the above copyright 10 1.2.2.2 rmind * notice, this list of conditions and the following disclaimer. 11 1.2.2.2 rmind * 2. Redistributions in binary form must reproduce the above copyright 12 1.2.2.2 rmind * notice, this list of conditions and the following disclaimer in the 13 1.2.2.2 rmind * documentation and/or other materials provided with the distribution. 14 1.2.2.2 rmind * 15 1.2.2.2 rmind * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 1.2.2.2 rmind * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 1.2.2.2 rmind * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 1.2.2.2 rmind * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 1.2.2.2 rmind * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 1.2.2.2 rmind * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 1.2.2.2 rmind * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 1.2.2.2 rmind * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 1.2.2.2 rmind * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 1.2.2.2 rmind * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 1.2.2.2 rmind * POSSIBILITY OF SUCH DAMAGE. 26 1.2.2.2 rmind */ 27 1.2.2.2 rmind 28 1.2.2.2 rmind #include <sys/cdefs.h> 29 1.2.2.2 rmind __KERNEL_RCSID(0, "$NetBSD: mvsocgpp.c,v 1.2.2.2 2011/03/05 20:49:37 rmind Exp $"); 30 1.2.2.2 rmind 31 1.2.2.2 rmind #include "gpio.h" 32 1.2.2.2 rmind 33 1.2.2.2 rmind #define _INTR_PRIVATE 34 1.2.2.2 rmind 35 1.2.2.2 rmind #include <sys/param.h> 36 1.2.2.2 rmind #include <sys/bus.h> 37 1.2.2.2 rmind #include <sys/device.h> 38 1.2.2.2 rmind #include <sys/errno.h> 39 1.2.2.2 rmind #include <sys/evcnt.h> 40 1.2.2.2 rmind #include <sys/gpio.h> 41 1.2.2.2 rmind #include <sys/kmem.h> 42 1.2.2.2 rmind 43 1.2.2.2 rmind #include <machine/intr.h> 44 1.2.2.2 rmind 45 1.2.2.2 rmind #include <arm/marvell/mvsocreg.h> 46 1.2.2.2 rmind #include <arm/marvell/mvsocvar.h> 47 1.2.2.2 rmind #include <arm/marvell/mvsocgppreg.h> 48 1.2.2.2 rmind #include <arm/marvell/mvsocgppvar.h> 49 1.2.2.2 rmind #include <arm/pic/picvar.h> 50 1.2.2.2 rmind 51 1.2.2.2 rmind #include <dev/marvell/marvellvar.h> 52 1.2.2.2 rmind 53 1.2.2.2 rmind #if NGPIO > 0 54 1.2.2.2 rmind #include <sys/gpio.h> 55 1.2.2.2 rmind #include <dev/gpio/gpiovar.h> 56 1.2.2.2 rmind #endif 57 1.2.2.2 rmind 58 1.2.2.2 rmind #define MVSOCGPP_DUMPREG 59 1.2.2.2 rmind 60 1.2.2.2 rmind #define MVSOCGPP_READ(sc, reg) \ 61 1.2.2.2 rmind bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 62 1.2.2.2 rmind #define MVSOCGPP_WRITE(sc, reg, val) \ 63 1.2.2.2 rmind bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 64 1.2.2.2 rmind 65 1.2.2.2 rmind struct mvsocgpp_softc { 66 1.2.2.2 rmind device_t sc_dev; 67 1.2.2.2 rmind 68 1.2.2.2 rmind bus_space_tag_t sc_iot; 69 1.2.2.2 rmind bus_space_handle_t sc_ioh; 70 1.2.2.2 rmind 71 1.2.2.2 rmind struct mvsocgpp_pic { 72 1.2.2.2 rmind struct pic_softc gpio_pic; 73 1.2.2.2 rmind int group; 74 1.2.2.2 rmind uint32_t edge; 75 1.2.2.2 rmind uint32_t level; 76 1.2.2.2 rmind } *sc_pic; 77 1.2.2.2 rmind 78 1.2.2.2 rmind #if NGPIO > 0 79 1.2.2.2 rmind struct gpio_chipset_tag sc_gpio_chipset; 80 1.2.2.2 rmind gpio_pin_t *sc_pins; 81 1.2.2.2 rmind #endif 82 1.2.2.2 rmind }; 83 1.2.2.2 rmind 84 1.2.2.2 rmind static int mvsocgpp_match(device_t, struct cfdata *, void *); 85 1.2.2.2 rmind static void mvsocgpp_attach(device_t, device_t, void *); 86 1.2.2.2 rmind 87 1.2.2.2 rmind #ifdef MVSOCGPP_DUMPREG 88 1.2.2.2 rmind static void mvsocgpp_dump_reg(struct mvsocgpp_softc *); 89 1.2.2.2 rmind #endif 90 1.2.2.2 rmind 91 1.2.2.2 rmind static void gpio_pic_unblock_irqs(struct pic_softc *, size_t, uint32_t); 92 1.2.2.2 rmind static void gpio_pic_block_irqs(struct pic_softc *, size_t, uint32_t); 93 1.2.2.2 rmind static int gpio_pic_find_pending_irqs(struct pic_softc *); 94 1.2.2.2 rmind static void gpio_pic_establish_irq(struct pic_softc *, struct intrsource *); 95 1.2.2.2 rmind 96 1.2.2.2 rmind static struct pic_ops gpio_pic_ops = { 97 1.2.2.2 rmind .pic_unblock_irqs = gpio_pic_unblock_irqs, 98 1.2.2.2 rmind .pic_block_irqs = gpio_pic_block_irqs, 99 1.2.2.2 rmind .pic_find_pending_irqs = gpio_pic_find_pending_irqs, 100 1.2.2.2 rmind .pic_establish_irq = gpio_pic_establish_irq, 101 1.2.2.2 rmind }; 102 1.2.2.2 rmind 103 1.2.2.2 rmind static struct mvsocgpp_softc *mvsocgpp_softc; /* One unit per One SoC */ 104 1.2.2.2 rmind int gpp_irqbase = 0; 105 1.2.2.2 rmind int gpp_npins = 0; 106 1.2.2.2 rmind 107 1.2.2.2 rmind 108 1.2.2.2 rmind CFATTACH_DECL_NEW(mvsocgpp, sizeof(struct mvsocgpp_softc), 109 1.2.2.2 rmind mvsocgpp_match, mvsocgpp_attach, NULL, NULL); 110 1.2.2.2 rmind 111 1.2.2.2 rmind 112 1.2.2.2 rmind /* ARGSUSED */ 113 1.2.2.2 rmind static int 114 1.2.2.2 rmind mvsocgpp_match(device_t parent, struct cfdata *match, void *aux) 115 1.2.2.2 rmind { 116 1.2.2.2 rmind struct marvell_attach_args *mva = aux; 117 1.2.2.2 rmind 118 1.2.2.2 rmind if (strcmp(mva->mva_name, match->cf_name) != 0) 119 1.2.2.2 rmind return 0; 120 1.2.2.2 rmind if (mva->mva_offset == MVA_OFFSET_DEFAULT || 121 1.2.2.2 rmind mva->mva_irq == MVA_IRQ_DEFAULT) 122 1.2.2.2 rmind return 0; 123 1.2.2.2 rmind 124 1.2.2.2 rmind mva->mva_size = MVSOC_GPP_SIZE; 125 1.2.2.2 rmind return 1; 126 1.2.2.2 rmind } 127 1.2.2.2 rmind 128 1.2.2.2 rmind /* ARGSUSED */ 129 1.2.2.2 rmind static void 130 1.2.2.2 rmind mvsocgpp_attach(device_t parent, device_t self, void *aux) 131 1.2.2.2 rmind { 132 1.2.2.2 rmind struct mvsocgpp_softc *sc = device_private(self); 133 1.2.2.2 rmind struct marvell_attach_args *mva = aux; 134 1.2.2.2 rmind struct pic_softc *gpio_pic; 135 1.2.2.2 rmind #if NGPIO > 0 136 1.2.2.2 rmind struct gpiobus_attach_args gba; 137 1.2.2.2 rmind gpio_pin_t *pins; 138 1.2.2.2 rmind uint32_t mask, dir, valin, valout, polarity, blink; 139 1.2.2.2 rmind #endif 140 1.2.2.2 rmind int i, j; 141 1.2.2.2 rmind void *ih; 142 1.2.2.2 rmind 143 1.2.2.2 rmind dir = valin = valout = polarity = blink = 0; 144 1.2.2.2 rmind 145 1.2.2.2 rmind aprint_normal(": Marvell SoC General Purpose I/O Port Interface\n"); 146 1.2.2.2 rmind aprint_naive("\n"); 147 1.2.2.2 rmind 148 1.2.2.2 rmind sc->sc_dev = self; 149 1.2.2.2 rmind sc->sc_iot = mva->mva_iot; 150 1.2.2.2 rmind /* Map I/O registers for oriongpp */ 151 1.2.2.2 rmind if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 152 1.2.2.2 rmind mva->mva_offset, mva->mva_size, &sc->sc_ioh)) { 153 1.2.2.2 rmind aprint_error_dev(self, "can't map registers\n"); 154 1.2.2.2 rmind return; 155 1.2.2.2 rmind } 156 1.2.2.2 rmind 157 1.2.2.2 rmind if (gpp_npins > 0) 158 1.2.2.2 rmind aprint_normal_dev(self, "%d gpio pins\n", gpp_npins); 159 1.2.2.2 rmind else { 160 1.2.2.2 rmind aprint_error_dev(self, "gpp_npins not initialized\n"); 161 1.2.2.2 rmind return; 162 1.2.2.2 rmind } 163 1.2.2.2 rmind 164 1.2.2.2 rmind mvsocgpp_softc = sc; 165 1.2.2.2 rmind 166 1.2.2.2 rmind for (i = 0; i < gpp_npins; i += 32) 167 1.2.2.2 rmind MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIC(i), 0); 168 1.2.2.2 rmind 169 1.2.2.2 rmind sc->sc_pic = 170 1.2.2.2 rmind kmem_zalloc(sizeof(struct mvsocgpp_pic) * gpp_npins / 8, KM_SLEEP); 171 1.2.2.2 rmind for (i = 0, j = 0; i < gpp_npins; i += 8, j++) { 172 1.2.2.2 rmind gpio_pic = &(sc->sc_pic + j)->gpio_pic; 173 1.2.2.2 rmind gpio_pic->pic_ops = &gpio_pic_ops; 174 1.2.2.2 rmind snprintf(gpio_pic->pic_name, sizeof(gpio_pic->pic_name), 175 1.2.2.2 rmind "%s[%d:%d]", device_xname(self), i + 7, i); 176 1.2.2.2 rmind gpio_pic->pic_maxsources = 177 1.2.2.2 rmind (gpp_npins - i) > 8 ? 8 : gpp_npins - i; 178 1.2.2.2 rmind pic_add(gpio_pic, gpp_irqbase + i); 179 1.2.2.2 rmind aprint_normal_dev(self, "interrupts %d..%d", 180 1.2.2.2 rmind gpp_irqbase + i, gpp_irqbase + i + 7); 181 1.2.2.2 rmind ih = intr_establish(mva->mva_irq + j, 182 1.2.2.2 rmind IPL_HIGH, IST_LEVEL_HIGH, pic_handle_intr, gpio_pic); 183 1.2.2.2 rmind aprint_normal(", intr %d\n", mva->mva_irq + j); 184 1.2.2.2 rmind 185 1.2.2.2 rmind (sc->sc_pic + j)->group = j; 186 1.2.2.2 rmind } 187 1.2.2.2 rmind 188 1.2.2.2 rmind #ifdef MVSOCGPP_DUMPREG 189 1.2.2.2 rmind mvsocgpp_dump_reg(sc); 190 1.2.2.2 rmind #endif 191 1.2.2.2 rmind 192 1.2.2.2 rmind #if NGPIO > 0 193 1.2.2.2 rmind sc->sc_pins = kmem_zalloc(sizeof(gpio_pin_t) * gpp_npins, KM_SLEEP); 194 1.2.2.2 rmind 195 1.2.2.2 rmind for (i = 0, mask = 1; i < gpp_npins; i++, mask <<= 1) { 196 1.2.2.2 rmind if ((i & (32 - 1)) == 0) { 197 1.2.2.2 rmind mask = 1; 198 1.2.2.2 rmind dir = MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(i)); 199 1.2.2.2 rmind valin = MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(i)); 200 1.2.2.2 rmind valout = MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(i)); 201 1.2.2.2 rmind polarity = MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(i)); 202 1.2.2.2 rmind blink = MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(i)); 203 1.2.2.2 rmind } 204 1.2.2.2 rmind pins = &sc->sc_pins[i]; 205 1.2.2.2 rmind pins->pin_num = i; 206 1.2.2.2 rmind pins->pin_caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 207 1.2.2.2 rmind GPIO_PIN_INVIN | GPIO_PIN_PULSATE); 208 1.2.2.2 rmind if (dir & mask) { 209 1.2.2.2 rmind pins->pin_flags = GPIO_PIN_INPUT; 210 1.2.2.2 rmind pins->pin_state = 211 1.2.2.2 rmind (valin & mask) ? GPIO_PIN_HIGH : GPIO_PIN_LOW; 212 1.2.2.2 rmind } else { 213 1.2.2.2 rmind pins->pin_flags = GPIO_PIN_OUTPUT; 214 1.2.2.2 rmind pins->pin_state = 215 1.2.2.2 rmind (valout & mask) ? GPIO_PIN_HIGH : GPIO_PIN_LOW; 216 1.2.2.2 rmind } 217 1.2.2.2 rmind if (polarity & mask) { 218 1.2.2.2 rmind pins->pin_flags |= GPIO_PIN_INVIN; 219 1.2.2.2 rmind } 220 1.2.2.2 rmind if (blink & mask) { 221 1.2.2.2 rmind pins->pin_flags |= GPIO_PIN_PULSATE; 222 1.2.2.2 rmind } 223 1.2.2.2 rmind } 224 1.2.2.2 rmind sc->sc_gpio_chipset.gp_cookie = sc; 225 1.2.2.2 rmind sc->sc_gpio_chipset.gp_pin_read = mvsocgpp_pin_read; 226 1.2.2.2 rmind sc->sc_gpio_chipset.gp_pin_write = mvsocgpp_pin_write; 227 1.2.2.2 rmind sc->sc_gpio_chipset.gp_pin_ctl = mvsocgpp_pin_ctl; 228 1.2.2.2 rmind gba.gba_gc = &sc->sc_gpio_chipset; 229 1.2.2.2 rmind gba.gba_pins = sc->sc_pins; 230 1.2.2.2 rmind gba.gba_npins = gpp_npins; 231 1.2.2.2 rmind config_found_ia(self, "gpiobus", &gba, gpiobus_print); 232 1.2.2.2 rmind #endif 233 1.2.2.2 rmind } 234 1.2.2.2 rmind 235 1.2.2.2 rmind /* 236 1.2.2.2 rmind * arch/arm/pic functions. 237 1.2.2.2 rmind */ 238 1.2.2.2 rmind 239 1.2.2.2 rmind static void 240 1.2.2.2 rmind gpio_pic_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask) 241 1.2.2.2 rmind { 242 1.2.2.2 rmind struct mvsocgpp_softc *sc = mvsocgpp_softc; 243 1.2.2.2 rmind struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic; 244 1.2.2.2 rmind uint32_t mask; 245 1.2.2.2 rmind int pin = mvsocgpp_pic->group << 3; 246 1.2.2.2 rmind 247 1.2.2.2 rmind MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIC(pin), 248 1.2.2.2 rmind MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(pin)) & ~irq_mask); 249 1.2.2.2 rmind if (irq_mask & mvsocgpp_pic->edge) { 250 1.2.2.2 rmind mask = MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin)); 251 1.2.2.2 rmind mask |= (irq_mask & mvsocgpp_pic->edge); 252 1.2.2.2 rmind MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIM(pin), mask); 253 1.2.2.2 rmind } 254 1.2.2.2 rmind if (irq_mask & mvsocgpp_pic->level) { 255 1.2.2.2 rmind mask = MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin)); 256 1.2.2.2 rmind mask |= (irq_mask & mvsocgpp_pic->level); 257 1.2.2.2 rmind MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOILM(pin), mask); 258 1.2.2.2 rmind } 259 1.2.2.2 rmind } 260 1.2.2.2 rmind 261 1.2.2.2 rmind /* ARGSUSED */ 262 1.2.2.2 rmind static void 263 1.2.2.2 rmind gpio_pic_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask) 264 1.2.2.2 rmind { 265 1.2.2.2 rmind struct mvsocgpp_softc *sc = mvsocgpp_softc; 266 1.2.2.2 rmind struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic; 267 1.2.2.2 rmind int pin = mvsocgpp_pic->group << 3; 268 1.2.2.2 rmind 269 1.2.2.2 rmind MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIM(pin), 270 1.2.2.2 rmind MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin)) & ~irq_mask); 271 1.2.2.2 rmind MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOILM(pin), 272 1.2.2.2 rmind MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin)) & ~irq_mask); 273 1.2.2.2 rmind } 274 1.2.2.2 rmind 275 1.2.2.2 rmind static int 276 1.2.2.2 rmind gpio_pic_find_pending_irqs(struct pic_softc *pic) 277 1.2.2.2 rmind { 278 1.2.2.2 rmind struct mvsocgpp_softc *sc = mvsocgpp_softc; 279 1.2.2.2 rmind struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic; 280 1.2.2.2 rmind uint32_t pending; 281 1.2.2.2 rmind int pin = mvsocgpp_pic->group << 3; 282 1.2.2.2 rmind 283 1.2.2.2 rmind pending = MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(pin)); 284 1.2.2.2 rmind pending &= (0xff << mvsocgpp_pic->group); 285 1.2.2.2 rmind pending &= (MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin)) | 286 1.2.2.2 rmind MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin))); 287 1.2.2.2 rmind if (pending == 0) 288 1.2.2.2 rmind return 0; 289 1.2.2.2 rmind pic_mark_pending_sources(pic, 0, pending); 290 1.2.2.2 rmind return 1; 291 1.2.2.2 rmind } 292 1.2.2.2 rmind 293 1.2.2.2 rmind static void 294 1.2.2.2 rmind gpio_pic_establish_irq(struct pic_softc *pic, struct intrsource *is) 295 1.2.2.2 rmind { 296 1.2.2.2 rmind struct mvsocgpp_softc *sc = mvsocgpp_softc; 297 1.2.2.2 rmind struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic; 298 1.2.2.2 rmind uint32_t im, ilm, mask; 299 1.2.2.2 rmind int type, pin; 300 1.2.2.2 rmind 301 1.2.2.2 rmind type = is->is_type; 302 1.2.2.2 rmind pin = pic->pic_irqbase + is->is_irq - gpp_irqbase; 303 1.2.2.2 rmind mask = MVSOCGPP_GPIOPIN(pin); 304 1.2.2.2 rmind 305 1.2.2.2 rmind switch (type) { 306 1.2.2.2 rmind case IST_LEVEL_LOW: 307 1.2.2.2 rmind case IST_EDGE_FALLING: 308 1.2.2.2 rmind mvsocgpp_pin_ctl(NULL, pin, GPIO_PIN_INPUT | GPIO_PIN_INVIN); 309 1.2.2.2 rmind break; 310 1.2.2.2 rmind 311 1.2.2.2 rmind case IST_LEVEL_HIGH: 312 1.2.2.2 rmind case IST_EDGE_RISING: 313 1.2.2.2 rmind mvsocgpp_pin_ctl(NULL, pin, GPIO_PIN_INPUT); 314 1.2.2.2 rmind break; 315 1.2.2.2 rmind 316 1.2.2.2 rmind default: 317 1.2.2.2 rmind panic("unknwon interrupt type %d for pin %d.\n", type, pin); 318 1.2.2.2 rmind } 319 1.2.2.2 rmind 320 1.2.2.2 rmind im = MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin)); 321 1.2.2.2 rmind ilm = MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin)); 322 1.2.2.2 rmind switch (type) { 323 1.2.2.2 rmind case IST_EDGE_FALLING: 324 1.2.2.2 rmind case IST_EDGE_RISING: 325 1.2.2.2 rmind im |= mask; 326 1.2.2.2 rmind ilm &= ~mask; 327 1.2.2.2 rmind mvsocgpp_pic->edge |= mask; 328 1.2.2.2 rmind mvsocgpp_pic->level &= ~mask; 329 1.2.2.2 rmind break; 330 1.2.2.2 rmind 331 1.2.2.2 rmind case IST_LEVEL_LOW: 332 1.2.2.2 rmind case IST_LEVEL_HIGH: 333 1.2.2.2 rmind im &= ~mask; 334 1.2.2.2 rmind ilm |= mask; 335 1.2.2.2 rmind mvsocgpp_pic->edge &= ~mask; 336 1.2.2.2 rmind mvsocgpp_pic->level |= mask; 337 1.2.2.2 rmind break; 338 1.2.2.2 rmind } 339 1.2.2.2 rmind MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIM(pin), im); 340 1.2.2.2 rmind MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOILM(pin), ilm); 341 1.2.2.2 rmind } 342 1.2.2.2 rmind 343 1.2.2.2 rmind 344 1.2.2.2 rmind /* 345 1.2.2.2 rmind * gpio(4) functions, and can call you. 346 1.2.2.2 rmind */ 347 1.2.2.2 rmind 348 1.2.2.2 rmind /* ARGSUSED */ 349 1.2.2.2 rmind int 350 1.2.2.2 rmind mvsocgpp_pin_read(void *arg, int pin) 351 1.2.2.2 rmind { 352 1.2.2.2 rmind struct mvsocgpp_softc *sc = mvsocgpp_softc; 353 1.2.2.2 rmind uint32_t val; 354 1.2.2.2 rmind 355 1.2.2.2 rmind KASSERT(sc != NULL); 356 1.2.2.2 rmind 357 1.2.2.2 rmind val = MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(pin)); 358 1.2.2.2 rmind return (val & MVSOCGPP_GPIOPIN(pin)) != 0; 359 1.2.2.2 rmind } 360 1.2.2.2 rmind 361 1.2.2.2 rmind /* ARGSUSED */ 362 1.2.2.2 rmind void 363 1.2.2.2 rmind mvsocgpp_pin_write(void *arg, int pin, int value) 364 1.2.2.2 rmind { 365 1.2.2.2 rmind struct mvsocgpp_softc *sc = mvsocgpp_softc; 366 1.2.2.2 rmind uint32_t old, new, mask = MVSOCGPP_GPIOPIN(pin); 367 1.2.2.2 rmind 368 1.2.2.2 rmind KASSERT(sc != NULL); 369 1.2.2.2 rmind 370 1.2.2.2 rmind old = MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(pin)); 371 1.2.2.2 rmind if (value) 372 1.2.2.2 rmind new = old | mask; 373 1.2.2.2 rmind else 374 1.2.2.2 rmind new = old & ~mask; 375 1.2.2.2 rmind if (new != old) 376 1.2.2.2 rmind MVSOCGPP_WRITE(sc, MVSOCGPP_GPIODO(pin), new); 377 1.2.2.2 rmind } 378 1.2.2.2 rmind 379 1.2.2.2 rmind /* ARGSUSED */ 380 1.2.2.2 rmind void 381 1.2.2.2 rmind mvsocgpp_pin_ctl(void *arg, int pin, int flags) 382 1.2.2.2 rmind { 383 1.2.2.2 rmind struct mvsocgpp_softc *sc = mvsocgpp_softc; 384 1.2.2.2 rmind uint32_t old, new, mask = MVSOCGPP_GPIOPIN(pin); 385 1.2.2.2 rmind 386 1.2.2.2 rmind KASSERT(sc != NULL); 387 1.2.2.2 rmind 388 1.2.2.2 rmind old = MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(pin)); 389 1.2.2.2 rmind switch (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { 390 1.2.2.2 rmind case GPIO_PIN_INPUT: 391 1.2.2.2 rmind new = old | mask; 392 1.2.2.2 rmind break; 393 1.2.2.2 rmind 394 1.2.2.2 rmind case GPIO_PIN_OUTPUT: 395 1.2.2.2 rmind new = old & ~mask; 396 1.2.2.2 rmind break; 397 1.2.2.2 rmind 398 1.2.2.2 rmind default: 399 1.2.2.2 rmind return; 400 1.2.2.2 rmind } 401 1.2.2.2 rmind if (new != old) 402 1.2.2.2 rmind MVSOCGPP_WRITE(sc, MVSOCGPP_GPIODOEC(pin), new); 403 1.2.2.2 rmind 404 1.2.2.2 rmind /* Blink every 2^24 TCLK */ 405 1.2.2.2 rmind old = MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(pin)); 406 1.2.2.2 rmind if (flags & GPIO_PIN_PULSATE) 407 1.2.2.2 rmind new = old | mask; 408 1.2.2.2 rmind else 409 1.2.2.2 rmind new = old & ~mask; 410 1.2.2.2 rmind if (new != old) 411 1.2.2.2 rmind MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOBE(pin), new); 412 1.2.2.2 rmind 413 1.2.2.2 rmind old = MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(pin)); 414 1.2.2.2 rmind if (flags & GPIO_PIN_INVIN) 415 1.2.2.2 rmind new = old | mask; 416 1.2.2.2 rmind else 417 1.2.2.2 rmind new = old & ~mask; 418 1.2.2.2 rmind if (new != old) 419 1.2.2.2 rmind MVSOCGPP_WRITE(sc, MVSOCGPP_GPIODIP(pin), new); 420 1.2.2.2 rmind } 421 1.2.2.2 rmind 422 1.2.2.2 rmind 423 1.2.2.2 rmind #ifdef MVSOCGPP_DUMPREG 424 1.2.2.2 rmind static void 425 1.2.2.2 rmind mvsocgpp_dump_reg(struct mvsocgpp_softc *sc) 426 1.2.2.2 rmind { 427 1.2.2.2 rmind 428 1.2.2.2 rmind aprint_normal_dev(sc->sc_dev, " Data Out: \t0x%08x\n", 429 1.2.2.2 rmind MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(0))); 430 1.2.2.2 rmind aprint_normal_dev(sc->sc_dev, " Data Out Enable Control: \t0x%08x\n", 431 1.2.2.2 rmind MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(0))); 432 1.2.2.2 rmind aprint_normal_dev(sc->sc_dev, " Data Blink Enable: \t0x%08x\n", 433 1.2.2.2 rmind MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(0))); 434 1.2.2.2 rmind aprint_normal_dev(sc->sc_dev, " Data In Polarity: \t0x%08x\n", 435 1.2.2.2 rmind MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(0))); 436 1.2.2.2 rmind aprint_normal_dev(sc->sc_dev, " Data In: \t0x%08x\n", 437 1.2.2.2 rmind MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(0))); 438 1.2.2.2 rmind aprint_normal_dev(sc->sc_dev, " Interrupt Cause: \t0x%08x\n", 439 1.2.2.2 rmind MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(0))); 440 1.2.2.2 rmind aprint_normal_dev(sc->sc_dev, " Interrupt Mask: \t0x%08x\n", 441 1.2.2.2 rmind MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(0))); 442 1.2.2.2 rmind aprint_normal_dev(sc->sc_dev, " Interrupt Level Mask: \t0x%08x\n", 443 1.2.2.2 rmind MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(0))); 444 1.2.2.2 rmind 445 1.2.2.2 rmind if (gpp_npins <= 32) 446 1.2.2.2 rmind return; 447 1.2.2.2 rmind 448 1.2.2.2 rmind aprint_normal_dev(sc->sc_dev, " High Data Out: \t0x%08x\n", 449 1.2.2.2 rmind MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(32))); 450 1.2.2.2 rmind aprint_normal_dev(sc->sc_dev, " High Data Out Enable Ctrl:\t0x%08x\n", 451 1.2.2.2 rmind MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(32))); 452 1.2.2.2 rmind aprint_normal_dev(sc->sc_dev, " High Blink Enable: \t0x%08x\n", 453 1.2.2.2 rmind MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(32))); 454 1.2.2.2 rmind aprint_normal_dev(sc->sc_dev, " High Data In Polarity: \t0x%08x\n", 455 1.2.2.2 rmind MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(32))); 456 1.2.2.2 rmind aprint_normal_dev(sc->sc_dev, " High Data In: \t0x%08x\n", 457 1.2.2.2 rmind MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(32))); 458 1.2.2.2 rmind aprint_normal_dev(sc->sc_dev, " High Interrupt Cause: \t0x%08x\n", 459 1.2.2.2 rmind MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(32))); 460 1.2.2.2 rmind aprint_normal_dev(sc->sc_dev, " High Interrupt Mask: \t0x%08x\n", 461 1.2.2.2 rmind MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(32))); 462 1.2.2.2 rmind aprint_normal_dev(sc->sc_dev, " High Interrupt Level Mask:\t0x%08x\n", 463 1.2.2.2 rmind MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(32))); 464 1.2.2.2 rmind } 465 1.2.2.2 rmind #endif 466
Indexes created Wed Oct 22 13:09:56 GMT 2025