mvsocgpp.c revision 1.1.8.1
1 /* $NetBSD: mvsocgpp.c,v 1.1.8.1 2011/02/08 16:19:12 bouyer Exp $ */ 2 /* 3 * Copyright (c) 2008, 2010 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsocgpp.c,v 1.1.8.1 2011/02/08 16:19:12 bouyer Exp $"); 30 31 #include "gpio.h" 32 33 #define _INTR_PRIVATE 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/errno.h> 39 #include <sys/evcnt.h> 40 #include <sys/gpio.h> 41 #include <sys/kmem.h> 42 43 #include <machine/intr.h> 44 45 #include <arm/marvell/mvsocreg.h> 46 #include <arm/marvell/mvsocvar.h> 47 #include <arm/marvell/mvsocgppreg.h> 48 #include <arm/marvell/mvsocgppvar.h> 49 #include <arm/pic/picvar.h> 50 51 #include <dev/marvell/marvellvar.h> 52 53 #if NGPIO > 0 54 #include <sys/gpio.h> 55 #include <dev/gpio/gpiovar.h> 56 #endif 57 58 #define MVSOCGPP_DUMPREG 59 60 #define MVSOCGPP_READ(sc, reg) \ 61 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 62 #define MVSOCGPP_WRITE(sc, reg, val) \ 63 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 64 65 struct mvsocgpp_softc { 66 device_t sc_dev; 67 68 bus_space_tag_t sc_iot; 69 bus_space_handle_t sc_ioh; 70 71 struct mvsocgpp_pic { 72 struct pic_softc gpio_pic; 73 int group; 74 uint32_t edge; 75 uint32_t level; 76 } *sc_pic; 77 78 #if NGPIO > 0 79 struct gpio_chipset_tag sc_gpio_chipset; 80 gpio_pin_t *sc_pins; 81 #endif 82 }; 83 84 static int mvsocgpp_match(device_t, struct cfdata *, void *); 85 static void mvsocgpp_attach(device_t, device_t, void *); 86 87 #ifdef MVSOCGPP_DUMPREG 88 static void mvsocgpp_dump_reg(struct mvsocgpp_softc *); 89 #endif 90 91 static void gpio_pic_unblock_irqs(struct pic_softc *, size_t, uint32_t); 92 static void gpio_pic_block_irqs(struct pic_softc *, size_t, uint32_t); 93 static int gpio_pic_find_pending_irqs(struct pic_softc *); 94 static void gpio_pic_establish_irq(struct pic_softc *, struct intrsource *); 95 96 static struct pic_ops gpio_pic_ops = { 97 .pic_unblock_irqs = gpio_pic_unblock_irqs, 98 .pic_block_irqs = gpio_pic_block_irqs, 99 .pic_find_pending_irqs = gpio_pic_find_pending_irqs, 100 .pic_establish_irq = gpio_pic_establish_irq, 101 }; 102 103 static struct mvsocgpp_softc *mvsocgpp_softc; /* One unit per One SoC */ 104 int gpp_irqbase = 0; 105 int gpp_npins = 0; 106 107 108 CFATTACH_DECL_NEW(mvsocgpp, sizeof(struct mvsocgpp_softc), 109 mvsocgpp_match, mvsocgpp_attach, NULL, NULL); 110 111 112 /* ARGSUSED */ 113 static int 114 mvsocgpp_match(device_t parent, struct cfdata *match, void *aux) 115 { 116 struct marvell_attach_args *mva = aux; 117 118 if (strcmp(mva->mva_name, match->cf_name) != 0) 119 return 0; 120 if (mva->mva_offset == MVA_OFFSET_DEFAULT || 121 mva->mva_irq == MVA_IRQ_DEFAULT) 122 return 0; 123 124 mva->mva_size = MVSOC_GPP_SIZE; 125 return 1; 126 } 127 128 /* ARGSUSED */ 129 static void 130 mvsocgpp_attach(device_t parent, device_t self, void *aux) 131 { 132 struct mvsocgpp_softc *sc = device_private(self); 133 struct marvell_attach_args *mva = aux; 134 struct pic_softc *gpio_pic; 135 #if NGPIO > 0 136 struct gpiobus_attach_args gba; 137 gpio_pin_t *pins; 138 uint32_t mask, dir, valin, valout, polarity, blink; 139 #endif 140 int i, j; 141 void *ih; 142 143 dir = valin = valout = polarity = blink = 0; 144 145 aprint_normal(": Marvell SoC General Purpose I/O Port Interface\n"); 146 aprint_naive("\n"); 147 148 sc->sc_dev = self; 149 sc->sc_iot = mva->mva_iot; 150 /* Map I/O registers for oriongpp */ 151 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 152 mva->mva_offset, mva->mva_size, &sc->sc_ioh)) { 153 aprint_error_dev(self, "can't map registers\n"); 154 return; 155 } 156 157 if (gpp_npins > 0) 158 aprint_normal_dev(self, "%d gpio pins\n", gpp_npins); 159 else { 160 aprint_error_dev(self, "gpp_npins not initialized\n"); 161 return; 162 } 163 164 mvsocgpp_softc = sc; 165 166 for (i = 0; i < gpp_npins; i += 32) 167 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIC(i), 0); 168 169 sc->sc_pic = 170 kmem_zalloc(sizeof(struct mvsocgpp_pic) * gpp_npins / 8, KM_SLEEP); 171 for (i = 0, j = 0; i < gpp_npins; i += 8, j++) { 172 gpio_pic = &(sc->sc_pic + j)->gpio_pic; 173 gpio_pic->pic_ops = &gpio_pic_ops; 174 snprintf(gpio_pic->pic_name, sizeof(gpio_pic->pic_name), 175 "%s[%d:%d]", device_xname(self), i + 7, i); 176 gpio_pic->pic_maxsources = 177 (gpp_npins - i) > 8 ? 8 : gpp_npins - i; 178 pic_add(gpio_pic, gpp_irqbase + i); 179 aprint_normal_dev(self, "interrupts %d..%d", 180 gpp_irqbase + i, gpp_irqbase + i + 7); 181 ih = intr_establish(mva->mva_irq + j, 182 IPL_HIGH, IST_LEVEL_HIGH, pic_handle_intr, gpio_pic); 183 aprint_normal(", intr %d\n", mva->mva_irq + j); 184 185 (sc->sc_pic + j)->group = j; 186 } 187 188 #ifdef MVSOCGPP_DUMPREG 189 mvsocgpp_dump_reg(sc); 190 #endif 191 192 #if NGPIO > 0 193 sc->sc_pins = kmem_zalloc(sizeof(gpio_pin_t) * gpp_npins, KM_SLEEP); 194 195 for (i = 0, mask = 1; i < gpp_npins; i++, mask <<= 1) { 196 if ((i & (32 - 1)) == 0) { 197 mask = 1; 198 dir = MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(i)); 199 valin = MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(i)); 200 valout = MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(i)); 201 polarity = MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(i)); 202 blink = MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(i)); 203 } 204 pins = &sc->sc_pins[i]; 205 pins->pin_num = i; 206 pins->pin_caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 207 GPIO_PIN_INVIN | GPIO_PIN_PULSATE); 208 if (dir & mask) { 209 pins->pin_flags = GPIO_PIN_INPUT; 210 pins->pin_state = 211 (valin & mask) ? GPIO_PIN_HIGH : GPIO_PIN_LOW; 212 } else { 213 pins->pin_flags = GPIO_PIN_OUTPUT; 214 pins->pin_state = 215 (valout & mask) ? GPIO_PIN_HIGH : GPIO_PIN_LOW; 216 } 217 if (polarity & mask) { 218 pins->pin_flags |= GPIO_PIN_INVIN; 219 } 220 if (blink & mask) { 221 pins->pin_flags |= GPIO_PIN_PULSATE; 222 } 223 } 224 sc->sc_gpio_chipset.gp_cookie = sc; 225 sc->sc_gpio_chipset.gp_pin_read = mvsocgpp_pin_read; 226 sc->sc_gpio_chipset.gp_pin_write = mvsocgpp_pin_write; 227 sc->sc_gpio_chipset.gp_pin_ctl = mvsocgpp_pin_ctl; 228 gba.gba_gc = &sc->sc_gpio_chipset; 229 gba.gba_pins = sc->sc_pins; 230 gba.gba_npins = gpp_npins; 231 config_found_ia(self, "gpiobus", &gba, gpiobus_print); 232 #endif 233 } 234 235 /* 236 * arch/arm/pic functions. 237 */ 238 239 static void 240 gpio_pic_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask) 241 { 242 struct mvsocgpp_softc *sc = mvsocgpp_softc; 243 struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic; 244 uint32_t mask; 245 int pin = mvsocgpp_pic->group << 3; 246 247 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIC(pin), 248 MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(pin)) & ~irq_mask); 249 if (irq_mask & mvsocgpp_pic->edge) { 250 mask = MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin)); 251 mask |= (irq_mask & mvsocgpp_pic->edge); 252 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIM(pin), mask); 253 } 254 if (irq_mask & mvsocgpp_pic->level) { 255 mask = MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin)); 256 mask |= (irq_mask & mvsocgpp_pic->level); 257 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOILM(pin), mask); 258 } 259 } 260 261 /* ARGSUSED */ 262 static void 263 gpio_pic_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask) 264 { 265 struct mvsocgpp_softc *sc = mvsocgpp_softc; 266 struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic; 267 int pin = mvsocgpp_pic->group << 3; 268 269 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIM(pin), 270 MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin)) & ~irq_mask); 271 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOILM(pin), 272 MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin)) & ~irq_mask); 273 } 274 275 static int 276 gpio_pic_find_pending_irqs(struct pic_softc *pic) 277 { 278 struct mvsocgpp_softc *sc = mvsocgpp_softc; 279 struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic; 280 uint32_t pending; 281 int pin = mvsocgpp_pic->group << 3; 282 283 pending = MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(pin)); 284 pending &= (0xff << mvsocgpp_pic->group); 285 pending &= (MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin)) | 286 MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin))); 287 if (pending == 0) 288 return 0; 289 pic_mark_pending_sources(pic, 0, pending); 290 return 1; 291 } 292 293 static void 294 gpio_pic_establish_irq(struct pic_softc *pic, struct intrsource *is) 295 { 296 struct mvsocgpp_softc *sc = mvsocgpp_softc; 297 struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic; 298 uint32_t im, ilm, mask; 299 int type, pin; 300 301 type = is->is_type; 302 pin = pic->pic_irqbase + is->is_irq - gpp_irqbase; 303 mask = MVSOCGPP_GPIOPIN(pin); 304 305 switch (type) { 306 case IST_LEVEL_LOW: 307 case IST_EDGE_FALLING: 308 mvsocgpp_pin_ctl(NULL, pin, GPIO_PIN_INPUT | GPIO_PIN_INVIN); 309 break; 310 311 case IST_LEVEL_HIGH: 312 case IST_EDGE_RISING: 313 mvsocgpp_pin_ctl(NULL, pin, GPIO_PIN_INPUT); 314 break; 315 316 default: 317 panic("unknwon interrupt type %d for pin %d.\n", type, pin); 318 } 319 320 im = MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin)); 321 ilm = MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin)); 322 switch (type) { 323 case IST_EDGE_FALLING: 324 case IST_EDGE_RISING: 325 im |= mask; 326 ilm &= ~mask; 327 mvsocgpp_pic->edge |= mask; 328 mvsocgpp_pic->level &= ~mask; 329 break; 330 331 case IST_LEVEL_LOW: 332 case IST_LEVEL_HIGH: 333 im &= ~mask; 334 ilm |= mask; 335 mvsocgpp_pic->edge &= ~mask; 336 mvsocgpp_pic->level |= mask; 337 break; 338 } 339 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIM(pin), im); 340 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOILM(pin), ilm); 341 } 342 343 344 /* 345 * gpio(4) functions, and can call you. 346 */ 347 348 /* ARGSUSED */ 349 int 350 mvsocgpp_pin_read(void *arg, int pin) 351 { 352 struct mvsocgpp_softc *sc = mvsocgpp_softc; 353 uint32_t val; 354 355 KASSERT(sc != NULL); 356 357 val = MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(pin)); 358 return (val & MVSOCGPP_GPIOPIN(pin)) != 0; 359 } 360 361 /* ARGSUSED */ 362 void 363 mvsocgpp_pin_write(void *arg, int pin, int value) 364 { 365 struct mvsocgpp_softc *sc = mvsocgpp_softc; 366 uint32_t old, new, mask = MVSOCGPP_GPIOPIN(pin); 367 368 KASSERT(sc != NULL); 369 370 old = MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(pin)); 371 if (value) 372 new = old | mask; 373 else 374 new = old & ~mask; 375 if (new != old) 376 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIODO(pin), new); 377 } 378 379 /* ARGSUSED */ 380 void 381 mvsocgpp_pin_ctl(void *arg, int pin, int flags) 382 { 383 struct mvsocgpp_softc *sc = mvsocgpp_softc; 384 uint32_t old, new, mask = MVSOCGPP_GPIOPIN(pin); 385 386 KASSERT(sc != NULL); 387 388 old = MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(pin)); 389 switch (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { 390 case GPIO_PIN_INPUT: 391 new = old | mask; 392 break; 393 394 case GPIO_PIN_OUTPUT: 395 new = old & ~mask; 396 break; 397 398 default: 399 return; 400 } 401 if (new != old) 402 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIODOEC(pin), new); 403 404 /* Blink every 2^24 TCLK */ 405 old = MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(pin)); 406 if (flags & GPIO_PIN_PULSATE) 407 new = old | mask; 408 else 409 new = old & ~mask; 410 if (new != old) 411 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOBE(pin), new); 412 413 old = MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(pin)); 414 if (flags & GPIO_PIN_INVIN) 415 new = old | mask; 416 else 417 new = old & ~mask; 418 if (new != old) 419 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIODIP(pin), new); 420 } 421 422 423 #ifdef MVSOCGPP_DUMPREG 424 static void 425 mvsocgpp_dump_reg(struct mvsocgpp_softc *sc) 426 { 427 428 aprint_normal_dev(sc->sc_dev, " Data Out: \t0x%08x\n", 429 MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(0))); 430 aprint_normal_dev(sc->sc_dev, " Data Out Enable Control: \t0x%08x\n", 431 MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(0))); 432 aprint_normal_dev(sc->sc_dev, " Data Blink Enable: \t0x%08x\n", 433 MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(0))); 434 aprint_normal_dev(sc->sc_dev, " Data In Polarity: \t0x%08x\n", 435 MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(0))); 436 aprint_normal_dev(sc->sc_dev, " Data In: \t0x%08x\n", 437 MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(0))); 438 aprint_normal_dev(sc->sc_dev, " Interrupt Cause: \t0x%08x\n", 439 MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(0))); 440 aprint_normal_dev(sc->sc_dev, " Interrupt Mask: \t0x%08x\n", 441 MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(0))); 442 aprint_normal_dev(sc->sc_dev, " Interrupt Level Mask: \t0x%08x\n", 443 MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(0))); 444 445 if (gpp_npins <= 32) 446 return; 447 448 aprint_normal_dev(sc->sc_dev, " High Data Out: \t0x%08x\n", 449 MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(32))); 450 aprint_normal_dev(sc->sc_dev, " High Data Out Enable Ctrl:\t0x%08x\n", 451 MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(32))); 452 aprint_normal_dev(sc->sc_dev, " High Blink Enable: \t0x%08x\n", 453 MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(32))); 454 aprint_normal_dev(sc->sc_dev, " High Data In Polarity: \t0x%08x\n", 455 MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(32))); 456 aprint_normal_dev(sc->sc_dev, " High Data In: \t0x%08x\n", 457 MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(32))); 458 aprint_normal_dev(sc->sc_dev, " High Interrupt Cause: \t0x%08x\n", 459 MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(32))); 460 aprint_normal_dev(sc->sc_dev, " High Interrupt Mask: \t0x%08x\n", 461 MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(32))); 462 aprint_normal_dev(sc->sc_dev, " High Interrupt Level Mask:\t0x%08x\n", 463 MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(32))); 464 } 465 #endif 466
Indexes created Thu Oct 23 22:10:10 GMT 2025