Home | History | Annotate | Line # | Download | only in marvell
mvsocgppreg.h revision 1.1.10.2 
      1 /*	$NetBSD: mvsocgppreg.h,v 1.1.10.2 2011/03/05 20:49:37 rmind Exp $	*/
      2 /*
      3  * Copyright (c) 2008 KIYOHARA Takashi
      4  * All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     17  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
     19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
     23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
     24  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     25  * POSSIBILITY OF SUCH DAMAGE.
     26  */
     27 
     28 #ifndef _MVSOCGPPREG_H_
     29 #define _MVSOCGPPREG_H_
     30 
     31 #define MVSOC_GPP_SIZE		0x100
     32 
     33 /*
     34  * General Purpose Port Registers
     35  */
     36 /* GPIO Register Map */
     37 					/* GPIO Data Out */
     38 #define MVSOCGPP_GPIODO(p)	((((p) & 0x20) << 1) + 0x00)
     39 					/* GPIO Data Out Enable Control */
     40 #define MVSOCGPP_GPIODOEC(p)	((((p) & 0x20) << 1) + 0x04)
     41 					/* GPIO Blink Enable Control */
     42 #define MVSOCGPP_GPIOBE(p)	((((p) & 0x20) << 1) + 0x08)
     43 					/* GPIO Data In Polarity */
     44 #define MVSOCGPP_GPIODIP(p)	((((p) & 0x20) << 1) + 0x0c)
     45 					/* GPIO Data In */
     46 #define MVSOCGPP_GPIODI(p)	((((p) & 0x20) << 1) + 0x10)
     47 					/* GPIO Interrupt Cause */
     48 #define MVSOCGPP_GPIOIC(p)	((((p) & 0x20) << 1) + 0x14)
     49 					/* GPIO Interrupt Mask */
     50 #define MVSOCGPP_GPIOIM(p)	((((p) & 0x20) << 1) + 0x18)
     51 					/* GPIO Interrupt Level Mask */
     52 #define MVSOCGPP_GPIOILM(p)	((((p) & 0x20) << 1) + 0x1c)
     53 
     54 #define MVSOCGPP_GPIOPIN(pin)		(1 << ((pin) & 0x1f))
     55 
     56 /* Out Enable */
     57 #define MVSOCGPP_GPIODOE_OUT		0
     58 #define MVSOCGPP_GPIODOE_IN		1
     59 
     60 /* Polarity */
     61 #define MVSOCGPP_GPIODIP_INVERT		1
     62 
     63 /* Interrupt Mask */
     64 #define MVSOCGPP_GPIOIM_EDGE		0
     65 #define MVSOCGPP_GPIOIM_LEVEL		1
     66 
     67 #endif	/* _ORIONPCIREG_H_ */
     68