soc_tegra124.c revision 1.2 1 /* $NetBSD: soc_tegra124.c,v 1.2 2015/04/26 22:04:28 jmcneill Exp $ */
2
3 /*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include "opt_tegra.h"
30 #include "opt_multiprocessor.h"
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: soc_tegra124.c,v 1.2 2015/04/26 22:04:28 jmcneill Exp $");
34
35 #include <sys/param.h>
36 #include <sys/bus.h>
37 #include <sys/cpu.h>
38 #include <sys/device.h>
39
40 #include <uvm/uvm_extern.h>
41
42 #include <arm/cpufunc.h>
43
44 #include <arm/nvidia/tegra_reg.h>
45 #include <arm/nvidia/tegra_pmcreg.h>
46 #include <arm/nvidia/tegra_var.h>
47
48 #define EVP_RESET_VECTOR_0_REG 0x100
49
50 void
51 tegra124_mpinit(void)
52 {
53 #if defined(MULTIPROCESSOR)
54 extern void cortex_mpstart(void);
55 bus_space_tag_t bst = &armv7_generic_bs_tag;
56 bus_space_handle_t bsh;
57 u_int i;
58
59 bus_space_subregion(bst, tegra_ppsb_bsh,
60 TEGRA_EVP_OFFSET, TEGRA_EVP_SIZE, &bsh);
61
62 arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU);
63 KASSERT(arm_cpu_max == 4);
64
65 bus_space_write_4(bst, bsh, EVP_RESET_VECTOR_0_REG, (uint32_t)cortex_mpstart);
66 bus_space_barrier(bst, bsh, EVP_RESET_VECTOR_0_REG, 4,
67 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
68
69 tegra_pmc_power(PMC_PARTID_CPU1, true);
70 tegra_pmc_power(PMC_PARTID_CPU2, true);
71 tegra_pmc_power(PMC_PARTID_CPU3, true);
72
73 for (i = 0x10000000; i > 0; i--) {
74 __asm __volatile("dmb" ::: "memory");
75 if (arm_cpu_hatched == 0xe)
76 break;
77 }
78 #endif
79 }
80