Home | History | Annotate | Line # | Download | only in nvidia
soc_tegra124.c revision 1.7 
      1 /* $NetBSD: soc_tegra124.c,v 1.7 2015/11/11 12:49:10 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #include "opt_tegra.h"
     30 #include "opt_multiprocessor.h"
     31 
     32 #include <sys/cdefs.h>
     33 __KERNEL_RCSID(0, "$NetBSD: soc_tegra124.c,v 1.7 2015/11/11 12:49:10 jmcneill Exp $");
     34 
     35 #include <sys/param.h>
     36 #include <sys/bus.h>
     37 #include <sys/cpu.h>
     38 #include <sys/device.h>
     39 
     40 #include <uvm/uvm_extern.h>
     41 
     42 #include <arm/cpufunc.h>
     43 
     44 #include <arm/nvidia/tegra_reg.h>
     45 #include <arm/nvidia/tegra_pmcreg.h>
     46 #include <arm/nvidia/tegra_var.h>
     47 
     48 #define EVP_RESET_VECTOR_0_REG	0x100
     49 
     50 static u_int	tegra124_cpufreq_set_rate(u_int);
     51 static u_int	tegra124_cpufreq_get_rate(void);
     52 static size_t	tegra124_cpufreq_get_available(u_int *, size_t);
     53 
     54 static const struct tegra_cpufreq_func tegra124_cpufreq_func = {
     55 	.set_rate = tegra124_cpufreq_set_rate,
     56 	.get_rate = tegra124_cpufreq_get_rate,
     57 	.get_available = tegra124_cpufreq_get_available,
     58 };
     59 
     60 static struct tegra124_cpufreq_rate {
     61 	u_int rate;
     62 	u_int divm;
     63 	u_int divn;
     64 	u_int divp;
     65 } tegra124_cpufreq_rates[] = {
     66 	{ 2292, 1, 191, 0 },
     67 	{ 2100, 1, 175, 0 },
     68 	{ 1896, 1, 158, 0 },
     69 	{ 1692, 1, 141, 0 },
     70 	{ 1500, 1, 125, 0 },
     71 	{ 1296, 1, 108, 0 },
     72 	{ 1092, 1, 91, 0 },
     73 	{ 900, 1, 75, 0 },
     74 	{ 696, 1, 58, 0 }
     75 };
     76 
     77 void
     78 tegra124_cpuinit(void)
     79 {
     80 	tegra_car_periph_i2c_enable(4, 204000000);
     81 
     82 	/* Set VDD_CPU voltage to 1.4V */
     83 	const u_int target_mv = 1400;
     84 	const u_int sd0_vsel = (target_mv - 600) / 10;
     85 	tegra_i2c_dvc_write(0x40, (sd0_vsel << 8) | 00, 2);
     86 	delay(10000);
     87 
     88 	tegra_cpufreq_register(&tegra124_cpufreq_func);
     89 }
     90 
     91 static u_int
     92 tegra124_cpufreq_set_rate(u_int rate)
     93 {
     94 	const u_int nrates = __arraycount(tegra124_cpufreq_rates);
     95 	const struct tegra124_cpufreq_rate *r = NULL;
     96 
     97 	for (int i = 0; i < nrates; i++) {
     98 		if (tegra124_cpufreq_rates[i].rate == rate) {
     99 			r = &tegra124_cpufreq_rates[i];
    100 			break;
    101 		}
    102 	}
    103 	if (r == NULL)
    104 		return EINVAL;
    105 
    106 	tegra_car_pllx_set_rate(r->divm, r->divn, r->divp);
    107 
    108 	return 0;
    109 }
    110 
    111 static u_int
    112 tegra124_cpufreq_get_rate(void)
    113 {
    114 	return tegra_car_pllx_rate() / 1000000;
    115 }
    116 
    117 static size_t
    118 tegra124_cpufreq_get_available(u_int *pavail, size_t maxavail)
    119 {
    120 	const u_int nrates = __arraycount(tegra124_cpufreq_rates);
    121 	u_int n;
    122 
    123 	KASSERT(nrates <= maxavail);
    124 
    125 	for (n = 0; n < nrates; n++) {
    126 		pavail[n] = tegra124_cpufreq_rates[n].rate;
    127 	}
    128 
    129 	return nrates;
    130 }
    131 
    132 void
    133 tegra124_mpinit(void)
    134 {
    135 #if defined(MULTIPROCESSOR)
    136 	extern void cortex_mpstart(void);
    137 	bus_space_tag_t bst = &armv7_generic_bs_tag;
    138 	bus_space_handle_t bsh;
    139 
    140 	bus_space_subregion(bst, tegra_ppsb_bsh,
    141 	    TEGRA_EVP_OFFSET, TEGRA_EVP_SIZE, &bsh);
    142 
    143 	arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU);
    144 	KASSERT(arm_cpu_max == 4);
    145 
    146 	bus_space_write_4(bst, bsh, EVP_RESET_VECTOR_0_REG, (uint32_t)cortex_mpstart);
    147 	bus_space_barrier(bst, bsh, EVP_RESET_VECTOR_0_REG, 4,
    148 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
    149 	uint32_t started = 0;
    150 
    151 	tegra_pmc_power(PMC_PARTID_CPU1, true); started |= __BIT(1);
    152 	tegra_pmc_power(PMC_PARTID_CPU2, true); started |= __BIT(2);
    153 	tegra_pmc_power(PMC_PARTID_CPU3, true); started |= __BIT(3);
    154 
    155 	for (u_int i = 0x10000000; i > 0; i--) {
    156 		arm_dmb();
    157 		if (arm_cpu_hatched == started)
    158 			break;
    159 	}
    160 #endif
    161 }
    162