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tegra124_cpu.c revision 1.1.4.1 
      1 /* $NetBSD: tegra124_cpu.c,v 1.1.4.1 2017/05/02 03:19:16 pgoyette Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #include "opt_tegra.h"
     30 #include "opt_multiprocessor.h"
     31 
     32 #include <sys/cdefs.h>
     33 __KERNEL_RCSID(0, "$NetBSD: tegra124_cpu.c,v 1.1.4.1 2017/05/02 03:19:16 pgoyette Exp $");
     34 
     35 #include <sys/param.h>
     36 #include <sys/bus.h>
     37 #include <sys/cpu.h>
     38 #include <sys/device.h>
     39 
     40 #include <uvm/uvm_extern.h>
     41 
     42 #include <dev/fdt/fdtvar.h>
     43 
     44 #include <arm/cpufunc.h>
     45 
     46 #include <arm/nvidia/tegra_reg.h>
     47 #include <arm/nvidia/tegra_pmcreg.h>
     48 #include <arm/nvidia/tegra_var.h>
     49 
     50 
     51 #define FUSE_SKU_INFO_REG	0x010
     52 #define FUSE_CPU_SPEEDO_0_REG	0x014
     53 #define FUSE_CPU_IDDQ_REG	0x018
     54 #define FUSE_FT_REV_REG		0x028
     55 #define FUSE_CPU_SPEEDO_1_REG	0x02c
     56 #define FUSE_CPU_SPEEDO_2_REG	0x030
     57 #define FUSE_SOC_SPEEDO_0_REG	0x034
     58 #define FUSE_SOC_SPEEDO_1_REG	0x038
     59 #define FUSE_SOC_SPEEDO_2_REG	0x03c
     60 #define FUSE_SOC_IDDQ_REG	0x040
     61 #define FUSE_GPU_IDDQ_REG	0x128
     62 
     63 static void	tegra124_speedo_init(void);
     64 static int	tegra124_speedo_init_ids(uint32_t);
     65 static bool	tegra124_speedo_rate_ok(u_int);
     66 
     67 static u_int	tegra124_cpufreq_set_rate(u_int);
     68 static u_int	tegra124_cpufreq_get_rate(void);
     69 static size_t	tegra124_cpufreq_get_available(u_int *, size_t);
     70 
     71 static int	tegra124_cpu_match(device_t, cfdata_t, void *);
     72 static void	tegra124_cpu_attach(device_t, device_t, void *);
     73 static void	tegra124_cpu_init_cpufreq(device_t);
     74 
     75 CFATTACH_DECL_NEW(tegra124_cpu, 0, tegra124_cpu_match, tegra124_cpu_attach,
     76     NULL, NULL);
     77 
     78 static const struct tegra_cpufreq_func tegra124_cpufreq_func = {
     79 	.set_rate = tegra124_cpufreq_set_rate,
     80 	.get_rate = tegra124_cpufreq_get_rate,
     81 	.get_available = tegra124_cpufreq_get_available,
     82 };
     83 
     84 static struct tegra124_cpufreq_rate {
     85 	u_int rate;
     86 	u_int divm;
     87 	u_int divn;
     88 	u_int divp;
     89 	u_int uvol;
     90 } tegra124_cpufreq_rates[] = {
     91 	{ 2316, 1, 193, 0, 1360000 },
     92 	{ 2100, 1, 175, 0, 1260000 },
     93 	{ 1896, 1, 158, 0, 1180000 },
     94 	{ 1692, 1, 141, 0, 1100000 },
     95 	{ 1500, 1, 125, 0, 1020000 },
     96 	{ 1296, 1, 108, 0, 960000 },
     97 	{ 1092, 1, 91,  0, 900000 },
     98 	{ 900,  1, 75,  0, 840000 },
     99 	{ 696,  1, 58,  0, 800000 }
    100 };
    101 
    102 static const u_int tegra124_cpufreq_max[] = {
    103 	2014,
    104 	2320,
    105 	2116,
    106 	2524
    107 };
    108 
    109 static struct tegra124_speedo {
    110 	u_int cpu_speedo_id;
    111 	u_int soc_speedo_id;
    112 	u_int gpu_speedo_id;
    113 } tegra124_speedo = {
    114 	.cpu_speedo_id = 0,
    115 	.soc_speedo_id = 0,
    116 	.gpu_speedo_id = 0
    117 };
    118 
    119 static struct clk *tegra124_clk_pllx = NULL;
    120 static struct fdtbus_regulator *tegra124_reg_vddcpu = NULL;
    121 
    122 static int
    123 tegra124_cpu_match(device_t parent, cfdata_t cf, void *aux)
    124 {
    125 	const char * const compatible[] = { "nvidia,tegra124", NULL };
    126 	struct fdt_attach_args *faa = aux;
    127 
    128 	if (OF_finddevice("/cpus") != faa->faa_phandle)
    129 		return 0;
    130 
    131 	return of_match_compatible(OF_finddevice("/"), compatible);
    132 }
    133 
    134 static void
    135 tegra124_cpu_attach(device_t parent, device_t self, void *aux)
    136 {
    137 	aprint_naive("\n");
    138 	aprint_normal(": CPU complex\n");
    139 
    140 	config_defer(self, tegra124_cpu_init_cpufreq);
    141 }
    142 
    143 static void
    144 tegra124_cpu_init_cpufreq(device_t dev)
    145 {
    146 	tegra124_speedo_init();
    147 
    148 	int cpu_node = OF_finddevice("/cpus/cpu@0");
    149 	if (cpu_node != -1) {
    150 		tegra124_clk_pllx = fdtbus_clock_get(cpu_node, "pll_x");
    151 		tegra124_reg_vddcpu = fdtbus_regulator_acquire(cpu_node,
    152 		    "vdd-cpu-supply");
    153 	}
    154 	if (tegra124_clk_pllx == NULL) {
    155 		aprint_error_dev(dev, "couldn't find clock pll_x\n");
    156 		return;
    157 	}
    158 	if (tegra124_reg_vddcpu == NULL) {
    159 		aprint_error_dev(dev, "couldn't find voltage regulator\n");
    160 		return;
    161 	}
    162 
    163 	tegra_cpufreq_register(&tegra124_cpufreq_func);
    164 }
    165 
    166 static void
    167 tegra124_speedo_init(void)
    168 {
    169 	uint32_t sku_id;
    170 
    171 	sku_id = tegra_fuse_read(FUSE_SKU_INFO_REG);
    172 	tegra124_speedo_init_ids(sku_id);
    173 }
    174 
    175 static int
    176 tegra124_speedo_init_ids(uint32_t sku_id)
    177 {
    178 	int threshold = 0;
    179 
    180 	switch (sku_id) {
    181 	case 0x00:
    182 	case 0x0f:
    183 	case 0x23:
    184 		break;	/* use default */
    185 	case 0x83:
    186 		tegra124_speedo.cpu_speedo_id = 2;
    187 		break;
    188 	case 0x1f:
    189 	case 0x87:
    190 	case 0x27:
    191 		tegra124_speedo.cpu_speedo_id = 2;
    192 		tegra124_speedo.soc_speedo_id = 0;
    193 		tegra124_speedo.gpu_speedo_id = 1;
    194 		break;
    195 	case 0x81:
    196 	case 0x21:
    197 	case 0x07:
    198 		tegra124_speedo.cpu_speedo_id = 1;
    199 		tegra124_speedo.soc_speedo_id = 1;
    200 		tegra124_speedo.gpu_speedo_id = 1;
    201 		threshold = 1;
    202 		break;
    203 	case 0x49:
    204 	case 0x4a:
    205 	case 0x48:
    206 		tegra124_speedo.cpu_speedo_id = 4;
    207 		tegra124_speedo.soc_speedo_id = 2;
    208 		tegra124_speedo.gpu_speedo_id = 3;
    209 		threshold = 1;
    210 		break;
    211 	default:
    212 		aprint_error("tegra124: unknown SKU ID %#x\n", sku_id);
    213 		break;	/* use default */
    214 	}
    215 
    216 	return threshold;
    217 }
    218 
    219 static bool
    220 tegra124_speedo_rate_ok(u_int rate)
    221 {
    222 	u_int tbl = 0;
    223 
    224 	if (tegra124_speedo.cpu_speedo_id < __arraycount(tegra124_cpufreq_max))
    225 		tbl = tegra124_speedo.cpu_speedo_id;
    226 
    227 	return rate <= tegra124_cpufreq_max[tbl];
    228 }
    229 
    230 
    231 static u_int
    232 tegra124_cpufreq_set_rate(u_int rate)
    233 {
    234 	const u_int nrates = __arraycount(tegra124_cpufreq_rates);
    235 	const struct tegra124_cpufreq_rate *r = NULL;
    236 	CPU_INFO_ITERATOR cii;
    237 	struct cpu_info *ci;
    238 	u_int cur_uvol;
    239 	int error;
    240 
    241 	if (tegra124_speedo_rate_ok(rate) == false)
    242 		return EINVAL;
    243 
    244 	for (int i = 0; i < nrates; i++) {
    245 		if (tegra124_cpufreq_rates[i].rate == rate) {
    246 			r = &tegra124_cpufreq_rates[i];
    247 			break;
    248 		}
    249 	}
    250 	if (r == NULL)
    251 		return EINVAL;
    252 
    253 	error = fdtbus_regulator_get_voltage(tegra124_reg_vddcpu, &cur_uvol);
    254 	if (error != 0)
    255 		return error;
    256 
    257 	if (cur_uvol < r->uvol) {
    258 		error = fdtbus_regulator_set_voltage(tegra124_reg_vddcpu,
    259 		    r->uvol, r->uvol);
    260 		if (error != 0)
    261 			return error;
    262 	}
    263 
    264 	error = clk_set_rate(tegra124_clk_pllx, r->rate * 1000000);
    265 	if (error == 0) {
    266 		rate = tegra124_cpufreq_get_rate();
    267 		for (CPU_INFO_FOREACH(cii, ci)) {
    268 			ci->ci_data.cpu_cc_freq = rate * 1000000;
    269 		}
    270 	}
    271 
    272 	if (cur_uvol > r->uvol) {
    273 		(void)fdtbus_regulator_set_voltage(tegra124_reg_vddcpu,
    274 		    r->uvol, r->uvol);
    275 	}
    276 
    277 	return error;
    278 }
    279 
    280 static u_int
    281 tegra124_cpufreq_get_rate(void)
    282 {
    283 	return clk_get_rate(tegra124_clk_pllx) / 1000000;
    284 }
    285 
    286 static size_t
    287 tegra124_cpufreq_get_available(u_int *pavail, size_t maxavail)
    288 {
    289 	const u_int nrates = __arraycount(tegra124_cpufreq_rates);
    290 	u_int n, cnt;
    291 
    292 	KASSERT(nrates <= maxavail);
    293 
    294 	for (n = 0, cnt = 0; n < nrates; n++) {
    295 		if (tegra124_speedo_rate_ok(tegra124_cpufreq_rates[n].rate)) {
    296 			pavail[cnt++] = tegra124_cpufreq_rates[n].rate;
    297 		}
    298 	}
    299 
    300 	return cnt;
    301 }
    302