tegra210_xusbpad.c revision 1.1
1 /* $NetBSD: tegra210_xusbpad.c,v 1.1 2017/09/19 23:18:01 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra210_xusbpad.c,v 1.1 2017/09/19 23:18:01 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <arm/nvidia/tegra_reg.h> 40 #include <arm/nvidia/tegra_var.h> 41 #include <arm/nvidia/tegra_xusbpad.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 struct tegra210_xusbpad_softc { 46 device_t sc_dev; 47 int sc_phandle; 48 bus_space_tag_t sc_bst; 49 bus_space_handle_t sc_bsh; 50 51 struct fdtbus_reset *sc_rst; 52 }; 53 54 #define RD4(sc, reg) \ 55 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 56 #define WR4(sc, reg, val) \ 57 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 58 #define SETCLR4(sc, reg, set, clr) \ 59 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr)) 60 61 static const char * tegra210_xusbpad_usb2_func[] = { "snps", "xusb", "uart" }; 62 static const char * tegra210_xusbpad_hsic_func[] = { "snps", "xusb" }; 63 static const char * tegra210_xusbpad_pcie_func[] = { "pcie-x1", "usb3-ss", "sata", "pcie-x4" }; 64 65 #define XUSBPAD_LANE(n, r, m, f) \ 66 { \ 67 .name = (n), \ 68 .reg = (r), \ 69 .mask = (m), \ 70 .funcs = (f), \ 71 .nfuncs = __arraycount(f) \ 72 } 73 74 static const struct tegra210_xusbpad_lane { 75 const char *name; 76 bus_size_t reg; 77 uint32_t mask; 78 const char **funcs; 79 int nfuncs; 80 } tegra210_xusbpad_lanes[] = { 81 XUSBPAD_LANE("usb2-0", 0x04, __BITS(1,0), tegra210_xusbpad_usb2_func), 82 XUSBPAD_LANE("usb2-1", 0x04, __BITS(3,2), tegra210_xusbpad_usb2_func), 83 XUSBPAD_LANE("usb2-2", 0x04, __BITS(5,4), tegra210_xusbpad_usb2_func), 84 XUSBPAD_LANE("usb2-3", 0x04, __BITS(7,6), tegra210_xusbpad_usb2_func), 85 86 XUSBPAD_LANE("hsic-0", 0x04, __BIT(14), tegra210_xusbpad_hsic_func), 87 XUSBPAD_LANE("hsic-1", 0x04, __BIT(15), tegra210_xusbpad_hsic_func), 88 89 XUSBPAD_LANE("pcie-0", 0x28, __BITS(13,12), tegra210_xusbpad_pcie_func), 90 XUSBPAD_LANE("pcie-1", 0x28, __BITS(15,14), tegra210_xusbpad_pcie_func), 91 XUSBPAD_LANE("pcie-2", 0x28, __BITS(17,16), tegra210_xusbpad_pcie_func), 92 XUSBPAD_LANE("pcie-3", 0x28, __BITS(19,18), tegra210_xusbpad_pcie_func), 93 XUSBPAD_LANE("pcie-4", 0x28, __BITS(21,20), tegra210_xusbpad_pcie_func), 94 XUSBPAD_LANE("pcie-5", 0x28, __BITS(23,22), tegra210_xusbpad_pcie_func), 95 XUSBPAD_LANE("pcie-6", 0x28, __BITS(25,24), tegra210_xusbpad_pcie_func), 96 97 XUSBPAD_LANE("sata-0", 0x28, __BITS(31,30), tegra210_xusbpad_pcie_func), 98 }; 99 100 static int 101 tegra210_xusbpad_find_func(const struct tegra210_xusbpad_lane *lane, 102 const char *func) 103 { 104 for (int n = 0; n < lane->nfuncs; n++) 105 if (strcmp(lane->funcs[n], func) == 0) 106 return n; 107 return -1; 108 } 109 110 static const struct tegra210_xusbpad_lane * 111 tegra210_xusbpad_find_lane(const char *name) 112 { 113 for (int n = 0; n < __arraycount(tegra210_xusbpad_lanes); n++) 114 if (strcmp(tegra210_xusbpad_lanes[n].name, name) == 0) 115 return &tegra210_xusbpad_lanes[n]; 116 return NULL; 117 } 118 119 static void 120 tegra210_xusbpad_configure_lane(struct tegra210_xusbpad_softc *sc, 121 int phandle) 122 { 123 const struct tegra210_xusbpad_lane *lane; 124 const char *name, *function; 125 int func; 126 127 name = fdtbus_get_string(phandle, "name"); 128 if (name == NULL) { 129 aprint_error_dev(sc->sc_dev, "no 'name' property\n"); 130 return; 131 } 132 function = fdtbus_get_string(phandle, "nvidia,function"); 133 if (function == NULL) { 134 aprint_error_dev(sc->sc_dev, "no 'nvidia,function' property\n"); 135 return; 136 } 137 138 lane = tegra210_xusbpad_find_lane(name); 139 if (lane == NULL) { 140 aprint_error_dev(sc->sc_dev, "unsupported lane '%s'\n", name); 141 return; 142 } 143 func = tegra210_xusbpad_find_func(lane, function); 144 if (func == -1) { 145 aprint_error_dev(sc->sc_dev, "unsupported function '%s'\n", function); 146 return; 147 } 148 149 aprint_debug_dev(sc->sc_dev, "[%s] set func %s\n", name, function); 150 SETCLR4(sc, lane->reg, __SHIFTIN(func, lane->mask), lane->mask); 151 } 152 153 static void 154 tegra210_xusbpad_configure_pads(struct tegra210_xusbpad_softc *sc, 155 const char *name) 156 { 157 struct fdtbus_reset *rst; 158 struct clk *clk; 159 int phandle, child; 160 161 /* Search for the pad's node */ 162 phandle = of_find_firstchild_byname(sc->sc_phandle, "pads"); 163 if (phandle == -1) { 164 aprint_error_dev(sc->sc_dev, "no 'pads' node\n"); 165 return; 166 } 167 phandle = of_find_firstchild_byname(phandle, name); 168 if (phandle == -1) { 169 aprint_error_dev(sc->sc_dev, "no 'pads/%s' node\n", name); 170 return; 171 } 172 173 if (!fdtbus_status_okay(phandle)) 174 return; /* pad is disabled */ 175 176 /* Enable the pad's resources */ 177 clk = fdtbus_clock_get_index(phandle, 0); 178 if (clk && clk_enable(clk) != 0) { 179 aprint_error_dev(sc->sc_dev, "couldn't enable %s's clock\n", name); 180 return; 181 } 182 rst = fdtbus_reset_get_index(phandle, 0); 183 if (rst && fdtbus_reset_deassert(rst) != 0) { 184 aprint_error_dev(sc->sc_dev, "couldn't de-assert %s's reset\n", name); 185 return; 186 } 187 188 /* Configure lanes */ 189 phandle = of_find_firstchild_byname(phandle, "lanes"); 190 if (phandle == -1) { 191 aprint_error_dev(sc->sc_dev, "no 'pads/%s/lanes' node\n", name); 192 return; 193 } 194 for (child = OF_child(phandle); child; child = OF_peer(child)) { 195 if (!fdtbus_status_okay(child)) 196 continue; 197 tegra210_xusbpad_configure_lane(sc, child); 198 } 199 } 200 201 static void 202 tegra210_xusbpad_sata_enable(device_t dev) 203 { 204 } 205 206 static void 207 tegra210_xusbpad_xhci_enable(device_t dev) 208 { 209 } 210 211 static const struct tegra_xusbpad_ops tegra210_xusbpad_ops = { 212 .sata_enable = tegra210_xusbpad_sata_enable, 213 .xhci_enable = tegra210_xusbpad_xhci_enable, 214 }; 215 216 static int 217 tegra210_xusbpad_match(device_t parent, cfdata_t cf, void *aux) 218 { 219 const char * const compatible[] = { 220 "nvidia,tegra210-xusb-padctl", 221 NULL 222 }; 223 struct fdt_attach_args * const faa = aux; 224 225 return of_match_compatible(faa->faa_phandle, compatible); 226 } 227 228 static void 229 tegra210_xusbpad_attach(device_t parent, device_t self, void *aux) 230 { 231 struct tegra210_xusbpad_softc * const sc = device_private(self); 232 struct fdt_attach_args * const faa = aux; 233 bus_addr_t addr; 234 bus_size_t size; 235 int error; 236 237 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 238 aprint_error(": couldn't get registers\n"); 239 return; 240 } 241 sc->sc_rst = fdtbus_reset_get(faa->faa_phandle, "padctl"); 242 if (sc->sc_rst == NULL) { 243 aprint_error(": couldn't get reset padctl\n"); 244 return; 245 } 246 247 sc->sc_dev = self; 248 sc->sc_phandle = faa->faa_phandle; 249 sc->sc_bst = faa->faa_bst; 250 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 251 if (error) { 252 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 253 return; 254 } 255 256 aprint_naive("\n"); 257 aprint_normal(": XUSB PADCTL\n"); 258 259 fdtbus_reset_deassert(sc->sc_rst); 260 261 tegra_xusbpad_register(self, &tegra210_xusbpad_ops); 262 263 tegra210_xusbpad_configure_pads(sc, "usb2"); 264 tegra210_xusbpad_configure_pads(sc, "hsic"); 265 tegra210_xusbpad_configure_pads(sc, "pcie"); 266 tegra210_xusbpad_configure_pads(sc, "sata"); 267 } 268 269 CFATTACH_DECL_NEW(tegra210_xusbpad, sizeof(struct tegra210_xusbpad_softc), 270 tegra210_xusbpad_match, tegra210_xusbpad_attach, NULL, NULL); 271
Indexes created Tue Sep 30 20:09:53 GMT 2025