tegra210_xusbpad.c revision 1.6
1 /* $NetBSD: tegra210_xusbpad.c,v 1.6 2017/09/24 20:09:53 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra210_xusbpad.c,v 1.6 2017/09/24 20:09:53 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <arm/nvidia/tegra_reg.h> 40 #include <arm/nvidia/tegra_var.h> 41 #include <arm/nvidia/tegra_xusbpad.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 #define XUSB_PADCTL_USB2_PAD_MUX_REG 0x04 46 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD __BITS(19,18) 47 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB 1 48 49 #define XUSB_PADCTL_VBUS_OC_MAP_REG 0x18 50 #define XUSB_PADCTL_VBUS_OC_MAP_VBUS_ENABLE(n) __BIT((n) * 5) 51 52 #define XUSB_PADCTL_OC_DET_REG 0x1c 53 #define XUSB_PADCTL_OC_DET_OC_DETECTED_VBUS_PAD(n) __BIT(12 + (n)) 54 #define XUSB_PADCTL_OC_DET_OC_DETECTED(n) __BIT(8 + (n)) 55 #define XUSB_PADCTL_OC_DET_SET_OC_DETECTED(n) __BIT(0 + (n)) 56 57 #define XUSB_PADCTL_ELPG_PROGRAM_1_REG 0x24 58 #define XUSB_PADCTL_ELPG_PROGRAM_1_AUX_MUX_LP0_VCORE_DOWN __BIT(31) 59 #define XUSB_PADCTL_ELPG_PROGRAM_1_AUX_MUX_LP0_CLAMP_EN_EARLY __BIT(30) 60 #define XUSB_PADCTL_ELPG_PROGRAM_1_AUX_MUX_LP0_CLAMP_EN __BIT(29) 61 #define XUSB_PADCTL_ELPG_PROGRAM_1_SSPn_ELPG_VCORE_DOWN(n) __BIT((n) * 3 + 2) 62 #define XUSB_PADCTL_ELPG_PROGRAM_1_SSPn_ELPG_CLAMP_EN_EARLY(n) __BIT((n) * 3 + 1) 63 #define XUSB_PADCTL_ELPG_PROGRAM_1_SSPn_ELPG_CLAMP_EN(n) __BIT((n) * 3 + 0) 64 65 #define XUSB_PADCTL_USB3_PAD_MUX_REG 0x28 66 #define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE __BIT(8) 67 #define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE(n) __BIT(1 + (n)) 68 69 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG 0x360 70 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_PSDIV __BITS(29,28) 71 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_NDIV __BITS(27,20) 72 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_MDIV __BITS(17,16) 73 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_LOCKDET_STATUS __BIT(15) 74 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_PWR_OVRD __BIT(4) 75 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_ENABLE __BIT(3) 76 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_SLEEP __BITS(2,1) 77 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_IDDQ __BIT(0) 78 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG 0x364 79 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_CTRL __BITS(27,4) 80 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_OVRD __BIT(2) 81 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_DONE __BIT(1) 82 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_EN __BIT(0) 83 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_3_REG 0x368 84 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REG 0x36c 85 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_TXCLKREF_EN __BIT(15) 86 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_TXCLKREF_SEL __BITS(13,12) 87 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REFCLKBUF_EN __BIT(8) 88 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REFCLK_SEL __BITS(7,4) 89 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_5_REG 0x370 90 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_5_DCO_CTRL __BITS(23,16) 91 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_6_REG 0x374 92 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_7_REG 0x378 93 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG 0x37c 94 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_DONE __BIT(31) 95 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_OVRD __BIT(15) 96 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_CLK_EN __BIT(13) 97 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_EN __BIT(12) 98 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_9_REG 0x380 99 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_10_REG 0x384 100 #define XUSB_PADCTL_UPHY_PLL_P0_CTL_11_REG 0x388 101 102 #define XUSB_PADCTL_UPHY_USB3_PADn_ECTL_1_REG(n) (0xa60 + (n) * 0x40) 103 #define XUSB_PADCTL_UPHY_USB3_PADn_ECTL_2_TX_TERM_CTRL __BITS(19,18) 104 105 #define XUSB_PADCTL_UPHY_USB3_PADn_ECTL_2_REG(n) (0xa64 + (n) * 0x40) 106 #define XUSB_PADCTL_UPHY_USB3_PADn_ECTL_2_RX_CTLE __BITS(15,0) 107 108 #define XUSB_PADCTL_UPHY_USB3_PADn_ECTL_3_REG(n) (0xa68 + (n) * 0x40) 109 110 #define XUSB_PADCTL_UPHY_USB3_PADn_ECTL_4_REG(n) (0xa6c + (n) * 0x40) 111 #define XUSB_PADCTL_UPHY_USB3_PADn_ECTL_4_RX_CDR_CTRL __BITS(31,16) 112 113 #define XUSB_PADCTL_UPHY_USB3_PADn_ECTL_6_REG(n) (0xa74 + (n) * 0x40) 114 115 struct tegra210_xusbpad_softc { 116 device_t sc_dev; 117 int sc_phandle; 118 bus_space_tag_t sc_bst; 119 bus_space_handle_t sc_bsh; 120 121 struct fdtbus_reset *sc_rst; 122 123 bool sc_enabled; 124 }; 125 126 #define RD4(sc, reg) \ 127 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 128 #define WR4(sc, reg, val) \ 129 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 130 #define SETCLR4(sc, reg, set, clr) \ 131 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr)) 132 133 static const char * tegra210_xusbpad_usb2_func[] = { "snps", "xusb", "uart" }; 134 static const char * tegra210_xusbpad_hsic_func[] = { "snps", "xusb" }; 135 static const char * tegra210_xusbpad_pcie_func[] = { "pcie-x1", "usb3-ss", "sata", "pcie-x4" }; 136 137 static void 138 tegra210_xusbpad_uphy_enable_pcie(struct tegra210_xusbpad_softc *sc) 139 { 140 uint32_t val; 141 int retry; 142 143 /* UPHY PLLs */ 144 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG, 145 __SHIFTIN(0x136, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_CTRL), 146 XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_CTRL); 147 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_5_REG, 148 __SHIFTIN(0x2a, XUSB_PADCTL_UPHY_PLL_P0_CTL_5_DCO_CTRL), 149 XUSB_PADCTL_UPHY_PLL_P0_CTL_5_DCO_CTRL); 150 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG, 151 XUSB_PADCTL_UPHY_PLL_P0_CTL_1_PWR_OVRD, 0); 152 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG, 153 XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_OVRD, 0); 154 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG, 155 XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_OVRD, 0); 156 157 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REG, 158 __SHIFTIN(0, XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REFCLK_SEL), 159 XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REFCLK_SEL); 160 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REG, 161 __SHIFTIN(2, XUSB_PADCTL_UPHY_PLL_P0_CTL_4_TXCLKREF_SEL), 162 XUSB_PADCTL_UPHY_PLL_P0_CTL_4_TXCLKREF_SEL); 163 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REG, 164 XUSB_PADCTL_UPHY_PLL_P0_CTL_4_TXCLKREF_EN, 0); 165 166 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG, 167 __SHIFTIN(0, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_MDIV), 168 XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_MDIV); 169 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG, 170 __SHIFTIN(0x19, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_NDIV), 171 XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_NDIV); 172 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG, 173 __SHIFTIN(0, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_PSDIV), 174 XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_PSDIV); 175 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG, 176 0, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_IDDQ); 177 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG, 178 0, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_SLEEP); 179 180 delay(20); 181 182 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REG, 183 XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REFCLKBUF_EN, 0); 184 185 /* Calibration */ 186 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG, 187 XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_EN, 0); 188 for (retry = 10000; retry > 0; retry--) { 189 delay(2); 190 val = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG); 191 if ((val & XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_DONE) != 0) 192 break; 193 } 194 if (retry == 0) { 195 aprint_error_dev(sc->sc_dev, "timeout calibrating UPHY PLL (1)\n"); 196 return; 197 } 198 199 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG, 200 0, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_EN); 201 for (retry = 10000; retry > 0; retry--) { 202 delay(2); 203 val = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG); 204 if ((val & XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_DONE) == 0) 205 break; 206 } 207 if (retry == 0) { 208 aprint_error_dev(sc->sc_dev, "timeout calibrating UPHY PLL (2)\n"); 209 return; 210 } 211 212 /* Enable the PLL */ 213 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG, 214 XUSB_PADCTL_UPHY_PLL_P0_CTL_1_ENABLE, 0); 215 for (retry = 10000; retry > 0; retry--) { 216 delay(2); 217 val = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG); 218 if ((val & XUSB_PADCTL_UPHY_PLL_P0_CTL_1_LOCKDET_STATUS) != 0) 219 break; 220 } 221 if (retry == 0) { 222 aprint_error_dev(sc->sc_dev, "timeout enabling UPHY PLL\n"); 223 return; 224 } 225 226 /* RCAL */ 227 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG, 228 XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_EN, 0); 229 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG, 230 XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_CLK_EN, 0); 231 for (retry = 10000; retry > 0; retry--) { 232 delay(2); 233 val = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG); 234 if ((val & XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_DONE) != 0) 235 break; 236 } 237 if (retry == 0) { 238 aprint_error_dev(sc->sc_dev, "timeout calibrating UPHY PLL (3)\n"); 239 return; 240 } 241 242 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG, 243 0, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_EN); 244 for (retry = 10000; retry > 0; retry--) { 245 delay(2); 246 val = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG); 247 if ((val & XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_DONE) == 0) 248 break; 249 } 250 if (retry == 0) { 251 aprint_error_dev(sc->sc_dev, "timeout calibrating UPHY PLL (4)\n"); 252 return; 253 } 254 255 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG, 256 0, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_CLK_EN); 257 258 tegra210_car_xusbio_enable_hw_control(); 259 260 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG, 261 0, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_PWR_OVRD); 262 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG, 263 0, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_OVRD); 264 SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG, 265 0, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_RCAL_OVRD); 266 267 delay(1); 268 269 tegra210_car_xusbio_enable_hw_seq(); 270 } 271 272 static void 273 tegra210_xusbpad_lane_enable_pcie(struct tegra210_xusbpad_softc *sc, int index) 274 { 275 tegra210_xusbpad_uphy_enable_pcie(sc); 276 277 SETCLR4(sc, XUSB_PADCTL_USB3_PAD_MUX_REG, 278 XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE(index), 0); 279 } 280 281 #define XUSBPAD_LANE(n, i, r, m, f, ef) \ 282 { \ 283 .name = (n), \ 284 .index = (i), \ 285 .reg = (r), \ 286 .mask = (m), \ 287 .funcs = (f), \ 288 .nfuncs = __arraycount(f), \ 289 .enable = (ef) \ 290 } 291 292 static const struct tegra210_xusbpad_lane { 293 const char *name; 294 int index; 295 bus_size_t reg; 296 uint32_t mask; 297 const char **funcs; 298 int nfuncs; 299 void (*enable)(struct tegra210_xusbpad_softc *, int); 300 } tegra210_xusbpad_lanes[] = { 301 XUSBPAD_LANE("usb2-0", 0, 0x04, __BITS(1,0), tegra210_xusbpad_usb2_func, 302 NULL), 303 XUSBPAD_LANE("usb2-1", 1, 0x04, __BITS(3,2), tegra210_xusbpad_usb2_func, 304 NULL), 305 XUSBPAD_LANE("usb2-2", 2, 0x04, __BITS(5,4), tegra210_xusbpad_usb2_func, 306 NULL), 307 XUSBPAD_LANE("usb2-3", 3, 0x04, __BITS(7,6), tegra210_xusbpad_usb2_func, 308 NULL), 309 310 XUSBPAD_LANE("hsic-0", 0, 0x04, __BIT(14), tegra210_xusbpad_hsic_func, 311 NULL), 312 XUSBPAD_LANE("hsic-1", 1, 0x04, __BIT(15), tegra210_xusbpad_hsic_func, 313 NULL), 314 315 XUSBPAD_LANE("pcie-0", 0, 0x28, __BITS(13,12), tegra210_xusbpad_pcie_func, 316 tegra210_xusbpad_lane_enable_pcie), 317 XUSBPAD_LANE("pcie-1", 1, 0x28, __BITS(15,14), tegra210_xusbpad_pcie_func, 318 tegra210_xusbpad_lane_enable_pcie), 319 XUSBPAD_LANE("pcie-2", 2, 0x28, __BITS(17,16), tegra210_xusbpad_pcie_func, 320 tegra210_xusbpad_lane_enable_pcie), 321 XUSBPAD_LANE("pcie-3", 3, 0x28, __BITS(19,18), tegra210_xusbpad_pcie_func, 322 tegra210_xusbpad_lane_enable_pcie), 323 XUSBPAD_LANE("pcie-4", 4, 0x28, __BITS(21,20), tegra210_xusbpad_pcie_func, 324 tegra210_xusbpad_lane_enable_pcie), 325 XUSBPAD_LANE("pcie-5", 5, 0x28, __BITS(23,22), tegra210_xusbpad_pcie_func, 326 tegra210_xusbpad_lane_enable_pcie), 327 XUSBPAD_LANE("pcie-6", 6, 0x28, __BITS(25,24), tegra210_xusbpad_pcie_func, 328 tegra210_xusbpad_lane_enable_pcie), 329 330 XUSBPAD_LANE("sata-0", 0, 0x28, __BITS(31,30), tegra210_xusbpad_pcie_func, 331 NULL), 332 }; 333 334 #define XUSBPAD_PORT(n, i, r, m, im) \ 335 { \ 336 .name = (n), \ 337 .index = (i), \ 338 .reg = (r), \ 339 .mask = (m), \ 340 .internal_mask = (im) \ 341 } 342 343 struct tegra210_xusbpad_port { 344 const char *name; 345 int index; 346 bus_size_t reg; 347 uint32_t mask; 348 uint32_t internal_mask; 349 }; 350 351 static const struct tegra210_xusbpad_port tegra210_xusbpad_usb2_ports[] = { 352 XUSBPAD_PORT("usb2-0", 0, 0x08, __BITS(1,0), __BIT(2)), 353 XUSBPAD_PORT("usb2-1", 1, 0x08, __BITS(5,4), __BIT(6)), 354 XUSBPAD_PORT("usb2-2", 2, 0x08, __BITS(9,8), __BIT(10)), 355 XUSBPAD_PORT("usb2-3", 3, 0x08, __BITS(13,12), __BIT(14)), 356 }; 357 358 static const struct tegra210_xusbpad_port tegra210_xusbpad_usb3_ports[] = { 359 XUSBPAD_PORT("usb3-0", 0, 0x14, __BITS(3,0), __BIT(4)), 360 XUSBPAD_PORT("usb3-1", 1, 0x14, __BITS(8,5), __BIT(9)), 361 XUSBPAD_PORT("usb3-2", 2, 0x14, __BITS(13,10), __BIT(14)), 362 XUSBPAD_PORT("usb3-3", 3, 0x14, __BITS(18,15), __BIT(19)), 363 }; 364 365 static const struct tegra210_xusbpad_port tegra210_xusbpad_hsic_ports[] = { 366 XUSBPAD_PORT("hsic-0", 0, 0, 0, 0), 367 XUSBPAD_PORT("hsic-1", 1, 0, 0, 0), 368 }; 369 370 static int 371 tegra210_xusbpad_find_func(const struct tegra210_xusbpad_lane *lane, 372 const char *func) 373 { 374 for (int n = 0; n < lane->nfuncs; n++) 375 if (strcmp(lane->funcs[n], func) == 0) 376 return n; 377 return -1; 378 } 379 380 static const struct tegra210_xusbpad_lane * 381 tegra210_xusbpad_find_lane(const char *name) 382 { 383 for (int n = 0; n < __arraycount(tegra210_xusbpad_lanes); n++) 384 if (strcmp(tegra210_xusbpad_lanes[n].name, name) == 0) 385 return &tegra210_xusbpad_lanes[n]; 386 return NULL; 387 } 388 389 static void 390 tegra210_xusbpad_configure_lane(struct tegra210_xusbpad_softc *sc, 391 int phandle) 392 { 393 const struct tegra210_xusbpad_lane *lane; 394 const char *name, *function; 395 int func; 396 397 name = fdtbus_get_string(phandle, "name"); 398 if (name == NULL) { 399 aprint_error_dev(sc->sc_dev, "no 'name' property\n"); 400 return; 401 } 402 function = fdtbus_get_string(phandle, "nvidia,function"); 403 if (function == NULL) { 404 aprint_error_dev(sc->sc_dev, "no 'nvidia,function' property\n"); 405 return; 406 } 407 408 lane = tegra210_xusbpad_find_lane(name); 409 if (lane == NULL) { 410 aprint_error_dev(sc->sc_dev, "unsupported lane '%s'\n", name); 411 return; 412 } 413 func = tegra210_xusbpad_find_func(lane, function); 414 if (func == -1) { 415 aprint_error_dev(sc->sc_dev, "unsupported function '%s'\n", function); 416 return; 417 } 418 419 aprint_normal_dev(sc->sc_dev, "lane %s: set func %s\n", name, function); 420 SETCLR4(sc, lane->reg, __SHIFTIN(func, lane->mask), lane->mask); 421 422 if (lane->enable) 423 lane->enable(sc, lane->index); 424 } 425 426 static void 427 tegra210_xusbpad_configure_pads(struct tegra210_xusbpad_softc *sc, 428 const char *name) 429 { 430 struct fdtbus_reset *rst; 431 struct clk *clk; 432 int phandle, child; 433 434 /* Search for the pad's node */ 435 phandle = of_find_firstchild_byname(sc->sc_phandle, "pads"); 436 if (phandle == -1) { 437 aprint_error_dev(sc->sc_dev, "no 'pads' node\n"); 438 return; 439 } 440 phandle = of_find_firstchild_byname(phandle, name); 441 if (phandle == -1) { 442 aprint_error_dev(sc->sc_dev, "no 'pads/%s' node\n", name); 443 return; 444 } 445 446 if (!fdtbus_status_okay(phandle)) 447 return; /* pad is disabled */ 448 449 /* Enable the pad's resources */ 450 if (of_hasprop(phandle, "clocks")) { 451 clk = fdtbus_clock_get_index(phandle, 0); 452 if (clk == NULL || clk_enable(clk) != 0) { 453 aprint_error_dev(sc->sc_dev, "couldn't enable %s's clock\n", name); 454 return; 455 } 456 } 457 if (of_hasprop(phandle, "resets")) { 458 rst = fdtbus_reset_get_index(phandle, 0); 459 if (rst == NULL || fdtbus_reset_deassert(rst) != 0) { 460 aprint_error_dev(sc->sc_dev, "couldn't de-assert %s's reset\n", name); 461 return; 462 } 463 } 464 465 /* Configure lanes */ 466 phandle = of_find_firstchild_byname(phandle, "lanes"); 467 if (phandle == -1) { 468 aprint_error_dev(sc->sc_dev, "no 'pads/%s/lanes' node\n", name); 469 return; 470 } 471 for (child = OF_child(phandle); child; child = OF_peer(child)) { 472 if (!fdtbus_status_okay(child)) 473 continue; 474 tegra210_xusbpad_configure_lane(sc, child); 475 } 476 } 477 478 static const struct tegra210_xusbpad_port * 479 tegra210_xusbpad_find_port(const char *name, const struct tegra210_xusbpad_port *ports, 480 int nports) 481 { 482 for (int n = 0; n < nports; n++) 483 if (strcmp(name, ports[n].name) == 0) 484 return &ports[n]; 485 return NULL; 486 } 487 488 static const struct tegra210_xusbpad_port * 489 tegra210_xusbpad_find_usb2_port(const char *name) 490 { 491 return tegra210_xusbpad_find_port(name, tegra210_xusbpad_usb2_ports, 492 __arraycount(tegra210_xusbpad_usb2_ports)); 493 } 494 495 static const struct tegra210_xusbpad_port * 496 tegra210_xusbpad_find_usb3_port(const char *name) 497 { 498 return tegra210_xusbpad_find_port(name, tegra210_xusbpad_usb3_ports, 499 __arraycount(tegra210_xusbpad_usb3_ports)); 500 } 501 502 static const struct tegra210_xusbpad_port * 503 tegra210_xusbpad_find_hsic_port(const char *name) 504 { 505 return tegra210_xusbpad_find_port(name, tegra210_xusbpad_hsic_ports, 506 __arraycount(tegra210_xusbpad_hsic_ports)); 507 } 508 509 static void 510 tegra210_xusbpad_enable_vbus(struct tegra210_xusbpad_softc *sc, 511 const struct tegra210_xusbpad_port *port, int phandle) 512 { 513 struct fdtbus_regulator *vbus_reg; 514 515 if (!of_hasprop(phandle, "vbus-supply")) 516 return; 517 518 vbus_reg = fdtbus_regulator_acquire(phandle, "vbus-supply"); 519 if (vbus_reg == NULL || fdtbus_regulator_enable(vbus_reg) != 0) { 520 aprint_error_dev(sc->sc_dev, 521 "couldn't enable vbus regulator for port %s\n", 522 port->name); 523 } 524 } 525 526 static void 527 tegra210_xusbpad_configure_usb2_port(struct tegra210_xusbpad_softc *sc, 528 int phandle, const struct tegra210_xusbpad_port *port) 529 { 530 u_int modeval, internal; 531 const char *mode; 532 533 mode = fdtbus_get_string(phandle, "mode"); 534 if (mode == NULL) { 535 aprint_error_dev(sc->sc_dev, "no 'mode' property on port %s\n", port->name); 536 return; 537 } 538 if (strcmp(mode, "host") == 0) 539 modeval = 1; 540 else if (strcmp(mode, "device") == 0) 541 modeval = 2; 542 else if (strcmp(mode, "otg") == 0) 543 modeval = 3; 544 else { 545 aprint_error_dev(sc->sc_dev, "unsupported mode '%s' on port %s\n", mode, port->name); 546 return; 547 } 548 549 internal = of_hasprop(phandle, "nvidia,internal"); 550 551 tegra210_xusbpad_enable_vbus(sc, port, phandle); 552 553 aprint_normal_dev(sc->sc_dev, "port %s: set mode %s, %s\n", port->name, mode, 554 internal ? "internal" : "external"); 555 SETCLR4(sc, port->reg, __SHIFTIN(internal, port->internal_mask), port->internal_mask); 556 SETCLR4(sc, port->reg, __SHIFTIN(modeval, port->mask), port->mask); 557 } 558 559 static void 560 tegra210_xusbpad_configure_usb3_port(struct tegra210_xusbpad_softc *sc, 561 int phandle, const struct tegra210_xusbpad_port *port) 562 { 563 u_int companion, internal; 564 565 if (of_getprop_uint32(phandle, "nvidia,usb2-companion", &companion)) { 566 aprint_error_dev(sc->sc_dev, "no 'nvidia,usb2-companion' property on port %s\n", port->name); 567 return; 568 } 569 internal = of_hasprop(phandle, "nvidia,internal"); 570 571 tegra210_xusbpad_enable_vbus(sc, port, phandle); 572 573 aprint_normal_dev(sc->sc_dev, "port %s: set companion usb2-%d, %s\n", port->name, 574 companion, internal ? "internal" : "external"); 575 SETCLR4(sc, port->reg, __SHIFTIN(internal, port->internal_mask), port->internal_mask); 576 SETCLR4(sc, port->reg, __SHIFTIN(companion, port->mask), port->mask); 577 578 SETCLR4(sc, XUSB_PADCTL_UPHY_USB3_PADn_ECTL_1_REG(port->index), 579 __SHIFTIN(2, XUSB_PADCTL_UPHY_USB3_PADn_ECTL_2_TX_TERM_CTRL), 580 XUSB_PADCTL_UPHY_USB3_PADn_ECTL_2_TX_TERM_CTRL); 581 SETCLR4(sc, XUSB_PADCTL_UPHY_USB3_PADn_ECTL_2_REG(port->index), 582 __SHIFTIN(0xfc, XUSB_PADCTL_UPHY_USB3_PADn_ECTL_2_RX_CTLE), 583 XUSB_PADCTL_UPHY_USB3_PADn_ECTL_2_RX_CTLE); 584 WR4(sc, XUSB_PADCTL_UPHY_USB3_PADn_ECTL_3_REG(port->index), 0xc0077f1f); 585 SETCLR4(sc, XUSB_PADCTL_UPHY_USB3_PADn_ECTL_4_REG(port->index), 586 __SHIFTIN(0x01c7, XUSB_PADCTL_UPHY_USB3_PADn_ECTL_4_RX_CDR_CTRL), 587 XUSB_PADCTL_UPHY_USB3_PADn_ECTL_4_RX_CDR_CTRL); 588 WR4(sc, XUSB_PADCTL_UPHY_USB3_PADn_ECTL_6_REG(port->index), 0xfcf01368); 589 590 SETCLR4(sc, XUSB_PADCTL_ELPG_PROGRAM_1_REG, 591 0, XUSB_PADCTL_ELPG_PROGRAM_1_SSPn_ELPG_CLAMP_EN(port->index)); 592 delay(200); 593 SETCLR4(sc, XUSB_PADCTL_ELPG_PROGRAM_1_REG, 594 0, XUSB_PADCTL_ELPG_PROGRAM_1_SSPn_ELPG_CLAMP_EN_EARLY(port->index)); 595 delay(200); 596 SETCLR4(sc, XUSB_PADCTL_ELPG_PROGRAM_1_REG, 597 0, XUSB_PADCTL_ELPG_PROGRAM_1_SSPn_ELPG_VCORE_DOWN(port->index)); 598 599 SETCLR4(sc, XUSB_PADCTL_VBUS_OC_MAP_REG, 600 XUSB_PADCTL_VBUS_OC_MAP_VBUS_ENABLE(port->index), 0); 601 } 602 603 static void 604 tegra210_xusbpad_configure_hsic_port(struct tegra210_xusbpad_softc *sc, 605 int phandle, const struct tegra210_xusbpad_port *port) 606 { 607 tegra210_xusbpad_enable_vbus(sc, port, phandle); 608 } 609 610 static void 611 tegra210_xusbpad_configure_ports(struct tegra210_xusbpad_softc *sc) 612 { 613 const struct tegra210_xusbpad_port *port; 614 const char *port_name; 615 int phandle, child; 616 617 /* Search for the ports node */ 618 phandle = of_find_firstchild_byname(sc->sc_phandle, "ports"); 619 620 /* Configure ports */ 621 for (child = OF_child(phandle); child; child = OF_peer(child)) { 622 if (!fdtbus_status_okay(child)) 623 continue; 624 port_name = fdtbus_get_string(child, "name"); 625 626 if ((port = tegra210_xusbpad_find_usb2_port(port_name)) != NULL) 627 tegra210_xusbpad_configure_usb2_port(sc, child, port); 628 else if ((port = tegra210_xusbpad_find_usb3_port(port_name)) != NULL) 629 tegra210_xusbpad_configure_usb3_port(sc, child, port); 630 else if ((port = tegra210_xusbpad_find_hsic_port(port_name)) != NULL) 631 tegra210_xusbpad_configure_hsic_port(sc, child, port); 632 else 633 aprint_error_dev(sc->sc_dev, "unsupported port '%s'\n", port_name); 634 } 635 } 636 637 static void 638 tegra210_xusbpad_enable(struct tegra210_xusbpad_softc *sc) 639 { 640 if (sc->sc_enabled) 641 return; 642 643 SETCLR4(sc, XUSB_PADCTL_ELPG_PROGRAM_1_REG, 0, XUSB_PADCTL_ELPG_PROGRAM_1_AUX_MUX_LP0_CLAMP_EN); 644 delay(200); 645 SETCLR4(sc, XUSB_PADCTL_ELPG_PROGRAM_1_REG, 0, XUSB_PADCTL_ELPG_PROGRAM_1_AUX_MUX_LP0_CLAMP_EN_EARLY); 646 delay(200); 647 SETCLR4(sc, XUSB_PADCTL_ELPG_PROGRAM_1_REG, 0, XUSB_PADCTL_ELPG_PROGRAM_1_AUX_MUX_LP0_VCORE_DOWN); 648 649 sc->sc_enabled = true; 650 } 651 652 static void 653 tegra210_xusbpad_sata_enable(device_t dev) 654 { 655 struct tegra210_xusbpad_softc * const sc = device_private(dev); 656 657 tegra210_xusbpad_enable(sc); 658 } 659 660 static void 661 tegra210_xusbpad_xhci_enable(device_t dev) 662 { 663 struct tegra210_xusbpad_softc * const sc = device_private(dev); 664 665 SETCLR4(sc, XUSB_PADCTL_USB2_PAD_MUX_REG, 666 __SHIFTIN(XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB, 667 XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD), 668 XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD); 669 670 tegra210_xusbpad_enable(sc); 671 } 672 673 static const struct tegra_xusbpad_ops tegra210_xusbpad_ops = { 674 .sata_enable = tegra210_xusbpad_sata_enable, 675 .xhci_enable = tegra210_xusbpad_xhci_enable, 676 }; 677 678 static int 679 tegra210_xusbpad_match(device_t parent, cfdata_t cf, void *aux) 680 { 681 const char * const compatible[] = { 682 "nvidia,tegra210-xusb-padctl", 683 NULL 684 }; 685 struct fdt_attach_args * const faa = aux; 686 687 return of_match_compatible(faa->faa_phandle, compatible); 688 } 689 690 static void 691 tegra210_xusbpad_attach(device_t parent, device_t self, void *aux) 692 { 693 struct tegra210_xusbpad_softc * const sc = device_private(self); 694 struct fdt_attach_args * const faa = aux; 695 bus_addr_t addr; 696 bus_size_t size; 697 int error; 698 699 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 700 aprint_error(": couldn't get registers\n"); 701 return; 702 } 703 sc->sc_rst = fdtbus_reset_get(faa->faa_phandle, "padctl"); 704 if (sc->sc_rst == NULL) { 705 aprint_error(": couldn't get reset padctl\n"); 706 return; 707 } 708 709 sc->sc_dev = self; 710 sc->sc_phandle = faa->faa_phandle; 711 sc->sc_bst = faa->faa_bst; 712 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 713 if (error) { 714 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 715 return; 716 } 717 718 aprint_naive("\n"); 719 aprint_normal(": XUSB PADCTL\n"); 720 721 fdtbus_reset_deassert(sc->sc_rst); 722 723 tegra_xusbpad_register(self, &tegra210_xusbpad_ops); 724 725 tegra210_xusbpad_configure_pads(sc, "usb2"); 726 tegra210_xusbpad_configure_pads(sc, "hsic"); 727 tegra210_xusbpad_configure_pads(sc, "pcie"); 728 tegra210_xusbpad_configure_pads(sc, "sata"); 729 730 tegra210_xusbpad_configure_ports(sc); 731 } 732 733 CFATTACH_DECL_NEW(tegra210_xusbpad, sizeof(struct tegra210_xusbpad_softc), 734 tegra210_xusbpad_match, tegra210_xusbpad_attach, NULL, NULL); 735
Indexes created Tue Sep 30 20:09:53 GMT 2025